Random Pattern Generation (includes Pseudorandom Pattern) Patents (Class 714/739)
  • Patent number: 10268638
    Abstract: A database system allows users to specify plan constraint specification that limit choices of execution plans considered by an optimizer of the database system for optimizing database queries. The plan constraint specification specifies attributes of execution plans. The plan constraint specification may identify tables/intermediate results that the plan constraint is applicable to using table names or aliases. The database system applies the plan constraint specification to database queries that match the tables/aliases specified in the plan constraint specification. The database system limits the choice of execution plans evaluated for a database query to execution plans satisfying the attributes specified in an applicable plan constraint specification. The plan constraint specification may specify distribution of a table, a join order for tables, the join mechanism, cardinality of a table or intermediate result, and so on.
    Type: Grant
    Filed: November 11, 2014
    Date of Patent: April 23, 2019
    Assignee: ParAccel LLC
    Inventors: William J. McKenna, Richard L. Cole, Yijou Chen, Sergei Perfilov, Aman Sinha, Eugene Szedenits, Jr.
  • Patent number: 10049763
    Abstract: A semiconductor memory apparatus includes a plurality of stacked semiconductor dies including a first semiconductor die comprising a first internal circuit configured to control input timing of a test control signal that is output as a plurality of delayed test control signals to the plurality of stacked semiconductor dies according to the controlled input timing in response to a test mode signal.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: August 14, 2018
    Assignee: SK hynix Inc.
    Inventors: Chang Hyun Lee, Young Jun Ku
  • Patent number: 10031991
    Abstract: The present disclosure relates to a computer-implemented method for electronic design verification. Embodiments may include receiving an electronic design environment including both a design under test (“DUT”) and a testbench. Embodiments may further include simulating an electronic design associated with the electronic design environment and generating a coverage database associated with the electronic design. Embodiments may include performing coverage analysis of the DUT and testbench using an automated inheritance aware analysis and applying the coverage analysis results to the testbench after simulation.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: July 24, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventors: Praveen Kumar Chhabra, Hemant Gupta, Sharad Gaur, Matthew Aaron Graham, John Laurence Rose, Anupam Singal
  • Patent number: 9992084
    Abstract: A system for testing multiple cable modem/eMTA devices independently and simultaneously using different types of device probes is disclosed. The system employs multiple device probes configured to test various functions and connectivity associated with the device under test, including wireless local area network (WLAN), local area network (LAN), Multimedia Over Coax Alliance (MoCA), DOCSIS, and Foreign Exchange Station (FXS). The system includes real-time, bi-directional/asynchronous communication and interaction between the system components.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: June 5, 2018
    Assignee: Contec, LLC
    Inventors: Samant Kumar, Dinesh Kumar, Shivashankar Diddimani, Gunjan Samaiya, Ina Huh, Jin Ryu
  • Patent number: 9460069
    Abstract: A computer identifies a sample document and annotates the sample document using a plurality of annotators to produce annotations associated with the sample document. The computer determines a plurality of patterns in the sample document based on the annotations. The computer populates a template using the patterns, and varies parts of the patterns in the template to generate test data. The computer identifies a knowledge domain of the sample document and identifies at least one of the annotators based on the knowledge domain of the sample document. The computer determines the observed occurrence count of at least one of the patterns in the sample document, and the likelihood of populating the template using the at least one of the patterns can be proportional to the observed occurrence count.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: October 4, 2016
    Assignee: International Business Machines Corporation
    Inventors: Dhruv A. Bhatt, Kristin E. McNeil, Nitaben A. Patel
  • Patent number: 9383409
    Abstract: A method for implementing a scan chain to test a semiconductor including obtaining an initial structure of the scan chain, determining, according to function modules of the semiconductor corresponding to scan registers on the scan chain, a first scan register pair with backward dependency, adjusting a structure of the scan chain such that the first scan register pair with backward dependency becomes a scan register pair with forward dependency, when a fan-in scan register in the scan register pair with backward dependency belongs to the key subset of the fan-out scan register in the first scan register pair with backward dependency, and determining a key subset of a fan-out scan register in the first scan register pair with backward dependency, wherein when all fan-in scan registers in the key subset reflect a same logic value, an output logic value of a function module connected to the fan-out scan register is fixed.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: July 5, 2016
    Assignee: International Business Machines Corporation
    Inventors: Liang Chen, Guofan Jiang, Teng Lin, Yang Liu
  • Patent number: 9372772
    Abstract: A co-verification method and system are described herein. The co-verification method is able to verify software and hardware at the same time. Constraints are provided to a software compiler which generates programming values. The programming values and stimulus from a verification test bench are utilized to test a design such as a microprocessor.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: June 21, 2016
    Assignee: CAVIUM, INC.
    Inventors: Mohan Balan, Harish Krishnamoorthy, Nimalan Siva, Kishore Badari Atreya
  • Patent number: 9361066
    Abstract: Apparatus and method for a ring oscillator based random number generator with intentional startup delays timed for each ring to provide a uniform initial spreading of the ring oscillator transition edges. This invention adds a controlled incremental delay in the startup of each individual ring within the ring oscillator random number generator. Typically the delay units used in the ring oscillators themselves can be used to get a course delay between the start times of each ring. A subset of the rings start up with a particular course delay and different fine delays such that the transition edges of all the rings are spread out over the oscillation period. This spreading of the transition edges ensures the output of the random number generator are not a predictable sequence of ones and zeros based on a simultaneous startup of all rings at the same time.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: June 7, 2016
    Assignee: The United States of America as represented by the Secretary of the Air Force.
    Inventor: John W. Rooks
  • Patent number: 9335374
    Abstract: Various aspects of the disclosed techniques relate to using dynamic shift for test pattern compression. Scan chains are divided into segments. Non-shift clock cycles are added to one or more segments to make an uncompressible test pattern compressible. The one or more segments may be selected based on compressibility, the number of specified bits and/or the location on the scan chains. A dynamic shift controller may be employed to control the dynamic shift.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: May 10, 2016
    Assignee: Mentor Graphics Corporation
    Inventors: Xijiang Lin, Mark A. Kassab, Janusz Rajski
  • Patent number: 9311488
    Abstract: A system and method for processing electronic devices to determine removal of customer personal information (CPI). An electronic device is connected to a test device. A number of electronic devices including the electronic device are received for determining that the CPI is removed from a number of sources. The number of electronic devices include a number of makes and models of electronic devices. A determination of whether CPI is included on the electronic device is made. An identification of the electronic device is recorded in response to determining that CPI is included on the electronic device. The CPI is cleared form the electronic device in response to determining that the CPI is included on the electronic device. The identification of the electronic devices and metadata is reported in response to determining the CPI was included on the electronic device.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: April 12, 2016
    Assignee: ATC Logistics & Electronics, Inc.
    Inventors: Brian Gventer, Ken Nguyen, Kevin M. Asbury, Joel McCarty, Mike Lowry
  • Patent number: 9239777
    Abstract: System, method, and non-transitory medium for generating a test scenario template from a cluster of similar partial runs of test scenarios involves executing the following: identifying runs of test scenarios run by users on software systems that belong to different organizations; generating partial runs of the test scenarios by extracting from each run of a test scenario data pertaining to a proper subset of the plurality of test steps described in the run; clustering the partial runs of the test scenarios into clusters of similar partial runs; receiving a profile of a user; selecting, based on the profile, from among the clusters a certain cluster suitable for the user; and generating a test scenario template based on partial runs belonging to the certain cluster.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: January 19, 2016
    Assignee: Panaya Ltd.
    Inventors: Yossi Cohen, Mati Cohen, Nurit Dor, Dror Weiss
  • Patent number: 9218271
    Abstract: A method for refining a test plan is provided. The method comprises defining a coverage model including: one or more variables, wherein respective values for the variables are assigned, and one or more definitions for value combinations for said variables with assigned values, wherein zero or more of said value combinations are defined according to one or more restrictions for the purpose of generating a test plan to test a system for which the coverage model is constructed; determining zero or more uncovered value combinations in the test plan; and providing means to update the test plan.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: December 22, 2015
    Assignee: International Business Machines Corporation
    Inventors: Itai Segall, Rachel Tzoref-Brill
  • Patent number: 9178684
    Abstract: In an example, a self-testing integrated circuit (IC) includes N channels i and a controller, where i is an integer from 1 to N. Each channel i may include a clock and data recovery circuit (CDR), a pseudorandom bit stream (PRBS) generator circuit, and a PRBS checker and eye quality monitor (EQM) circuit. The controller may be configured to selectively couple the channels i in a daisy chain during self-testing.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: November 3, 2015
    Assignee: FINISAR CORPORATION
    Inventor: The' Linh Nguyen
  • Patent number: 9152752
    Abstract: An improved compression technique can increase PRPG-based compression by modifying test generation so that justification of certain decision nodes, called xheadlines, is delayed and merged with PRPG seed computation. Xheadlines are defined by gate modification restrictions, dynamic value considerations, and fanout allowance. Before mapping, the xheadlines can be preprocessed. This preprocessing can include transforming XOR xheadlines having shared inputs, augmenting AND/OR xheadlines, and reducing AND/OR xheadlines with common inputs. Mapping can include determining which xheadlines are satisfied by a current seed, which xheadlines can be satisfied by a future seed, and which xheadlines can opportunistically be satisfied by the current seed.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 6, 2015
    Assignee: Synopsys, Inc.
    Inventors: Peter Wohl, John A. Waicukauski
  • Patent number: 9110957
    Abstract: A business intelligence document provides functionality for testing a hypothesis on aggregated data in a business intelligence document (e.g., a spreadsheet-like document), wherein one or more of the input data values and transformation properties are designated as constrained (e.g., invariant or constrained within a range, set, enumeration, or domain). The hypothesis, which is articulated as a data mining assertion, is input through the user interface of the business intelligence document (e.g., via an expression interface or properties of a row, column, or cell) and solved over the aggregated data. The solution is then presented through the user interface of the spreadsheet-like document, such as in a table, graph, histogram, etc.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: August 18, 2015
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Vijay Mital, Gary Shon Katzenberger, Darryl Rubin, David George Green
  • Patent number: 9104815
    Abstract: System, method, and non-transitory medium for ranking similar runs of test scenarios based on unessential test steps in the runs. Runs of test scenarios run by users on software systems that belong to different organizations are clustered to clusters of similar runs. Analysis of a certain selected cluster identifies occurrences of potentially unessential test steps in the similar runs belonging to the cluster. By counting, for each potentially unessential test step, the number of different users that ran a test scenario that includes the potentially unessential test step, it is possible to label certain test steps as verified unessential test steps. A potentially unessential test step may be labeled a verified unessential test step when its corresponding number of different users is below a predetermined threshold. A ranking module utilizes the number of occurrences of verified unessential test steps in runs in order to rank the runs.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: August 11, 2015
    Assignee: Panaya Ltd.
    Inventors: Yossi Cohen, Mati Cohen, Nurit Dor, Dror Weiss
  • Patent number: 9092622
    Abstract: A data processing system having a first processor, a second processor, a local memory of the second processor, and a built-in self-test (BIST) controller of the second processor which can be randomly enabled to perform memory accesses on the local memory of the second processor and which includes a random value generator is provided. The system can perform a method including executing a secure code sequence by the first processor and performing, by the BIST controller of the second processor, BIST memory accesses to the local memory of the second processor in response to the random value generator. Performing the BIST memory accesses is performed concurrently with executing the secure code sequence.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: July 28, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: William C. Moyer, Jeffrey W. Scott
  • Patent number: 9015545
    Abstract: Disclosed is a solid state drive tester which divides the functions of generating and comparing test pattern data and Frame Information Structure (FIS) data with each other into each other to implement the functions as separate logics, so that entire test time is decreased by reducing load of a processor. The solid state drive tester includes a host terminal for receiving a test condition for testing a storage from a user, and a test control unit creating a test pattern corresponding to the test condition, and adaptively selecting an interface according to an interface type of the storage to be tested to test the storage using the test pattern, wherein the test control unit is divided into a control module for controlling the test of the storage and a test execution module for practically executing the test in hardware to test a plurality of storages in real time.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: April 21, 2015
    Assignee: Unitest Inc
    Inventors: Eui Won Lee, Hyo Jin Oh
  • Patent number: 8990669
    Abstract: A linear feedback shift register machine capable of generating periodic sequences and having means for detecting single point errors in the generated sequences.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 24, 2015
    Assignee: The Aerospace Corporation
    Inventors: Rouh T. Bow, Philip A. Dafesh, Clyde E. Edgar, Jr.
  • Patent number: 8923417
    Abstract: Embodiments disclosed herein relate to apparatus and methods of transceiver power noise reduction. One embodiment relates to a method of serial data communication. At a transmitter, data may be encoded by a communication protocol encoder, and the protocol-encoded data may be serialized. The serialized data may be encoded for power-delivery-network noise reduction (PNR) so as to generate PNR-encoded serial data, and the PNR-encoded serial data may be driven onto a communication channel. Other embodiments, aspects, and features are also disclosed.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: December 30, 2014
    Assignee: Altera Corporation
    Inventors: Zhe Li, Hong Shi
  • Patent number: 8892973
    Abstract: A debugging control system using inside-core events as trigger conditions and a method of the same are revealed. The method includes following steps. First set up at least one trigger condition and a search range of the clock cycle according to internal states of a core under debug. Pause clock and recover clock of each clock cycle within the search range. Retrieve data of scan chains of the core under debug by a shift buffer during the clock pausing. Next combine data of the scan chains by a trigger comparator circuit to form trigger signals and check whether the trigger signals satisfy the trigger condition. If the trigger condition is satisfied or the trigger signal is over the search range, the clock is paused continuingly and internal states of the scan chains of the core under debug are output otherwise the core under debug is recovered.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: November 18, 2014
    Assignee: National Cheng Kung University
    Inventors: Kuen-Jong Lee, Jia-Wei Jhou
  • Patent number: 8887015
    Abstract: An arithmetic processor executes analysis processing for analyzing a probability that an output value of the scan flip-flop circuit after the capturing operation becomes a given logical state, and scan chain structure processing for structuring a scan chain for a plurality of scan flip-flop circuits having the same degree of probability that the output value after the capturing operation becomes the given logical state, on the basis of a result of the analyzing processing. The scan chain lower in a transition probability during the scan operation is formed so that a power consumption during a scan test can be reduced.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: November 11, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroyuki Iwata, Jun Matsushima
  • Patent number: 8868992
    Abstract: REUT (Robust Electrical Unified Testing) for memory links is introduced which speeds testing, tool development, and debug. In addition it provides training hooks that have enough performance to be used by BIOS to train parameters and conditions that have not been possible with past implementations. Address pattern generation circuitry is also disclosed.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: October 21, 2014
    Assignee: Intel Corporation
    Inventors: Bryan L. Spry, Theodore Z. Schoenborn, Philip Abraham, Christopher P. Mozak, David G. Ellis, Jay J. Nejedlo, Bruce Querbach, Zvika Greenfield, Rony Ghattas, Jayasekhar Tholiyil, Charles D. Lucas, Christopher E. Yunker
  • Patent number: 8856627
    Abstract: In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: October 7, 2014
    Assignee: Intel Corporation
    Inventors: Steven R. King, Frank L. Berry, Michael E. Kounavis
  • Patent number: 8843797
    Abstract: A method for detecting unstable signatures when testing a VLSI chip that includes adding to an LFSR one or more save and restore registers for storing an initial seed consisting of 0s and 1s; loading the initial seed into the LFSR and one or more save and restore registers; initializing a MISR and running test loops. Upon reaching a predetermined number of test loops, moving a signature of the MISR to a shadow register; then, performing a signature stability test by loading the initial seed to the LFSR; executing the predetermined number of BIST test loops, and comparing a resulting MISR signature for differences versus a previous signature stored in a MISR save and restore register, wherein unloading is performed by way of serial MISR unloads and single bit XORs.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: September 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Franco Motika, Raymond J. Kurtulik, John D. Parker
  • Patent number: 8832513
    Abstract: A processor link that couples a first processor and a second processor is selected for validation and a plurality of communication parameter settings associated with the first and the second processors is identified. The first and the second processors are successively configured with each of the communication parameter settings. One or more test data pattern(s) are provided from the first processor to the second processor in accordance with the communication parameter setting. Performance measurements associated with the selected processor link and with the communication parameter setting are determined based, at least in part, on the test data pattern as received at the second processor. One of the communication parameter settings that is associated with the highest performance measurements is selected. The selected communication parameter setting is applied to the first and the second processors for subsequent communication between the first and the second processors via the processor link.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: September 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Robert W. Berry, Anand Haridass, Prasanna Jayaraman
  • Patent number: 8826092
    Abstract: A processor link that couples a first processor and a second processor is selected for validation and a plurality of communication parameter settings associated with the first and the second processors is identified. The first and the second processors are successively configured with each of the communication parameter settings. One or more test data pattern(s) are provided from the first processor to the second processor in accordance with the communication parameter setting. Performance measurements associated with the selected processor link and with the communication parameter setting are determined based, at least in part, on the test data pattern as received at the second processor. One of the communication parameter settings that is associated with the highest performance measurements is selected. The selected communication parameter setting is applied to the first and the second processors for subsequent communication between the first and the second processors via the processor link.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: September 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Robert W. Berry, Jr., Anand Haridass, Prasanna Jayaraman
  • Patent number: 8819502
    Abstract: Exemplary method, system, and computer program embodiments for performing deterministic data verification by a storage controller are provided. Each of a plurality of concurrent write tasks is configured to be placed in a plurality of overlapping data storage ranges by performing at least one of: implementing a data generation function for generating pseudo-random data using a data seed, and generating a range map, the range map utilized as a lookup data structure to verify a chronological order for performing the plurality of concurrent write tasks, wherein a data address space is first designated in the range map as undetermined. Each of a plurality of read tasks is analyzed by comparing data read from a sub range in the plurality of overlapping data storage ranges against the data seed associated with the sub range.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: August 26, 2014
    Assignee: International Business Machines Corporation
    Inventors: Yair G. Chuchem, Adi Goldfarb, Zohar Zilberman
  • Patent number: 8812918
    Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: August 19, 2014
    Assignee: Rambus Inc.
    Inventors: Jared Zerbe, Pak Shing Chau, William Franklin Stonecypher
  • Patent number: 8775911
    Abstract: In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: July 8, 2014
    Assignee: Intel Corporation
    Inventors: Steven R. King, Frank L. Berry, Michael E. Kounavis
  • Patent number: 8775912
    Abstract: In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: July 8, 2014
    Assignee: Intel Corporation
    Inventors: Steven R. King, Frank L. Berry, Michael E. Kounavis
  • Patent number: 8762803
    Abstract: A method and circuit for implementing enhanced Logic Built In Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides are provided. A plurality of pseudo random pattern generators (PRPGs) is provided, each PRPG comprising one or more linear feedback shift registers (LFSRs). Each respective PRPG includes an XOR feedback input selectively receiving a feedback from another PRPG and predefined inputs of the respective PRPG. A respective XOR spreading function is coupled to a plurality of outputs of each PRPG with predefined XOR spreading functions applying test pseudo random pattern inputs to LBIST channels for LBIST diagnostics.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: June 24, 2014
    Assignee: International Business Machines Corporation
    Inventors: Steven M. Douskey, Ryan A. Fitch, Michael J. Hamilton, Amanda R. Kaufer
  • Patent number: 8756469
    Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: June 17, 2014
    Assignee: Rambus Inc.
    Inventors: Jared Zerbe, Pak Shing Chau, William Franklin Stonecypher
  • Patent number: 8689069
    Abstract: Disclosed are representative examples of methods, apparatus, and systems for generating test patterns targeting multiple faults using Boolean Satisfiability (SAT)-based test pattern generation methods. A SAT instance is constructed based on the circuit design information and a set of faults being targeted. A SAT solving engine is applied to the SAT instance to search for a test pattern for detecting the set of faults. The SAT instance or the SAT solving engine may be modified so that the SAT solving engine will search for a test pattern for detecting a maximum number of faults in the set of faults.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: April 1, 2014
    Assignee: Mentor Graphics Corporation
    Inventors: Rene Krenz-Baath, Andreas Glowatz, Friedrich Hapke
  • Patent number: 8689067
    Abstract: A system and method for detecting transition delay faults decouples the test enable pins of the clock gating cells from other elements in the circuitry. The test enable pins are controlled during test mode by a unique signal, allowing the tester to independently control the clock gating logic of the circuitry. By being able to ungate the clock, the tester can ensure that the two clock pulses needed to check for transition delay faults will always be present.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: April 1, 2014
    Assignee: Marvell International Ltd.
    Inventor: Darren Bertanzetti
  • Patent number: 8689071
    Abstract: A test system includes a supervisor unit coupled to a control interface; the control interface coupled to first and second test modules, each test module comprising a first logic module to test macro blocking errors; a second logic module to perform optical character recognition; a third logic module to perform signal to noise ratio measurement; and a fourth logic module to perform random noise measurement; each test module coupled to a device under test, the four logic modules applied to test a menu-driven video decoding device.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: April 1, 2014
    Assignee: Contec Holdings, Ltd.
    Inventors: Vladzimir Valakh, Vicente Miranda, Darby Racey
  • Patent number: 8683280
    Abstract: Aspects of the invention relate to low power BIST-based testing. A low power test generator may comprise a pseudo-random pattern generator unit, a toggle control unit configured to generate toggle control data based on bit sequence data generated by the pseudo-random pattern generator unit, and a hold register unit configured to generate low power test pattern data by replacing, based on the toggle control data received from the toggle control unit, data from some or all of outputs of the pseudo-random pattern generator unit with constant values during various time periods. The low power test generator may further comprise a phase shifter configured to combine bits of the low power test pattern data for driving scan chains.
    Type: Grant
    Filed: April 19, 2012
    Date of Patent: March 25, 2014
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Benoit Nadeau-Dostie
  • Patent number: 8627163
    Abstract: Improved apparatus, systems and methods, such as those for testing an error correction code (ECC) encoder/decoder for solid-state memory devices, are provided. In one or more embodiments, the improved systems and methods deliberately inject errors into memory storage areas of memory devices to test the operation of the ECC encoder/decoder.
    Type: Grant
    Filed: March 25, 2008
    Date of Patent: January 7, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Yutaka Ito, Adrian Drexler, Brandi Jones
  • Patent number: 8572447
    Abstract: A method of testing a data connection using at least one test sequence, the method including providing a first bit sequence by a first generator; duplicating the first bit sequence to generate a second bit sequence identical to the first; and generating the at least one test sequence based on the first and second bit sequences and transmitting the at least one test sequence over a data connection to be tested.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: October 29, 2013
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventor: Hervé Le-Gall
  • Patent number: 8549369
    Abstract: A semiconductor-based test device includes a plurality of testing clusters and a pseudorandom global stimulus source coupled to the testing clusters. Each testing cluster includes a plurality of data registers and logic elements configured to perform random logic functions for generating test data for the plurality of data registers. The pseudorandom global stimulus source generates a pseudorandom binary stimulus for the logic elements. At least some of the plurality of testing clusters are coupled together to support inter-cluster fan-out and fan-in of data register output.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: October 1, 2013
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventor: Christian Haufe
  • Patent number: 8533394
    Abstract: Instruction fetch unit (IFU) verification is improved by dynamically monitoring the current state of the IFU model and detecting any predetermined states of interest. The instruction address sequence is automatically modified to force a selected address to be fetched next by the IFU model. The instruction address sequence may be modified by inserting one or more new instruction addresses, or by jumping to a non-sequential address in the instruction address sequence. In exemplary implementations, the selected address is a corresponding address for an existing instruction already loaded in the IFU cache, or differs only in a specific field from such an address. The instruction address control is preferably accomplished without violating any rules of the processor architecture by sending a flush signal to the IFU model and overwriting an address register corresponding to a next address to be fetched.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: September 10, 2013
    Assignee: International Business Machines Corporation
    Inventors: Akash V. Giri, Darin M. Greene, Alan G. Singletary
  • Patent number: 8515416
    Abstract: In a radio device such as a receiver or transceiver, a test operation can be performed to determine performance. A received signal can be processed to obtain demodulated samples, which can be provided to a logic to perform a logic operation on the samples to generate a logic output. A storage such as a counter or other mechanism is coupled to the logic to store a count of a number of the logic outputs having an error.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: August 20, 2013
    Assignee: Silicon Laboratories Inc
    Inventor: Hendricus De Ruijter
  • Patent number: 8495440
    Abstract: A pseudo random bit stream generator is disclosed which has a fully programmable pseudo random polynomial up to the supported width of the CSRs, fully programmable tap selection for providing any specified combination of generator state taps, and fully programmable parallel sequence generation which determines the number of sequential bits calculated and how much the sequence generator advances per clock.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: July 23, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Glenn A. Dearth
  • Patent number: 8495176
    Abstract: A content management system (CMS) includes a value-add application with a first set of XML content services, one or more dedicated XML processing servers with a second and other sets of XML content services, and a core CMS with a third set of XML content services. The content management system may be designed to provide XML content services at any of these three tiers of processing. A first threshold is defined that allows the value-add application to determine when to offload XML content services to a dedicated XML processing server. A second threshold is defined that allows the core CMS to determine when to offload XML content services to a dedicated XML processing server. Callback services are included that allow each tier of XML content services to send or receive additional information to complete the XML processing. The result is a content management system that is very powerful and flexible.
    Type: Grant
    Filed: August 18, 2010
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: David G. Herbeck, John E. Petri
  • Patent number: 8489970
    Abstract: A receiver includes a seed recovery module and a pseudo-random binary sequence generator. The seed recovery module is configured to receive a pseudo-random binary sequence and a signal including a seed value, recover the seed value from the signal using the pseudo-random binary sequence, and determine a likelihood that a bit of the seed value was recovered accurately. The pseudo-random binary sequence generator is configured to generate the pseudo-random binary sequence, and adjust the pseudo-random binary sequence based on the likelihood until the likelihood is greater than a threshold.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: July 16, 2013
    Assignee: Marvell International Ltd.
    Inventors: Jamal Riani, Haoli Qian
  • Patent number: 8478940
    Abstract: Instruction fetch unit (IFU) verification is improved by dynamically monitoring the current state of the IFU model and detecting any predetermined states of interest. The instruction address sequence is automatically modified to force a selected address to be fetched next by the IFU model. The instruction address sequence may be modified by inserting one or more new instruction addresses, or by jumping to a non-sequential address in the instruction address sequence. In exemplary implementations, the selected address is a corresponding address for an existing instruction already loaded in the IFU cache, or differs only in a specific field from such an address. The instruction address control is preferably accomplished without violating any rules of the processor architecture by sending a flush signal to the IFU model and overwriting an address register corresponding to a next address to be fetched.
    Type: Grant
    Filed: June 2, 2009
    Date of Patent: July 2, 2013
    Assignee: International Business Machines Corporation
    Inventors: Akash V. Giri, Darin M. Greene, Alan G. Singletary
  • Patent number: 8458540
    Abstract: A integrated circuit include: a first selection circuit selecting first data from input-data or scan-data, scan-data being for performing a diagnosis of a combinational circuit, input-data being received from a combinational circuit; a first latch circuit holding first data as first output-data in accordance with a first signal; a second latch circuit holding first output-data as second output-data in accordance with which of the first signal and a second signal, the second signal being used to force the second latch circuit to hold first output-data; a third latch circuit holding first output-data as third output-data in accordance with which of the first signal and a third signal, the third signal being used to force the third latch circuit to hold first output-data; and a second selection circuit selecting second data from among the data which include second output-data and third output-data.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: June 4, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Ryoichi Inagawa
  • Patent number: 8443246
    Abstract: A system and method for detecting transition delay faults decouples the test enable pins of the clock gating cells from other elements in the circuitry. The test enable pins are controlled during test mode by a unique signal, allowing the tester to independently control the clock gating logic of the circuitry. By being able to ungate the clock, the tester can ensure that the two clock pulses needed to check for transition delay faults will always be present.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: May 14, 2013
    Assignee: Marvell International Ltd.
    Inventor: Darren Bertanzetti
  • Patent number: 8429473
    Abstract: An improved compression technique can increase PRPG-based compression by modifying test generation so that justification of certain decision nodes, called xheadlines, is delayed and merged with PRPG seed computation. Xheadlines are defined by gate modification restrictions, dynamic value considerations, and fanout allowance. Before mapping, the xheadlines can be preprocessed. This preprocessing can include transforming XOR xheadlines having shared inputs, augmenting AND/OR xheadlines, and reducing AND/OR xheadlines with common inputs. Mapping can include determining which xheadlines are satisfied by a current seed, which xheadlines can be satisfied by a future seed, and which xheadlines can opportunistically be satisfied by the current seed.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: April 23, 2013
    Assignee: Synopsys, Inc.
    Inventors: Peter Wohl, John A. Waicukauski
  • Patent number: 8413024
    Abstract: In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: April 2, 2013
    Assignee: Intel Corporation
    Inventors: Steven R. King, Frank Berry, Michael E. Kounavis