Abstract: A method of scan-chain testing of an integrated circuit device having a plurality of respective scan-chain paths, at least some of the respective scan-chain paths being designated as having resource constraints, includes propagating a respective scan-chain data pattern through each of the respective scan-chain paths, and gating each respective scan-chain path designated as having resource constraints, to reduce a rate of scan-chain data propagation through the respective scan-chain path, without gating any scan-chain path not designated as having resource constraints. Scan-chain paths may be designated as having resource constraints because of high power consumption or data congestion.

Abstract: Techniques that facilitate orchestration engine blueprint aspects for hybrid cloud composition are provided. In one example, a system includes a blueprint component and a hybrid cloud composition component. The blueprint component determines one or more blueprint-level aspects for a blueprint associated with a cloud-based computing platform. The one or more blueprint-level aspects are indicative of encoded information for one or more features associated with one or more computing resources for the cloud-based computing platform. The hybrid cloud composition component determines a set of resource definitions for the cloud-based computing platform based on the one or more blueprint-level aspects.

Abstract: A method for processing data stored in a memory unit. The method includes the following steps: ascertaining a randomly or pseudo-randomly formed test pattern, which characterizes at least one first subarea of a memory area of the memory unit, forming, as a function of the test pattern, a test variable associated with data stored in the at least one first subarea.

Abstract: A built-in self-test (BIST) method includes providing expanded test patterns to a logic circuit under test, generating a first signature based on a response of the logic circuit to the expanded test patterns, generating a second signature based on the first signature, wherein the second signature is a compressed version of the first signature, selecting one of the first signature or the second signature in response to a control signal, comparing the selected one of the first signature or the second signature to an expected signature, and, based on the comparison of the selected one of the first signature or the second signature to the expected signature, determining that the logic circuit passes or fails BIST.

Abstract: The present disclosure describes various embodiments of systems, apparatuses, and methods for detecting a Trojan inserted integrated circuit design using delay-based side channel analysis. In one such embodiment, an automated test generation algorithm produces test patterns that are likely to activate trigger conditions and change critical paths of an integrated circuit design.

Abstract: Provided are scan device and method of diagnosing scan chain fault. The scan device for diagnosing a fault includes a scan partition including a plurality of scan chains which include path control scan flipflops connected to scan flipflops in cascade. In the scan partition, connection paths of the scan flipflops are controllable. The connection paths of the path control scan flipflops are controlled to detect a position of a fault such that a fault range in the scan partition is reduced to diagnose the fault.

Abstract: The invention discloses an extended joint test action group based controller and a method for functional debugging using the extended joint test action group based controller. The object of the invention to lower the power dissipation (dynamic and leakage) but providing the same functionality of the testing and debugging procedures at the same time will be solved by an extended joint test action group (JTAG) controller for testing flip-flops of a register of an integrated circuit (IC) using a design for testing scan infrastructure on the IC which comprises at least one scan chain, wherein an external debugger is connected to the design for testing scan infrastructure via the JTAG controller which is extended by a debug controller, whereas a feedback loop is formed from an output of the scan chain to an input multiplexer of the scan chain which is activated according to the extended JTAG controller.

Abstract: An extended joint test action group based controller and a method of use allows easier testing of integrated circuits by reducing the power dissipation of an IC. The extended joint test action group (JTAG) controller tests internal storage elements that form digital units in an integrated circuit (IC) use a design for testing scan infrastructure on the IC, wherein the JTAG controller is extended by an overall reset generator for all digital units of the IC, and a finite state machine controls the overall reset generator. In reset mode the JTAG controller stops the at least one clock module in supplying the digital units that should be reset. It then sets all scan chains in test mode and switches the input multiplexers into reset mode; and then controls the number of shift clock cycles for shifting in the reset value to the flip-flops in the scan chain, respectively.

Abstract: A method for simulating different traffic situations for an autonomous or semiautonomous test vehicle. The method includes the simulated driving of the test vehicle through a simulated road network, and the simulated randomized driving of other vehicles through the simulated road network. The method also includes the capture of vehicle driving parameters. Further according to the method, there is a determination of whether a predefined traffic situation is satisfied by the test vehicle and at least one of the other vehicles, the at least one other vehicle being within a test zone around the test vehicle. Where the predefined traffic situation is satisfied, randomized driving of the at least one other vehicle can be stopped, and the at least one other vehicle can be made to perform a predetermined driving maneuver. The predetermined driving maneuver can provoke a reaction by the test vehicle.

Abstract: According to one embodiment, a storage device includes a nonvolatile memory and a control circuit. The nonvolatile memory includes a plurality of storage blocks, each including a shift register. The control circuit controls writing and reading of data to and from the nonvolatile memory. The control circuit is configured to: read target data from a first storage block of the plurality of storage blocks; and write the target data read from the first storage block to a second storage block of the plurality of storage blocks, the second storage block being different from the first storage block.

Abstract: A trace subsystem of an emulation system may generate differential frame data based upon successive frames. If one compression mode, the trace subsystem may set a flag bit and store differential frame data if there is at least one non-zero bit in the differential frame data. If the differential frame data includes only zero bits, the trace subsystem may set the flag bit without storing the frame data. In another compression mode, the computer may further compress the differential data if the frame data includes one (one-hot) or two (two-hot) non-zero bits. The controller may set flag bits to indicate one of all-zeroes, one-hot, two-hot, and random data conditions (more than two non-zero bits). For one-hot or two-hot conditions, the controller may store bits indicating the positions of the non-zero bits. For random data conditions, the controller may store the entire differential frame.

Abstract: Generating instructions, in particular for mailbox verification in a simulation environment. A sequence of instructions is received, as well as selection data representative of a plurality of commands including a special command. Repeatedly selecting one of the plurality of commands and outputting an instruction based on the selected command. The outputting of an instruction includes outputting a next instruction in the sequence of instructions if the selected command is the special command, and outputting an instruction associated with the command if the selected command is not the special command.

Abstract: The present disclosure is directed towards electronic circuit design and verification. Embodiments may include receiving, using a processor, source code corresponding to at least a portion of an electronic design and generating at least one coverage model for each of a dynamic verification and a formal verification. The method may further include determining a formal data set including stimuli coverage status, cone of influence coverage status, and proof coverage status and consolidating the formal data set using a user-programmable consolidation function to generate a combined formal coverage data set.

Abstract: A method and system of determining whether a specification is an accurate representation of an application program interface (API) is provided. The specification is received electronically over a network. Service calls to be tested are identified based on the specification. A test case is created for each of the identified service calls. A sequence is created for the test cases. A test plan is generated based on the created sequence. The generated test plan is executed. Upon identifying an error in response to the executed test plan, a notification is generated, indicating that the specification is not an accurate representation of the API.

Abstract: A database system allows users to specify plan constraint specification that limit choices of execution plans considered by an optimizer of the database system for optimizing database queries. The plan constraint specification specifies attributes of execution plans. The plan constraint specification may identify tables/intermediate results that the plan constraint is applicable to using table names or aliases. The database system applies the plan constraint specification to database queries that match the tables/aliases specified in the plan constraint specification. The database system limits the choice of execution plans evaluated for a database query to execution plans satisfying the attributes specified in an applicable plan constraint specification. The plan constraint specification may specify distribution of a table, a join order for tables, the join mechanism, cardinality of a table or intermediate result, and so on.

Abstract: A semiconductor memory apparatus includes a plurality of stacked semiconductor dies including a first semiconductor die comprising a first internal circuit configured to control input timing of a test control signal that is output as a plurality of delayed test control signals to the plurality of stacked semiconductor dies according to the controlled input timing in response to a test mode signal.

Abstract: The present disclosure relates to a computer-implemented method for electronic design verification. Embodiments may include receiving an electronic design environment including both a design under test (“DUT”) and a testbench. Embodiments may further include simulating an electronic design associated with the electronic design environment and generating a coverage database associated with the electronic design. Embodiments may include performing coverage analysis of the DUT and testbench using an automated inheritance aware analysis and applying the coverage analysis results to the testbench after simulation.

Abstract: A system for testing multiple cable modem/eMTA devices independently and simultaneously using different types of device probes is disclosed. The system employs multiple device probes configured to test various functions and connectivity associated with the device under test, including wireless local area network (WLAN), local area network (LAN), Multimedia Over Coax Alliance (MoCA), DOCSIS, and Foreign Exchange Station (FXS). The system includes real-time, bi-directional/asynchronous communication and interaction between the system components.

Abstract: A computer identifies a sample document and annotates the sample document using a plurality of annotators to produce annotations associated with the sample document. The computer determines a plurality of patterns in the sample document based on the annotations. The computer populates a template using the patterns, and varies parts of the patterns in the template to generate test data. The computer identifies a knowledge domain of the sample document and identifies at least one of the annotators based on the knowledge domain of the sample document. The computer determines the observed occurrence count of at least one of the patterns in the sample document, and the likelihood of populating the template using the at least one of the patterns can be proportional to the observed occurrence count.

Abstract: A method for implementing a scan chain to test a semiconductor including obtaining an initial structure of the scan chain, determining, according to function modules of the semiconductor corresponding to scan registers on the scan chain, a first scan register pair with backward dependency, adjusting a structure of the scan chain such that the first scan register pair with backward dependency becomes a scan register pair with forward dependency, when a fan-in scan register in the scan register pair with backward dependency belongs to the key subset of the fan-out scan register in the first scan register pair with backward dependency, and determining a key subset of a fan-out scan register in the first scan register pair with backward dependency, wherein when all fan-in scan registers in the key subset reflect a same logic value, an output logic value of a function module connected to the fan-out scan register is fixed.

Abstract: A co-verification method and system are described herein. The co-verification method is able to verify software and hardware at the same time. Constraints are provided to a software compiler which generates programming values. The programming values and stimulus from a verification test bench are utilized to test a design such as a microprocessor.

Abstract: Apparatus and method for a ring oscillator based random number generator with intentional startup delays timed for each ring to provide a uniform initial spreading of the ring oscillator transition edges. This invention adds a controlled incremental delay in the startup of each individual ring within the ring oscillator random number generator. Typically the delay units used in the ring oscillators themselves can be used to get a course delay between the start times of each ring. A subset of the rings start up with a particular course delay and different fine delays such that the transition edges of all the rings are spread out over the oscillation period. This spreading of the transition edges ensures the output of the random number generator are not a predictable sequence of ones and zeros based on a simultaneous startup of all rings at the same time.

Abstract: Various aspects of the disclosed techniques relate to using dynamic shift for test pattern compression. Scan chains are divided into segments. Non-shift clock cycles are added to one or more segments to make an uncompressible test pattern compressible. The one or more segments may be selected based on compressibility, the number of specified bits and/or the location on the scan chains. A dynamic shift controller may be employed to control the dynamic shift.

Abstract: A system and method for processing electronic devices to determine removal of customer personal information (CPI). An electronic device is connected to a test device. A number of electronic devices including the electronic device are received for determining that the CPI is removed from a number of sources. The number of electronic devices include a number of makes and models of electronic devices. A determination of whether CPI is included on the electronic device is made. An identification of the electronic device is recorded in response to determining that CPI is included on the electronic device. The CPI is cleared form the electronic device in response to determining that the CPI is included on the electronic device. The identification of the electronic devices and metadata is reported in response to determining the CPI was included on the electronic device.

Abstract: System, method, and non-transitory medium for generating a test scenario template from a cluster of similar partial runs of test scenarios involves executing the following: identifying runs of test scenarios run by users on software systems that belong to different organizations; generating partial runs of the test scenarios by extracting from each run of a test scenario data pertaining to a proper subset of the plurality of test steps described in the run; clustering the partial runs of the test scenarios into clusters of similar partial runs; receiving a profile of a user; selecting, based on the profile, from among the clusters a certain cluster suitable for the user; and generating a test scenario template based on partial runs belonging to the certain cluster.

Abstract: A method for refining a test plan is provided. The method comprises defining a coverage model including: one or more variables, wherein respective values for the variables are assigned, and one or more definitions for value combinations for said variables with assigned values, wherein zero or more of said value combinations are defined according to one or more restrictions for the purpose of generating a test plan to test a system for which the coverage model is constructed; determining zero or more uncovered value combinations in the test plan; and providing means to update the test plan.

Abstract: In an example, a self-testing integrated circuit (IC) includes N channels i and a controller, where i is an integer from 1 to N. Each channel i may include a clock and data recovery circuit (CDR), a pseudorandom bit stream (PRBS) generator circuit, and a PRBS checker and eye quality monitor (EQM) circuit. The controller may be configured to selectively couple the channels i in a daisy chain during self-testing.

Abstract: An improved compression technique can increase PRPG-based compression by modifying test generation so that justification of certain decision nodes, called xheadlines, is delayed and merged with PRPG seed computation. Xheadlines are defined by gate modification restrictions, dynamic value considerations, and fanout allowance. Before mapping, the xheadlines can be preprocessed. This preprocessing can include transforming XOR xheadlines having shared inputs, augmenting AND/OR xheadlines, and reducing AND/OR xheadlines with common inputs. Mapping can include determining which xheadlines are satisfied by a current seed, which xheadlines can be satisfied by a future seed, and which xheadlines can opportunistically be satisfied by the current seed.

Abstract: A business intelligence document provides functionality for testing a hypothesis on aggregated data in a business intelligence document (e.g., a spreadsheet-like document), wherein one or more of the input data values and transformation properties are designated as constrained (e.g., invariant or constrained within a range, set, enumeration, or domain). The hypothesis, which is articulated as a data mining assertion, is input through the user interface of the business intelligence document (e.g., via an expression interface or properties of a row, column, or cell) and solved over the aggregated data. The solution is then presented through the user interface of the spreadsheet-like document, such as in a table, graph, histogram, etc.

Abstract: System, method, and non-transitory medium for ranking similar runs of test scenarios based on unessential test steps in the runs. Runs of test scenarios run by users on software systems that belong to different organizations are clustered to clusters of similar runs. Analysis of a certain selected cluster identifies occurrences of potentially unessential test steps in the similar runs belonging to the cluster. By counting, for each potentially unessential test step, the number of different users that ran a test scenario that includes the potentially unessential test step, it is possible to label certain test steps as verified unessential test steps. A potentially unessential test step may be labeled a verified unessential test step when its corresponding number of different users is below a predetermined threshold. A ranking module utilizes the number of occurrences of verified unessential test steps in runs in order to rank the runs.

Abstract: A data processing system having a first processor, a second processor, a local memory of the second processor, and a built-in self-test (BIST) controller of the second processor which can be randomly enabled to perform memory accesses on the local memory of the second processor and which includes a random value generator is provided. The system can perform a method including executing a secure code sequence by the first processor and performing, by the BIST controller of the second processor, BIST memory accesses to the local memory of the second processor in response to the random value generator. Performing the BIST memory accesses is performed concurrently with executing the secure code sequence.

Abstract: Disclosed is a solid state drive tester which divides the functions of generating and comparing test pattern data and Frame Information Structure (FIS) data with each other into each other to implement the functions as separate logics, so that entire test time is decreased by reducing load of a processor. The solid state drive tester includes a host terminal for receiving a test condition for testing a storage from a user, and a test control unit creating a test pattern corresponding to the test condition, and adaptively selecting an interface according to an interface type of the storage to be tested to test the storage using the test pattern, wherein the test control unit is divided into a control module for controlling the test of the storage and a test execution module for practically executing the test in hardware to test a plurality of storages in real time.

Abstract: A linear feedback shift register machine capable of generating periodic sequences and having means for detecting single point errors in the generated sequences.

Abstract: Embodiments disclosed herein relate to apparatus and methods of transceiver power noise reduction. One embodiment relates to a method of serial data communication. At a transmitter, data may be encoded by a communication protocol encoder, and the protocol-encoded data may be serialized. The serialized data may be encoded for power-delivery-network noise reduction (PNR) so as to generate PNR-encoded serial data, and the PNR-encoded serial data may be driven onto a communication channel. Other embodiments, aspects, and features are also disclosed.

Abstract: A debugging control system using inside-core events as trigger conditions and a method of the same are revealed. The method includes following steps. First set up at least one trigger condition and a search range of the clock cycle according to internal states of a core under debug. Pause clock and recover clock of each clock cycle within the search range. Retrieve data of scan chains of the core under debug by a shift buffer during the clock pausing. Next combine data of the scan chains by a trigger comparator circuit to form trigger signals and check whether the trigger signals satisfy the trigger condition. If the trigger condition is satisfied or the trigger signal is over the search range, the clock is paused continuingly and internal states of the scan chains of the core under debug are output otherwise the core under debug is recovered.

Abstract: An arithmetic processor executes analysis processing for analyzing a probability that an output value of the scan flip-flop circuit after the capturing operation becomes a given logical state, and scan chain structure processing for structuring a scan chain for a plurality of scan flip-flop circuits having the same degree of probability that the output value after the capturing operation becomes the given logical state, on the basis of a result of the analyzing processing. The scan chain lower in a transition probability during the scan operation is formed so that a power consumption during a scan test can be reduced.

Abstract: REUT (Robust Electrical Unified Testing) for memory links is introduced which speeds testing, tool development, and debug. In addition it provides training hooks that have enough performance to be used by BIOS to train parameters and conditions that have not been possible with past implementations. Address pattern generation circuitry is also disclosed.

Abstract: In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.

Abstract: A method for detecting unstable signatures when testing a VLSI chip that includes adding to an LFSR one or more save and restore registers for storing an initial seed consisting of 0s and 1s; loading the initial seed into the LFSR and one or more save and restore registers; initializing a MISR and running test loops. Upon reaching a predetermined number of test loops, moving a signature of the MISR to a shadow register; then, performing a signature stability test by loading the initial seed to the LFSR; executing the predetermined number of BIST test loops, and comparing a resulting MISR signature for differences versus a previous signature stored in a MISR save and restore register, wherein unloading is performed by way of serial MISR unloads and single bit XORs.

Abstract: A processor link that couples a first processor and a second processor is selected for validation and a plurality of communication parameter settings associated with the first and the second processors is identified. The first and the second processors are successively configured with each of the communication parameter settings. One or more test data pattern(s) are provided from the first processor to the second processor in accordance with the communication parameter setting. Performance measurements associated with the selected processor link and with the communication parameter setting are determined based, at least in part, on the test data pattern as received at the second processor. One of the communication parameter settings that is associated with the highest performance measurements is selected. The selected communication parameter setting is applied to the first and the second processors for subsequent communication between the first and the second processors via the processor link.

Abstract: A processor link that couples a first processor and a second processor is selected for validation and a plurality of communication parameter settings associated with the first and the second processors is identified. The first and the second processors are successively configured with each of the communication parameter settings. One or more test data pattern(s) are provided from the first processor to the second processor in accordance with the communication parameter setting. Performance measurements associated with the selected processor link and with the communication parameter setting are determined based, at least in part, on the test data pattern as received at the second processor. One of the communication parameter settings that is associated with the highest performance measurements is selected. The selected communication parameter setting is applied to the first and the second processors for subsequent communication between the first and the second processors via the processor link.

Abstract: Exemplary method, system, and computer program embodiments for performing deterministic data verification by a storage controller are provided. Each of a plurality of concurrent write tasks is configured to be placed in a plurality of overlapping data storage ranges by performing at least one of: implementing a data generation function for generating pseudo-random data using a data seed, and generating a range map, the range map utilized as a lookup data structure to verify a chronological order for performing the plurality of concurrent write tasks, wherein a data address space is first designated in the range map as undetermined. Each of a plurality of read tasks is analyzed by comparing data read from a sub range in the plurality of overlapping data storage ranges against the data seed associated with the sub range.

Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

Abstract: In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.

Abstract: A method and circuit for implementing enhanced Logic Built In Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides are provided. A plurality of pseudo random pattern generators (PRPGs) is provided, each PRPG comprising one or more linear feedback shift registers (LFSRs). Each respective PRPG includes an XOR feedback input selectively receiving a feedback from another PRPG and predefined inputs of the respective PRPG. A respective XOR spreading function is coupled to a plurality of outputs of each PRPG with predefined XOR spreading functions applying test pseudo random pattern inputs to LBIST channels for LBIST diagnostics.

Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

Abstract: A test system includes a supervisor unit coupled to a control interface; the control interface coupled to first and second test modules, each test module comprising a first logic module to test macro blocking errors; a second logic module to perform optical character recognition; a third logic module to perform signal to noise ratio measurement; and a fourth logic module to perform random noise measurement; each test module coupled to a device under test, the four logic modules applied to test a menu-driven video decoding device.

Abstract: Disclosed are representative examples of methods, apparatus, and systems for generating test patterns targeting multiple faults using Boolean Satisfiability (SAT)-based test pattern generation methods. A SAT instance is constructed based on the circuit design information and a set of faults being targeted. A SAT solving engine is applied to the SAT instance to search for a test pattern for detecting the set of faults. The SAT instance or the SAT solving engine may be modified so that the SAT solving engine will search for a test pattern for detecting a maximum number of faults in the set of faults.

Abstract: A system and method for detecting transition delay faults decouples the test enable pins of the clock gating cells from other elements in the circuitry. The test enable pins are controlled during test mode by a unique signal, allowing the tester to independently control the clock gating logic of the circuitry. By being able to ungate the clock, the tester can ensure that the two clock pulses needed to check for transition delay faults will always be present.