Abstract: A method and system for efficiently coding test pattern for ICs in scan design and build-in linear feedback shift register (LFSR) for pseudo-random pattern generation. In an initialization procedure, a novel LFSR logic model is generated and integrated into the system for test data generation and test vector compression. In a test data generation procedure, test vectors are specified and compressed using the LFSR logic model. Every single one of the test vectors is compressed independently from the others. The result, however, may be presented all at once and subsequently provided to the user or another system for further processing or implementing in an integrated circuit to be tested. According to the present invention a test vector containing 0/1-values for, e.g., up to 500.000 shift registers and having, e.g., about 50 so called care-bits can be compressed to a compact pattern code of the number of care-bits, i.e., 50 bits for the example of 50 care-bits.

Abstract: There is provided a test system that tests a device under test.

Abstract: According to some embodiments, provided are a pseudo-random sequence generator to generate a pseudo-random sequence of data values, a decoder to receive compressed weight values and to generate decompressed weight values, and a weighting unit to receive the pseudo-random sequence of data values, to receive the decompressed weight values and to weight the pseudo-random sequence of data values based on the decompressed weight values.

Abstract: Devices and methods are provided for testing various types of smart cards including contact, contactless, and hybrid type (contact/contactless) smart cards. A test device includes a logic tester, a contactless interface unit, and a contact interface unit. The logic tester generates a test pattern that is transmitted to a smart card to test the smart card and compares a received response pattern with a response pattern to test a status of the smart card. The contactless interface unit enables a contactless test mode of operation and the contact interface unit enables a contact test mode of operation.

Abstract: An apparatus enables a high quality test to be carried out within a short time, without forcing a severe design limitation on the designer and without an expensive tester. The apparatus includes a pattern generator built in an integrated circuit to generate pseudo random patterns as test patterns. A plurality of shift registers are configured with sequential circuit elements inside said integrated circuit. An automatic test pattern generating unit generates ATPG patterns. A pattern modifier modifies a portion, to which a predetermined value is required to be set in order to detect a fault, in said pseudo random patterns generated by said pattern generator, on a basis of said ATPG patterns, and inputs said modified pseudo random patterns to said shift registers.

Abstract: In the optical disk apparatus, an arbitrary seed data for randomizing is added to an original data to be recorded on a disk. One-bit randomizing data is determined by operation using one-bit original data or seed data, and plural-bit past randomized data. At the time of descrambling, descrambling is performed without seed data.

Abstract: Integrated circuit with an application circuit (1) to be tested, and a self-test circuit (5-16) which is provided for testing the application circuit (1) and comprises an arrangement (5-9) for generating desired test patterns which are applied to the application circuit (1) for test purposes, wherein the output signals occurring in dependence upon the test patterns through the application circuit (1) are evaluated by means of a signature register (13), the arrangement (5-9) for generating the desired test patterns comprising a bit modification circuit (9) which individually controls first control inputs of combination logics (6, 7, 8) in such a way that a pseudo-random sequence of test patterns supplied by a shift register is modified such that, by approximation, the desired test patterns are obtained, and which controls second control inputs of the combination logics (6, 7, 8), by means of which the first control inputs can be blocked, such that those test patterns that are supplied by the shift register (5)

Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the invention may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the invention may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

Abstract: A signature circuit, i.e., a random-number generating circuit, is provided in a memory test apparatus. Also, a signature circuit is provided in each of devices-under-test. This configuration allows the large number of semiconductor integrated-circuit devices to be tested at one time with a high efficiency. This condition realizes a tremendous reduction in the test cost.

Abstract: A method apparatus for hardware and software co-simulation in ASIC development includes developing hardware and software concurrently and co-simulating the hardware and software therebetween via a network while the hardware and software are being developed. The method and apparatus for hardware and software co-simulation allows the software development and testing of hardware and software to start with the design of hardware so as to reduce an overall system development cycle involving ASICs.

Abstract: A novel decompressor/PRPG on a microchip performs both pseudo-random test pattern generation and decompression of deterministic test patterns for a circuit-under-test on the chip. The decompressor/PRPG has two phases of operation. In a pseudo-random phase, the decompressor/PRPG generates pseudo-random test patterns that are applied to scan chains within the circuit-under test. In a deterministic phase, compressed deterministic test patterns from an external tester are applied to the decompressor/PRPG. The patterns are decompressed as they are clocked through the decompressor/PRPG into the scan chains. The decompressor/PRPG thus provides much better fault coverage than a simple PRPG, but without the cost of a complete set of fully-specified deterministic test patterns.

Abstract: A programmable logic device includes a functional block, which does not form part of an embedded processor, which can perform a testing function on other functional blocks of the programmable logic device. Thus, the test block can read stored data values from registers in the other functional blocks of the programmable logic device, or can read signal values at points in the other functional blocks of the programmable logic device, or can insert specific data values in registers in the other functional blocks of the programmable logic device.

Abstract: A search engine apparatus having a built-in functional test may include an input generator, a search engine, a pseudo search engine and a comparator. The inputs generator is suitable for generating outputs including commands and points associated with the commands. The search engine and the pseudo search engine are communicatively coupled to the inputs generator. The search engine suitable for performing search and edit operations and the pseudo search engine is suitable for simulating the search engine by generating pseudo search engine outputs. The comparator is communicatively coupled to the search engine and the pseudo search engine, and is suitable for comparing outputs received from the search engine and pseudo search engine.

Abstract: A method for testing an electronic circuit includes selecting an input signal using a first multiplexer, selecting a signal to be input to the first multiplexer using at least one other multiplexer, and controlling the at least one other multiplexer using a selection signal output from a control circuit.

Abstract: Generating a test sequence includes receiving a circuit representation describing a circuit, and a fault associated with the circuit representation. A miter circuit model associated with a good circuit model and a faulty circuit model is established according to the circuit representation. A satisfiability problem corresponding to the fault as associated with the miter circuit model is also established. Whether the satisfiability problem is satisfiable is determined. If the satisfiability problem is satisfiable, a test sequence is generated for the fault as associated with the miter circuit model.

Abstract: A system and method for rapidly generating a series of non-repeating, deterministic, pseudo-random addresses is disclosed. A deterministic, pseudo-random number generator is implemented in hardware. Once a number in a pseudo-random sequence is generated, a pattern eliminator alters the number to remove any pattern existing in the low order bits. The number may then be combined with an offset and a base to form a memory address for testing a memory device. The generated memory address is output directly to the memory device being tested.

Abstract: The present invention provides a computer readable medium containing instructions for generating random jitter test patterns by generating a sequence of maximum-size asynchronous packets according to the P1394b standard and transmitting the sequence to the device under test. The instructions are executed to generate jitter test patterns by disabling the transmitter data scrambler of the second device; clear the port_error register of the device under test; and send a test pattern to said device under test.

Abstract: A truly random sequence of bits is transmitted from a transmitter, such that a receiver can receive and store a portion of the transmission for the duration of time that the receiver is within range of the transmitter. Thereafter, the stored sequence in the receiver is compared to a stored copy of the continuous transmission to determine the time that the stored sequence was transmitted. If the sequence of bits is truly random, the security of the system is assured.

Abstract: A test pattern generation flow has a stimulus and a device under test (DUT) that operate together through a test bench. The test bench monitors and collects all the data necessary to generate a test program. This information is presented as a captured simulation that allows for ease of generating test software, as well as other simulations such as fault simulation and virtual test simulation. The complete and convenient information can be utilized to automate the development and/or easily manually develop and debug the test software.

Abstract: A circuit consistent with certain embodiments of the present invention has a source of N reference clock frequencies (230), where N is an integer greater than one. N frequency extender circuits (954) receive the N reference clock frequencies and generating N frequency extended output clock signals therefrom. A plurality of N seed slewers (958) produce N seed update values. A plurality of N seed registers (962) each receive one of the N seed update values and produce N seed masks therefrom. A plurality of N logic circuits (966) each receive one of the N seed masks and one of the N frequency extended output clock signals. Each of the N logic circuits (966) produce a pseudorandom sequence from the seed mask and the frequency extended output clock signal. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.

Abstract: An embodiment includes encoding parallel digital data into encoded and parallel digital data in an encoder and generating parallel test data in a pseudo-random binary sequence generator circuit. The encoded and parallel digital data is coupled through a multiplexer to be serialized in a serializer in a normal mode of operation and the parallel test data is coupled through the multiplexer to be serialized in the serializer in a test mode of operation. Encoded and serial digital data are transmitted to a transmission medium in the normal mode, and serial test data are transmitted to the transmission medium in the test mode. The encoder, the serializer, the sequence generator circuit, and the multiplexer may be fabricated in a single integrated circuit chip. The parallel test data may be parallel pseudo-random binary sequence data. The parallel digital data may include data to generate colors in a visual image.

Abstract: A system and method for testing a parameterizable logic core are provided in various embodiments. A test controller is configured and arranged to generate a set of random parameter values for the logic core. A netlist is created from the parameterized logic core, and circuit behavior is simulated using the netlist. In other embodiments, selected parameter values are optionally weighted to increase the probability of generating those values, and the parameter set is cloned and mutated when simulation fails.

Abstract: A design verification system generates a small set of test cases, from a finite state machine model of the application under test. The finite state machine is reduced by creating efficient samples of the inputs to the application under test which are prepared by combinatorial input parameter selection. The test cases are generated by finite state machine traversal of the reduced state machine, and tests interacting combinations of input parameters in an efficient way. The technique is integrated into a test generator based on a finite state machine. Using an extended language, partial rulesets are employed to instruct the test generator to automatically employ combinatorial input parameter selection during test generation. Another technique for test case generation is disclosed, which uses combinatorial selection algorithms to guarantee coverage of the system under test from the aspect of interaction between stimuli at different stages or transitions in the test case.

Abstract: A method and apparatus that enable a Poisson distribution to be approximated by generating random bit sequences over a number of clock cycles. The apparatus of the present invention comprises a Poisson distribution module that includes logic configured to modulo-2 add at least two pseudo-random bit sequences (PRBSs) together to generate a number of PRBSs, which are then compared to a threshold bit sequence. The result of the comparison is a random bit sequence. Over a number of clock cycles, the random bit sequences produced approximate a Poisson distribution. The present invention can be used to evaluate the performance of communications systems by modulo-2 adding these random bit sequences with encoded data words to insert errors into the encoded data words, and then determining how well the communications system decodes and corrects the errors in the encoded data words.

Abstract: A plurality of pseudo random bit-pattern generators (PRPGs), advantageously linear feedback shift registers (LFSRs), having predetermined lengths and individual different tap locations for providing a respective sequence of pseudorandom bit-patterns. An output from a predetermined respective tap location at each LFSR is fed to a common OR-gate, a selected subset of the LFSRs are initialized with all bit storing locations to “0” in order to generate a respective permanent “0”-bit sequence, and the output of the OR-gate is used for reading the weighted or flat random bit output-pattern thereof. By controlling the number of zero-set LFSRs—a subset of the LFSRs—the weight of the generated output-pattern can be controlled.

Abstract: A method and apparatus for performing a built-in self-test (“BIST”) on an integrated circuit device are disclosed. A BIST controller comprises a logic built-in self-test (“LBIST”) engine capable of executing a LBIST and storing the results thereof and a multiple input signature register (“MISR”). The LBIST engine includes a LBIST state machine; and a pattern generator seeded with a first primitive polynomial. The MISR is capable of storing the results of an executed LBIST, the contents thereof being stored per a second primitive polynomial. A method for performing a LBIST comprises seeding a pattern generator in a LBIST engine with a first polynomial; executing a LBIST using the contents of the pattern generator; and storing the results of an executed LBIST in a MISR utilizing a second primitive polynomial.

Abstract: Flat pseudo random test patterns are provided in combination with weighted pseudo random test patterns so that the weight applied to every latch in a LSSD shift register (SR) chain can be changed on every cycle. This enables integration of on-chip weighted pattern generation with either internal or external weight set selection. WRP patterns are generated by a tester either externally or internally to a device under test (DUT) and loaded via the shift register inputs (SRIs or WPIs) into the chip's shift register latches (SRLs). A test (or LSSD tester loop sequence) includes loading the SRLs in the SR chains with a WRP, pulsing the appropriate clocks, and unloading the responses captured in the SRLs into the multiple input signature register (MISR). Each test can then be applied multiple times for each weight set, with the weight-set assigning a weight factor or probability to each SRL.

Abstract: A system and method for simulating a flow field are disclosed. A grid having cells is generated. Each cell is associated with a set of variables that describe a flow field. A value for each variable of each cell is calculated from a previous value at each period for a predetermined number of periods. The calculated values for each variable are averaged to yield an averaged value for each variable. A flow field is determined from the averaged values.

Abstract: An apparatus and method provide for an arithmetic built-in self test (ABIST) of a number of peripheral devices having parallel scan registers coupled to a processor core, all within an integrated circuit. Using the data paths of the processor core, operating logic generates pseudo-random test patterns for the peripheral devices, employing a mixed congruential generation scheme.

Abstract: An on-chip parallel data generator, including a Built In Self Test (BIST) generator, is integrated into a laser driver array of a parallel optical communication transmitter so that all optical outputs switch simultaneously. The BIST generator requires only one clock input which clocks the BIST generator for all channels. The optical outputs respond to either the on-chip BIST generator or the electrical inputs if a valid signal is present on the inputs.

Abstract: The apparatus includes the wiring-model generation section that generates a wiring model in accordance with high-frequency-circuit design information; the random-pattern analysis section that generates and analyzes a dummy random-pattern waveform for transmitting a wiring model in accordance with a command including the bit information of a random-pattern waveform and a differential waveform corresponding to the dummy random-pattern waveform; and the skew analysis section that skews a random-pattern waveform or differential waveform in accordance with a preset skew width.

Abstract: A circuit for controlling the random character of a bit flow, including an input shift register receiving the bit flow and having its outputs exploited in parallel, at least one element for comparing at least a partial content of the input register with predetermined patterns, a plurality of counters in a number at most equal to the number of predetermined patterns, and an element for detecting the exceeding of at least one threshold by one of the counters, the result of this detection conditioning the state of a word or bit indicative of the random or non-random character of the bit flow.

Abstract: Techniques are disclosed for automatically generating test instructions for use in testing a microprocessor design. A configuration file includes a plurality of knobs which specify a probability distribution of a plurality of microprocessor instructions. A random code generator takes the configuration file as an input and generates test instructions which are distributed according to the probability distribution specified by the knobs. The test instructions are executed on the microprocessor design. The microprocessor behaviors that are exercised by the test instructions are measured and a fitness value is assigned to the configuration file using a fitness function. The configuration file and its fitness value are added to a pool of configuration files. A configuration file synthesizer uses a genetic algorithm to synthesize a new configuration file from the pool of existing configuration files.

Abstract: An encoder (10,30) and method for encoding data comprising a pseudo random number generator (12) for generating an array of pseudo random numbers (15), and calculating means (10,30) for calculating a checkword (11,23,25) using the array of pseudo random numbers generated and a data sequence provided by a data unit (13).

Abstract: A system and method for generating random noise for use in testing electronic devices comprises a first random pattern generator circuit for generating first sets of random bit pattern signals; one or more delay devices each receiving a trigger input signal and a random bit pattern signal set for generating in response a respective delay output signal, each delay output signal being delayed in time with respect to a respective trigger signal, a delay time being determined by the bit pattern set received; and, an oscillator circuit device associated with a respective one or more delay devices for receiving a respective delay output signal therefrom and generating a respective oscillating signal, each oscillator signal generated being used to generate artificial random noise for emulating a real noise environment in an electronic device.

Abstract: A logic built-in self-test controller is disclosed. The invention, in its various aspects and embodiments, is a built-in self-test controller capable of performing a logic built-in self-test at a test frequency at least as slow as a slowest frequency of a plurality of timing domains to undergo the logic built-in self-test. A method for performing a built-in self-test on an integrated circuit device.

Abstract: A system is provided for testing a physical layer device, or various network portions connected to that physical layer device. The test system includes a random bit generator that, during use, produces a random pattern of bits clocked in parallel onto the transmit portion of the physical device. The parallel-fed information can then be serialized and selectably fed back to the receive input of the same physical device. The receive portion of the physical device can then deserialize the random pattern of bits, and present those bits to logic within the test system. The test system can, therefore, compare each of the random pattern of bits presented to the physical device with corresponding bits derived from the deserializer. If each bit within the random pattern of m bits forwarded to the serializer does not compare with each corresponding m bits forwarded from the deserializer, then the physical device is known to be a failure.

Abstract: A method and circuit periodically pseudo-randomly select a sample of digital event pulses comprising a logic data signal. A first timer times a first time interval. A second timer times a second time interval within the first time interval. A delay timer, coupled between the first and second timers, pseudo-randomly delays initiation of the second timer from the start of the first time interval. In one embodiment, the first timer is an (N+1)-bit binary counter. The delay timer includes an N-bit round robin latch and seeded by a pseudo-random number generator having fewer than N bits, the round robin latch shifting its contents to form an N-bit pseudo-random number. The second timer is initiated when the value of the first timer is equivalent to the round robin latch. A coincidence circuit passes digital event pulses during the second time interval. A count is accumulated of the sampled digital event pulses.

Abstract: A method and an apparatus make available uncommitted register values during the random code generation process. When there is a need for a register to contain a specific (desirable) value, then the register value is committed to that value at that point. Uncommitted values can propagate through one or more previous instructions. All registers and memory begin a test program in the uncommitted state. When the random code generator is done generating the test program, if any uncommitted values remain, then the uncommitted values are committed to arbitrary values.

Abstract: A method, apparatus, and computer instructions for testing hardware in a data processing system having multiple partitions. A monitor process in a first partition assigned to a first processor is initialized. A random code generation process in a second partition associated with a second processor is initialized. The random code generation process generates instructions and executes the instructions to test the second processor. The monitor process monitors the random code generation process and resets the second processor if the random code generation process fails.

Abstract: A method of testing for the presence of faults in digital logic circuits is described. The method involves re-ordering a number of test vectors for testing digital circuits by selecting faults at random from an original fault list to form a sample fault list FN and then forming a vector set TN?1 and then simulating the vector set TN?1 against the fault list FN. Any vector from the set TN?1 which does not detect any fault is discarded and the remaining vectors are saved as vector set TN. The method steps are repeated N times (with N having a value of 1 to M. Duplicated vector patterns in each vector set are removed and then the final vector set is initialized to produce a final vector set TF.

Abstract: LBIST and weighted LBIST tests are performed simultaneously on different portions of the tested object. This new test methodology and design change achieves the same test coverage and test time as the traditional test strategy with dramatic power reduction during test. It can be applied at wafer, chip, MCM, and system levels of test. Most importantly, it does not need new tools for support. Current test software will work as it does with the traditional test strategy. Scheduling the LBIST and weighted LBIST tests in the same test session reduces the overall power consumption because weighted LBIST testing consumes much less power than flat LBIST testing. In the same test session, if some parts of the logic is tested using weighted LBIST while the others were tested using LBIST, the power consumed by the circuit element at any given time is reduced.

Abstract: A test set used for introducing a Poisson distribution of errors into a known digital data signal to produce a test signal uses an error signal generator that produces a Poisson distribution error signal. The error signal is then combined with the known digital data signal to produce a test signal with the Poisson distribution of errors. A pseudo-random binary sequence generator is used to produce a PRBS sequence and a comparator is used for comparing the PRBS sequence with a probability control signal. The comparator sets a single bit in the output stream of zeros when the PRBS sequence is less than the probability control signal. For multiple bit Poisson distribution error signals the PRBS generator and comparator combination may be replicated m times, or a single PRBS generator may be used and a unique independent subset of the PRBS sequence is applied to each of the multiple comparators.

Abstract: A test vector decode circuit includes a lockout circuit to prevent inadvertent latching of output vectors. This circuit is driven by an additional output vector from the circuit. The additional output vector, as well as the other output vectors, undergo at least one latching. The signal transmitted by the additional output vector as a result of the final latching activates the lockout circuit. The test vector decode circuit also receives a supervoltage signal. Only by turning off the supervoltage signal can all of the output test vectors be reset, including the additional output vector.

Abstract: A method and an apparatus of loading a pre-load seed for a test code of a physical layer device (PHY). For a physical layer device including a scrambler and a Non-Return-to-Zero/Non-Return-to-Zero-Inverted (NRZ/NRZI) converter connected to the scrambler, where the NRZ/NRZI converter receives an NRZ signal outputted by the scrambler, and outputs an NRZI signal, the method includes the following steps. (a) Determine whether a plurality of starting bits of a frame are present. (b) Repeat from step (a) if the starting bits are not present. (c) Load the pre-load seed to the scrambler and transmitting the test code. (d) Set the NRZI signal in a high level when the NRZI signal is not in the high level. On the other hand, for a physical layer device having a descrambler, the method includes the steps of: (a) determining whether a plurality of starting bits of a frame are present; and (b) loading the pre-load seed to the descrambler to retrieve the test code.

Abstract: A method and apparatus for test vector compression is described. More particularly, a response analyzer is described having a shift register and a multiple-input signature register. The shift register is used to perform a first vector space reduction, and the MISR is used to perform a second vector space compression. Accordingly the MISR may be scaled down in input width by a reduction factor of the shift register.

Abstract: A test environment includes a test packet generator, a system under test, and a test device. The test packet generator generates test packets each containing a check value (e.g., a cyclic redundancy check value). The system under test performs a known transform of at least a portion of each test packet, and generates a new check value based on the transformed packet. The test device receives the transformed packets from the system under test. The test device performs an error check based on the check value and also compares the check value with an expected check value to validate the content of each received packet. Each test packet contains a splice or signature value so that the new check value calculated by the system under test is equal to the expected check value if the system under test is functioning properly.

Abstract: A built-in self test (BIST) circuit and method is provided for testing semiconductor memory. A linear feedback shift register (LFSR) is used for addressing the memory locations to be tested. Test data is derived at least partially from the address data generated from the linear feedback shift register.

Abstract: A device for generating a spreading code in a CDMA communication system is disclosed. In the device, an ML (Maximal Length) sequence generator generates an ML sequence according to a generator polynomial of an ML sequence having a length 2S−1 and a given initial value, and reloads the initial value whenever an ML sequence having a length shorter than the length 2S−1 is generated, to repeatedly perform an operation of generating the ML sequence. A mask selector including first and second masks having a given offset, selects the first mask in an ML sequence period of the desired length and selects the second mask in the other period. A modulo-2 adder adds an output of the ML sequence generator and an output of the mask selector to generate the spreading code, and truncates the ML sequence upon receipt of the second mask.

Abstract: A method of checking the authenticity of a digital electric circuit arrangement is achieved in that a concatenation (6; 8, 9) of at least a few circuit-technical elements (10) of the electric circuit arrangement (1) is formed, which deviates from the normal, intended use of the circuit arrangement (1), in that a digital random value generated by the external device (2) and transferred to the electric circuit arrangement (1) is modified in said circuit arrangement by the concatenated elements (6; 8, 9) and transferred to the external device (2), in that the external device (2) compares the modified value with a check value assigned to the random value transferred to the electric circuit arrangement (1), and in that the authenticity of the electric circuit arrangement (1) is recognized only when the modified value and the check value correspond to each other.