Abstract: Apparatus for selectively testing, in parallel, identical pins of a plurality of electronic components is provided. The apparatus enables testing of selective pins of selective electronic components according to different timing schemes.

Abstract: The invention discloses techniques for providing automatic retransmission query (ARQ) functions in a communication system. A transmitter in the system applies an input data packet to a first convolutional encoder operating at a first rate to generate an inner code including multiple encoded packets. The encoded packets are interleaved and applied to a second convolutional encoder operating at a second rate which generates an outer code including a transmit packet generated from each of the encoded packets. A first transmit packet is sent to a receiver, which decodes the transmit packet in a Viterbi decoder operating at the second rate to generate a decoded version of the first transmit packet. The decoded version is inverted to provide a first provisional decoding of the input packet. If a cyclic redundancy code (CRC) check of the first provisional decoding is passed, the receiver sends an ACK signal to the transmitter and no retransmission is required.

Abstract: An IC test equipment corrects the timing data for generating the strobe signal by each of the paths corresponding to a plurality of the devices under test measured in parallel and achieves an accurate measurement by each path, a measurement method in the IC test equipment, and a storage medium of the same. The IC test equipment is constructed as follows. The data generating circuit outputs the minimum value T1min of the timing data to the adding circuit. The data correction circuit outputs to the adding circuit the delay time TDLn with regard to the foregoing T1min corresponding to the device under test of the concerned number in accordance with the number data Dn inputted from the controller of the device under test. The adding circuit adds the foregoing T1min and the delay time TDLn to correct the timing data.

Abstract: A method for operating automatic test equipment for capturing digital data produced by a semiconductor device under test, whereby the digital data is repetitively sampled to produce a series of sampled data pairs. The digital data and the sampling frequency can be non-coherent. As a result, the digital data can be sampled early relative to some bits and late relative to other bits. The sampled data pairs that are captured while these shifts take place, from early-to-late sampling or from late-to-early sampling, are then assigned to respective groups. A minimum number of bit patterns, corresponding to the sampled digital data, is then derived from contiguous groups of sampled data pairs, and compared with expected bit patterns. The method is especially useful for capturing digital data with drifting frequency.

Abstract: A method and computer system for automatically determining test patterns for a netlist having multiple clocks and sequential circuits. The invention utilizes a static model of a sequential circuit and models the sequential circuit having multiple clock signals (e.g., one model is used for all multiple clock signals). The multiple clock signals include primary clock input signals and internal clock signals. The clock signals can be gated or dual edge. The invention makes use of the "iterative array representation of sequential circuits" (IAR) model for automatic test pattern generation (ATPG) but utilizes a static sequential circuit model. The invention receives user defined input clock signal waveforms and determines a cycle of clocks based thereon that statically represents all waveforms over time. The cycle of clocks is divided into frames where each frame contains stable clock values.

Abstract: A logic simulation monitoring system to verify a test stimulus set and generate a test vector set for use on an Automatic Test Equipment (ATE) device during manufacturing tests. The simulation monitor executes unobtrusively as part of the logic simulation to monitor the logic simulation's real time signal activity including contention checks, output strobe margins, and ATE compatibility checks, in addition to extracting the appropriate signal response or vector resulting from a given stimulus. The simulation monitor comprises at least one simulation monitor code block generated from a combination of values from an integrated circuit parameter file and at least one code block template. Output from the simulation monitor includes a report of the contention errors and input signal errors, and a test vector set comprised of the input test stimulus set used with the logic simulation and the stimulus responses resulting from the logic simulation all in an ATE compatible and ready to use format.