Abstract: An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing reference signal. The data-sampling signal may be provided by adjustably delaying a clock signal according to the phase information acquired from the strobe signal. The data-sampling signal may also have an improved waveform compared to the timing reference signal, including a fifty percent duty cycle and sharp transitions. The phase information acquired from the timing reference signal may also be used for other purposes, such as aligning received data with a local clock domain, or transmitting data so that it arrives at a remote device in synchronism with a reference clock signal at the remote device.

Abstract: A circuit is disclosed for testing integrated circuits at functional speed. In one aspect, an on-chip controller is used that accepts event data. The event data identifies a clock sequence to be used to test core logic of an integrated circuit. Multiple source clocks are generated by a phase-lock loop. The clock signals may be at the same frequency, but skewed from each other, or at different frequencies. In any event, the multiple source clocks are supplied to the on-chip controller that uses the source clocks to generate multiple test clocks. The test clocks are used to test the core logic of the integrated circuit at functional speed. In another aspect, external test equipment may supply the source clocks. Additionally, a select signal may choose whether the source clocks are supplied externally to the circuit under test or by the phase lock loop.

Abstract: A pre-conditioner for enabling high-speed time interval measurements in an ATE system having a relatively low-bandwidth pathway between a UUT and a timer/counter includes a frequency divider and a D flip-flop located near the UUT. The frequency divider receives a first input signal from the UUT and produces a first output signal having a frequency equal to 1/N times the frequency of the first input signal. The first output signal connects over the low-bandwidth pathway to a first channel of the timer/counter. The first output signal also connects to the D input of the D flip-flop. The pre-conditioner receives a second input signal from the UUT that drives the CLOCK input of the D flip-flop. The Q output of the D flip-flop supplies a second output of the pre-conditioner. The second output connects over the low-bandwidth pathway to a second channel of the timer/counter.

Abstract: A pattern generator for generating a test pattern that has a repetition rate higher than the basic repetition rate thereof to test a synchronous memory. The test pattern to be provided to a memory under test can be accurately modified by inverting the pattern data as a function of address data.

Abstract: A method and apparata for correcting for pulse width timing error during testing of an integrated circuit are described. The method includes storing in a memory, associated with a selected terminal of an integrated circuit, event timing data pertaining to testing of the integrated circuit. Functional data is provided, pertaining to the testing, and it is determined if the functional data causes a state transition in the integrated circuit, the state transition causing a pulse. If a pulse is created, then the event timing data is adjusted, thereby to produce pulse width adjusted event timing. A test signal is then applied to the selected terminal of the integrated circuit, the test signal including pulse width adjusted event timing. A test program first loads scrambler and sequencer memories with a code representing event timing data and event type data for a number of events that are to occur during a test vector, as specified by the user.

Abstract: The invention, in one embodiment, is a method of operating a synchronous memory device generally comprising providing a clock signal to the synchronous memory device to time the operation thereof and adapting the timing of at least one of reads from and writes to the synchronous memory device to improve timing parameters for the operation thereof.

Abstract: A method for designing a semiconductor integrated circuit while minimizing any increase in the area of its logic circuit under test. Circuit data about the semiconductor integrated circuit are received, and transition signal occurrence probabilities of all scanning function-equipped storage elements involved are computed by use of the circuit data. In keeping with the transition signal occurrence probabilities thus computed and based on predetermined parameters, the method permits selection of scanning function-equipped storage elements that may be replaced by delay test-ready scanning function-equipped storage elements.

Abstract: Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals generated from the captured first group. A second group of applied data signals is then captured and determined to have been properly captured when the second group corresponds to the group of expect data signals. In this way, when a captured series of data signals is shifted in time from an expected capture point, subsequent captured data signals are compared to their correct expected data signals in order to determine whether the group, although shifted in time, was nonetheless correctly captured. A pattern generator generates expect data signals in this manner, and may be utilized in in a variety of integrated circuits, such as an SLDRAM.

Abstract: A semiconductor test system is capable of time critical sequence generation using a general purpose operating system. The semiconductor test system includes a tester hardware for providing power sources and test patterns to a device under test, a host computer operated by a general purpose operating system, a configuration software for computing configuration data and timing data based on a test program, a device driver for providing a power trigger and a signal trigger to the tester hardware, and a hardware timer for producing an interrupt signal. The device driver causes to start the test pattern and to deactivate the power sources upon receiving the interrupt signal.

Abstract: A driver circuit applies a write data whose level is inverted for every write cycle to a selected memory cell in accordance with a write data held by a latch circuit when a writing operation in a test operation mode is designated in the test operation mode. A read driver circuit applies a comparison result of sequentially read data to a latch circuit in accordance with a read clock signal in the test operation mode. Data input and output buffers operate in synchronization with an external clock signal.

Abstract: A test pattern generator for automatically generating a test pattern for detecting a stack fault of a large scale integrated circuit an LSI with a tester includes a loop/path disconnecting section for disconnecting a loop portion of the LSI at a position where a fault detection rate is not lowered, based on net list information of the LSI and constraint of a test design rule when automatically generating the test pattern. A test pattern generator increasing fault detection rate and carrying out a suitable test is obtained.

Abstract: A railroad vital signal output module provides a predetermined output signal in response to a certain module input only under conditions that insure vitality of the output signal. The module includes a master microcontroller and a plurality of slave microcontrollers. The master microcontroller generates a periodic clock signal and a plurality of pseudo-random numbers in a predetermined sequence. Each slave microcontroller generates a plurality of pseudo-random numbers in the same predetermined sequence as the master microcontroller. The numbers from the master microcontroller are compared with the numbers in the slave microcontroller if the clock signal is received at a slave master controller in a predetermined window of time and if there is identity between said pseudo-random numbers, the module provides a predetermined output signal which is assured to be vital.

Abstract: A bus-clock-speed-independent apparatus and method of wrap input/output (I/O) testing of an I/O interface is provided. Launch data is launched in response to a launch clock. A capture clock is derived from the launch clock by delaying the launch clock through a programmable delay. Launch data is wrapped through the I/O interface buffers and captured in response to the capture clock. A initial value of the programmable delay is selected and successively increased or decreased until the launch data is just captured, or just fails to be captured, respectively. The value of the programmable delay when this occurs provides a measure of the limiting speed of the I/O interface.

Abstract: An apparatus that can determine whether a Tva parameter and a Tvb parameter of a device under test (DUT) complies with a design specification where the device under test is coupled to a secondary device. The Tvb parameter corresponds to a setup time of the secondary device. The Tva parameter corresponds to the hold time of the secondary device. The apparatus allows the DUT to be coupled to a secondary device that normally operates with the DUT. The apparatus writes data to the DUT and secondary device. The data is then written back to the apparatus which then determines whether the DUT complies with the Tvb and Tva design specifications. The apparatus may also implement tunable delay circuits to compensate for different setup and hold times of the secondary device.

Abstract: Test pattern generation is performed for a sequential circuit by first separating the circuit into overlapping pipelines by controlling corresponding clocks for one or more registers of the circuit so as to break feedback loops of the circuit, and then processing each of the pipelines separately in order to determine if particular target faults are detectable in the pipelines. Independent clocks may be provided for each of a number of registers of the circuit in order to facilitate the breaking of the feedback loops. The processing of the pipelines may include a first processing operation which detects target faults in a single time frame, and a second processing operation which detects target faults in two or more time frames. The first processing operation generates as many combinational test vectors as possible for each of the pipelines, while the second processing operation generates sequences of two or more combinational test vectors for each of the pipelines.

Abstract: The present invention relates to a method of functional testing of a logic circuit and to an integrated circuit for implementing the method. The method includes providing at least one test pattern and the storage of this test pattern in a first test register, this providing step being synchronized by an external clock signal; serially providing of this test pattern to an input of the internal logic circuit, this providing step being synchronized by a test clock signal generated from an internal clock signal; storing, in a second test register connected to the output of the internal logic circuit, at least one resulting pattern generated by the internal logic circuit when the test pattern is provided thereto, this storing being synchronized by the test clock signal; and providing to the outside, by series shifting, of the resulting pattern, this providing step being synchronized by the external clock signal.

Abstract: A method and apparatus for testing an input data path of an integrated circuit. Dual transmit and receive delay locked loops (DLLs) provide clocks for test mode data transmit and receive. Test mode logic drives a data pattern into an input receiver with the data pattern clocked by the transmit DLL and the input receiver clock by the receive DLL. The output of the input receiver is compared with the data pattern. The transmit DLL is adjusted relative to the receive DLL to measure setup and hold times of the data pattern driven through the input receiver.

Abstract: The present invention is a system and method that permits appropriate scan testing of internal components of an integrated circuit while reducing the number of external pins required to perform the scan testing. One embodiment of the present invention utilizes standard IEEE 1149.1 pins (e.g. TDO, TDI, TMS, TCK, etc.) to perform both boundary scan and full scan testing. A modified IEEE 1149.1 TAP controller generates signals to control the boundary scan and full scan operations. For example, a full scan cell facilitates full scan capture and shift operations when the TAP controller generates a full scan test mode signal and a full scan enable signal in response to inputs via the standard IEEE 1149.1 pins. In one example the scan enable signal is asserted when the TAP controller is in a shift state and the TAP controller's instruction register is loaded with a test mode instruction. A functional clock capture cycle is applied when the state machine of the TAP controller is in run/idle state.

Abstract: An internal guardband for use in semiconductor testing is disclosed. One aspect of the invention is a semiconductor circuit having two paths. The first path is a standard path, used for normal operation of the circuit. The second path is a test path, used for testing of the circuit. The second, test path adds delay as compared to the first, standard path. This delay acts as an internal guardband for the circuit.

Abstract: A double data rate (DDR) circuit for testing of a high speed DDR interface using single clock edge triggered tester data. The DDR testing circuit includes a first register, a second register, and a multiplexer (MUX). A clock signal is fed to the first register and the MUX. The inverse of the clock signal is fed to the second register. A tester data signal is fed to the first register which generates a latched tester data signal which is fed to the MUX. The inverse of the latched tester data signal is fed to the second register which generates a transformed tester data signal which is fed to the MUX. The MUX generates a combination of the latched tester data signal and the transformed tester data signal for transmission as an applied test data signal. The resulting applied test data signal has double the data rate of the tester data signal upon which it is based.

Abstract: A bit error measuring device for modem device, comprises; a bit error measuring unit for measuring a bit error in an input signal from the modem device, a clock controlling unit for controlling an output of a clock signal on the basis of a control signal outputted from the modem device, and a test pattern transmitting unit for transmitting a test pattern signal by synchronizing with the clock signal when clock pulses of the clock signal are outputted from the clock controlling unit, and for stopping a transmission of the test pattern signal when the clock pulses of the clock signal are not outputted from the clock controlling unit.

Abstract: A method for generating a test pattern used for testing, by an LSI tester, a semiconductor integrated circuit having external terminals and sequential unitary circuits, comprising the steps of: extracting, from circuit connection information of the semiconductor, at least one sequential unitary circuit having a pair of potentially contending input terminal, and a pair of potentially contending external terminals connected to the input terminals; and further extracting therefrom a pair of actually contending external terminals connected to the same sequential unitary circuit and concurrently changing their signal level in a test pattern. On the basis of a path delay value from each of the actually contending external terminals to the corresponding sequential unitary circuit, and on the basis of the value of a tester skew, determining an optimum timing condition in the sequential unitary circuit; and generating the test pattern for the LSI tester on the basis of the optimum timing condition.

Abstract: A timing fault diagnosis method diagnoses a timing fault of an integrated circuit chip having a logic circuit formed therein. The timing fault diagnosis method includes steps of (a) obtaining fail information by applying a test pattern to an external input terminal of the integrated circuit chip, (b) extracting, from the logic circuit, a circuit which is to be subjected to a timing fault diagnosis, based on logic structure data of the logic circuit and the fail information, (c) creating a timing fault pattern by assuming a timing fault in each of elements having a possibility of generating a timing fault within the circuit which is to be subjected to the timing fault diagnosis, and (d) specifying an element which is assumed to generate the timing fault based on a timing fault diagnosis by comparing the timing fault pattern and the fail information.

Abstract: A driver circuit applies a write data whose level is inverted for every write cycle to a selected memory cell in accordance with a write data held by a latch circuit when a writing operation in a test operation mode is designated in the test operation mode. A read driver circuit applies a comparison result of sequentially read data to a latch circuit in accordance with a read clock signal in the test operation mode. Data input and output buffers operate in synchronization with an external clock signal.

Abstract: The invention relates to a method of testing an integrated circuit comprising memory cells arranged around a core whose clock input is subjected to a conditional inhibition in the test mode.

Abstract: A semiconductor test system is capable of generating timing edges in the same direction having a time interval smaller than a reference clock cycle. The semiconductor test system includes a waveform memory for storing edge data which defines edges of a test signal waveform, a timing generator for generating timing data and a timing pulse for each test cycle, a wave formatter for generating a set signal and a reset signal for producing the test signal waveform in response to the timing data and the timing pulse, and a virtual timing generator for detecting a relationship between previous edge data and current edge data from the waveform memory and removing the current edge data when the current edge data is the same as the previous edge data and allocating the current edge data to a time position where there is an actual change of edge in the test signal waveform.

Abstract: An integrated and constantly enabled on-chip test interface for use in verifying the functionality of high speed embedded memories such as synchronous dynamic random access memories (“SDRAM”) which allows for the utilization of existing, relatively low speed, (and hence low cost), testers to perform the testing. The interface allows for the verification of an embedded memory macro design utilizing a test interface which includes the memory macro and separate on-chip test circuitry so that half-rate, narrow word, input signals from a tester can perform all memory macro operations across the breadth of a wide memory macro input/output (“I/O”) architecture. The on-chip test circuitry may also include a synchronizing circuit to minimize skew between the external clock and the data output from the test chip.

Abstract: To vigorously test synchronization logic and protocols in a digital circuit design, a synchronization logic model uses randomization to emulate the uncertainty in synchronization clock delay time exhibited in actual circuits. The synchronization logic model is inserted into a software description of the design so that simulation will reveal faulty assumptions in the synchronization protocol. Additionally, where a non-synchronized signal crosses from one clock domain to another clock domain in an asynchronous digital design, a transition on the non-synchronized signal triggers an “X” value window on the signal for a selected period relative to the receiving clock period, so that simulation will fail if the receiving logic samples the signal value during the “X” value window. These techniques aid in effective testing of the design.

Abstract: Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of these applied data signals have been properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated from the captured first group of applied data signals. A second group of the applied data signals are then captured after the first group. The second group of applied data signals are determined to have been properly captured when the second captured group of applied data signals corresponds to the group of expect data signals. In this way, when capture of the applied series of data signals is shifted in time from an expected initial capture point, subsequent captured groups of applied data signals are compared to their correct expected data signals in order to determine whether that group, although shifted in time, was nonetheless correctly captured.

Abstract: A method of generating a test pattern for a semiconductor integrated circuit comprising a logic circuit containing a combinational logic element, a first sequential circuit having an output side connected to an input side of the logic circuit, and a second sequential circuit having an input side connected to an output side of the logic circuit, whereby a test pattern for testing a signal path between the first and second sequential circuits for a data retention error associated with data held by the second sequential circuit based on output data of the second sequential circuit is generated. To generate the test pattern, a first test pattern is generated by setting, at the first sequential circuit, a first set value for the signal path such that the signal path is activated immediately before and after one pulse of a clock signal for synchronization is inputted and a second test pattern is generated by setting, at the first sequential circuit, a second set value obtained by inverting the first set value.

Abstract: Data output from a semiconductor device under test and a reference clock output therefrom in synchronization with the data are sampled by slightly phased-apart multiphase strobe pulses. The phases of points of change of the output data and the reference clock are obtained from the sampled outputs, then the phase difference between them is measured, and a check is made to determine if the phase difference falls within a predetermined range, thereby evaluating the semiconductor device under test on a pass/fail basis.

Abstract: A built-in self test system for testing a clock and data recovery circuit is disclosed. The present invention provides a built-in self test circuit which operates with high speed phase lock loop. The built-in circuit comprises data generating means for generating a test data byte and serializing means coupled to the data generating means for converting the test data byte into serial test data. The clock and data recovery means are coupled to the output of the serializing means for recovering the clock and test data from the serial test data. A deserializing means coupled to the output of the clock and data recovery means converts the recovered serial test data into a recovered test data byte, and analyzing means connected to the output of the deserializing means compares the recovered test data byte to the initial test data byte.

Abstract: A physical layer (PHY) device in an Ethernet type LAN is configured to permit ease of testing of the PHY device's logic. The PHY device comprises a PHY receiver, a start frame delimiter detector (SFD), and automatic checker circuitry in which the clock position and the PHY pop-up position of received signals can be determined. The automatic checker circuitry receives a data signal having a predetermined pattern corresponding to a valid data packet from a pattern generating circuit. The automatic checker circuitry outputs a verification signal indicating whether the supplied signals are valid. This arrangement supports a one pass test, which reduces production costs and testing duration.

Abstract: A system includes a first integrated circuit and a second integrated circuit coupled by at least one signal line. The first integrated circuit outputs on the signal line an interleaved output signal including both operating data and debug data. The second integrated circuit receives as an input signal, of the operating data and the debug data, only the operating data. In this manner, the internal states of the first integrated circuit are made visible during normal operation of the system without the use of dedicated I/O pins.

Abstract: The present invention includes bit synchronizers and methods of synchronizing and calculating error. One method of synchronizing with a data signal in accordance with the present invention includes providing a data signal having a first portion and a second portion, generating a timing signal, first adjusting the timing signal during the first portion of the data signal, accumulating a history value during the first portion of the data signal, and second adjusting the timing signal during a second portion of the data signal using the history.

Abstract: An IC tester includes a test pattern storage circuit that stores a test pattern, a delay amount storage table that stores a test condition, an offset address generation circuit that divides the delay amount storage table into a plurality of regions and selects a region from the plurality of divided regions, a reference signal delay circuit that delays a reference signal according to a test condition stored in a region of the delay amount storage table selected by the offset address generation circuit, and a test waveform formation circuit that generates a test waveform according to the test pattern stored in the test pattern storage circuit and the reference signal delayed by the reference signal delay circuit.

Abstract: A mobile communication system includes a demodulator demodulating an interleaved data signal and outputting a demodulated data. A deinterleaver data array receives and deinterleaves the demodulated interleaved data and outputs a deinterleaved demodulated data. A memory stores the deinterleaved demodulated data and a Viterbi decoder receives the deinterleaved demodulated data from the memory. The Viterbi decoder corrects any error in the deinterleaved demodulated data. A controller accesses unit data outputted from the demodulator to the deinterleaver data array and the memory, respectively. An address generator receives an externally applied start address signal and outputs address signals corresponding to a block size to the deinterleaver data array. An input/output unit is coupled to the demodulator, the deinterleaver data array, and the controller. The input/output unit controls data input/output operations.

Abstract: A test method for testing a semiconductor device includes providing a tester which generates a plurality of general clock signals and which has a minimum test cycle time greater than an operational cycle time of the semiconductor device. Then a modulated clock signal is generated from a first general clock signal and a second general clock signal so that the modulated clock signal has a minimum cycle time no greater than the operational cycle time. The next steps include supplying the modulated clock signal to the semiconductor device as a predetermined control signal, supplying test signals to the semiconductor device as specified by a functional test item, and comparing an output of the semiconductor device to a reference value.

Abstract: An electronic circuit tester (e.g., for testing integrated circuit wafers or packaged integrated circuits) is provided. The tester is preferably based on a relatively inexpensive computer system such as a personal computer and includes at least one high-precision clock circuit that is programmable with respect to frequency and number of clock pulses. The high-precision clock circuit is connectable to the circuit being tested to permit certain timing-critical tests to be performed, even though a large number of other data channels in the tester are controlled by a relatively low speed clock circuit. The tester also includes analog circuitry that can be programmed to provide various analog signals suitable for performing parametric testing on an electronic device under test.

Abstract: A processor provides trace capability. Trace information can be provided over a communication port that is operable both as a trace port and as a parallel debug port. The trace port provides trace information indicating instruction execution flow in the processor core. The operation of the communication port as a trace port and as a parallel debug port is mutually exclusive. The parallel debug port provides for transmission of debug information between a debug host controller and the processor. The parallel debug port and the trace port physically share pins. Bus request and grant signals are provided between the parallel debug port and a debug host controller to ensure that collisions do not occur between use by the trace port and the debug host controller. A separate serial debug port is also provided which can be used to enable the parallel debug port.

Abstract: A bit error measuring device for modem device, comprises; a control code detecting unit for detecting a flow control code set in an input signal from the modem device, and for masking the flow control code, a bit error measuring unit for measuring bit errors in the input signal of which the flow control code is masked, a clock controlling unit for controlling an output of a clock signal by the flow control code, and a test pattern transmitting unit for transmitting a test pattern signal by synchronizing with the clock signal when clock pulses of the clock signal are outputted from the clock signal controlling unit, and for stopping a transmission of the test pattern signal when the clock pulses of the clock signal are not outputted from the clock signal controlling unit.

Abstract: A method of LBIST testing of an entire chip (i.e. all logic and arrays are getting system clocks) enables finding intermittent fault in an area, such as the L1 cache. Latches such as GPTR latches can be set such that the L1 cache will no longer receive system clocks during LBIST testing. Logic causing an intermittent failure will no longer receive system clocks and hence will no longer cause intermittent LBIST signatures. LBIST testing can proceed on looking for the next failure, if one existed, or proving that the remaining logic contains no faults. Generally, a chip, has a basic clock distribution and control system that the chip is divided into a number (N) of functional units with each unit receiving system clocks from its own clock control macro. Each clock control macro receives an oscillator signal and a bit from the GPTR (General Purpose Test Register). All the functional units contain latches that are connected into one scan chain.

Abstract: An integrated circuit tester produces an output TEST signal following a pulse of a reference CLOCK signal with a delay that is a sum of an inherent drive delay and an adjustable drive delay. The tester also samples an input RESPONSE signal following a pulse of the reference CLOCK signal with a delay that is a sum of an inherent compare delay and an adjustable compare delay. The inherent drive and compare signal path delays within an integrated circuit tester are measured by first connecting a salphasic plane to transmission lines that normally convey signals between the tester and terminals of an integrated circuit device under test. A standing wave signal appearing on that salphasic plane is phase locked to the CLOCK signal so that a zero crossing of the standing wave occurs at a fixed interval after each pulse of the CLOCK signal.

Abstract: A path test signal generator and checker which can achieve a path test by effectively generating a path test signal in a system handling synchronous transport modules STM-Ns with an order higher than that of the basic interface. A test pattern generator generates a continuous PN pattern intermittently, inserts a predetermined logical value in locations of the section overhead and path overhead in a transmission frame while suspending the generation of the path test signal in those locations, and inserts the continuous PN pattern in the entire columns of the payload of the transmission frame. A path overhead insertion circuit rewrites the predetermined logical value inserted in the location of the path overhead into the path overhead. The multiplex section terminating circuit rewrites the predetermined logical value inserted in the location of the MSOH (multiplex section overhead) to the MSOH, and the logical value inserted in the location of the RSOH (regenerator section overhead) to the RSOH.

Abstract: A test pattern generating apparatus generates a test pattern for evaluating whether or not source data and a bit synchronous clock signal SCK are transmitted normally through a bus connecting a plurality of terminal units for transmitting and receiving source data. A test pattern generating circuit 33 generates predetermined test pattern data which are predetermined as the test pattern, based on the bit synchronous clock signal and a frame synchronous clock signal LRCK and outputs the test pattern data, bit synchronous clock signal and frame synchronous clock signal to the bus.

Abstract: A method for controlling a gating circuit of an electronic system incorporating a scan architecture complying with IEEE Standard 1149.1 such that the gating circuit applies mutually exclusive signals to, for example, a decoded multiplexer. The gating circuit receives input signals from flip-flops that are part of a scan chain, is selectively controllable by a control signal to transmit predetermined mutually exclusive signals to the select inputs of the multiplexer during a scan mode. Alternatively, the gating circuit is controllable by the control signal to pass the input signals to the multiplexer in a normal operation or test mode. A mutual exclusivity circuit is provided to generate the control signal. During the scan mode, the control signal is generated at a first logic level such that the gating circuit transmits the predetermined mutually exclusive signals to the multiplexer while test values are being scanned into the flip-flops.

Abstract: The present invention is generally directed to a circuit and method for evaluating the timing relationship of electrical signals in an integrated circuit. In accordance with one aspect of the invention, a circuit is provided having a signal select circuit that is includes two or more inputs and one output. The signal select circuit (preferably a multiplexer) is configured to select one of the two or more input signals for evaluation and direct it to the output. A plurality of signal buffers are electrically cascaded to the output of the signal select circuit. Finally, a scan chain having a plurality of scan elements is disposed to acquire a state of electrical signals along the plurality of signal buffers. In accordance with another aspect of the invention, a method is provided for evaluating the timing relationship of electrical signals in an integrated circuit.

Abstract: A method of automatically testing electronic components in parallel, identical pins (i; i+1) of said components interchanging test signals with at least one common test circuit (20; 20') which includes, firstly, timing generators (22a, 22b, 22c, 22d; 22'a, 22'b, 22'c, 22'd) controlled by a test programming memory (10) and, secondly, forcing circuits (24.sub.1, 24.sub.2 ; 24'.sub.1, 24'.sub.2) and comparator circuits (26.sub.1, 26.sub.2 ; 26'.sub.1, 26'.sub.2) controlled by said timing generators. In accordance with the invention, all the timing generators are assigned to said forcing circuits or to said comparator circuits in such manner as to produce synchronous test signals at said identical pins (i) of said electronic components. Applications include automatic testing of components in parallel.

Abstract: A timing edge forming circuit includes a pattern generator for generating address data, a rate signal and pattern data, a first logic delay circuit for generating first delay time data by the address data wherein the first delay time data includes a first multiple delay time which is an integer multiple of one cycle of the clock signal and a first fractional delay time which is smaller than one cycle of the clock signal, and for sending an enable signal in synchronism with the clock signal which is delayed by the first multiple delay time and the first fractional delay time, a logic delay control circuit for adding the first fractional delay time to skew data to form second delay time data, a second logic delay circuit for providing a second multiple delay time in the second delay time data which is an integer multiple of one cycle of the clock signal to the enable signal, and for producing a second fractional delay time which is smaller than one cycle of the clock signal, a variable delay circuits for provid

Abstract: An algorithmic pattern generator produces an output data value during each cycle of a clock signal. The pattern generator includes an addressable instruction memory reading out an instruction during each clock signal cycle. A memory controller normally increments the instruction memory's address during each clock signal cycle, but may jump to another address N+1 clock signal cycles after receiving a CALL, RETURN, REPEAT or BRANCH command from an instruction processor. The instruction processor normally executes the instruction read out of the instruction memory during each clock signal cycle and provides a data field included in the executed instruction as the pattern generator's output data. Other fields of the instruction reference a command the instruction processor sends to the memory controller.