Error Pointer Patents (Class 714/765)
  • Patent number: 11687406
    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a memory device may select an option for a host device to access a memory array including a first portion configured to store user data and a second portion configured to store different data based on whether an ECC function of the memory device is enabled or disabled—e.g., storing ECC data when the ECC function is enabled, storing additional user data, metadata, or both when the ECC function is disabled. The host device may disable the ECC function and transmit an input to the memory device as to how to access the memory array. The memory device, based on the input, may select the option for the host device to access the memory array and communicate with the host device in accordance with the selected option.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: June 27, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Anthony D. Veches
  • Patent number: 11676680
    Abstract: A method for dynamically handling the failure of the static random-access memory (SRAM) dynamic failure handling system using a cyclic redundancy check (CRC) includes obtaining a write data; determining a write address; storing the write data at the write address of a frame memory which is composed of the SRAM and includes a real address area and a spare address area which are distinguished from each other; storing, in response to the write address, a write cyclic redundancy check (CRC) generated by performing a CRC calculation on the write data; determining a read address; reading a read data from the read address of the frame memory; determining whether, based on the A CRC remainder W_CRC corresponding to the read address and the read data, a CRC error occurs, and generating an error flag when the CRC error occurs; determining a fault address based on the error flag; and mapping the fault address to one of non-fault spare addresses of the spare address area when the fault address is an address of the real a
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: June 13, 2023
    Assignee: MAGNACHIP SEMICONDUCTOR, LTD.
    Inventor: Sangsu Park
  • Patent number: 11379299
    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a memory device may select an option for a host device to access a memory array including a first portion configured to store user data and a second portion configured to store different data based on whether an ECC function of the memory device is enabled or disabled—e.g., storing ECC data when the ECC function is enabled, storing additional user data, metadata, or both when the ECC function is disabled. The host device may disable the ECC function and transmit an input to the memory device as to how to access the memory array. The memory device, based on the input, may select the option for the host device to access the memory array and communicate with the host device in accordance with the selected option.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: July 5, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Anthony D. Veches
  • Patent number: 10963336
    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a memory device may select an option for a host device to access a memory array including a first portion configured to store user data and a second portion configured to store different data based on whether an ECC function of the memory device is enabled or disabled—e.g., storing ECC data when the ECC function is enabled, storing additional user data, metadata, or both when the ECC function is disabled. The host device may disable the ECC function and transmit an input to the memory device as to how to access the memory array. The memory device, based on the input, may select the option for the host device to access the memory array and communicate with the host device in accordance with the selected option.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: March 30, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Anthony D. Veches
  • Patent number: 10860420
    Abstract: One embodiment facilitates data placement in a storage device. During operation, the system receives chunks of data to be written to a non-volatile memory. The system encodes a first chunk based on a first error-correcting code (ECC) to obtain a first ECC-encoded codeword. The system encodes a first group of ECC-encoded codewords which include the first ECC-encoded codeword, based on an erasure code (EC) to obtain a first EC-encoded group, wherein a respective EC-encoded group includes EC parity bits. The system encodes the EC parity bits of the obtained first EC-encoded group based on a second error-correcting code (ECC) to obtain ECC-encoded EC parity bits. The system writes the first EC-encoded group and the ECC-encoded EC parity bits to the non-volatile memory.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: December 8, 2020
    Assignee: Alibaba Group Holding Limited
    Inventor: Shu Li
  • Patent number: 10831583
    Abstract: An error mechanism provides stored error information to assist in determining the cause of failure of a storage device such as a hard disk drive. The error mechanism gathers information surrounding an error event from various software and hardware components in the system. An event command is sent to the storage device that includes the gathered information. The storage device stores the gathered information from the event command in a log on the storage device. After the storage device is removed from the system the error information in the log can be used to determine the cause of the failure. The event command may be standardized into an existing industry communication protocol or be vendor specific.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Timothy M. Damron, Justin K. King, Lee N. Helgeson, Michelle A. Schlicht
  • Patent number: 10761919
    Abstract: An information handling system includes a processor, a dual in-line memory module (DIMM), and a memory controller coupled to the DIMM. The memory controller provides interrupts to the processor each time a read transaction from the DIMM results in a correctable read error. The processor instantiates a failure predictor to receive the interrupts, accumulate a count of the interrupts, and provide a first error indication when the count exceeds a first error threshold. The failure predictor increments the count each time the predictor receives a particular interrupt and decrements the count in accordance with an error leak rate. The error leak rate has a first value when the DIMM is newer than a first age threshold and has a second value when the DIMM is older than the first age threshold.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: September 1, 2020
    Assignee: Dell Products, L.P.
    Inventors: René Franco, Amit S. Shah, Tuyet-Huong Thi Nguyen, Vijay B. Nijhawan, Vadhiraj Sankaranarayanan, Mark L. Farley, Andrew Butcher
  • Patent number: 10733290
    Abstract: Methods and equipment for determining whether a ransomware attack is suspected include a data storage device including a controller; non-volatile memory; a data path between the controller and the non-volatile memory; and an anti-ransomware module configured to monitor the data path. Methods and equipment also include monitoring a data path between a controller and a non-volatile memory on a data storage device; calculating an entropy of a data set to be written to the non-volatile memory; analyzing the calculated entropy; and determining whether a malware attack is suspected. Methods and equipment also include monitoring a data path between a controller and a non-volatile memory on a data storage device; identifying activity indicative of ransomware; once activity indicative of ransomware has been identified, calculating an entropy of a data set to be written to the non-volatile memory; analyzing the calculation; and determining whether a ransomware attack is suspected.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: August 4, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Danny Berler, Judah Gamliel Hahn
  • Patent number: 10725862
    Abstract: An integrated circuit comprising a memory array configured to store data chunks with corresponding error correction codes and error correction logic includes control logic that executes a recovery procedure to access a selected data chunk and corresponding error correction code from the memory array, to utilize the error correction logic to identify a location in the memory array of an error bit in the selected data chunk, and to access the identified location to write the corrected data. The recovery procedure is sequentially applied to a plurality of data chunks over a recovery operation region designated for a given instance of the recovery operation. Memory coupled with the control logic can store one or more recovery parameters that identify the recovery operation region in the memory.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: July 28, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chia-Feng Cheng, Chun-Hsiung Hung
  • Patent number: 10635554
    Abstract: An information handling system includes a first memory, a second memory, and a central processor. The first memory includes a buffer to store uncorrected no action (UCNA) errors for the second memory. The central processor detects a memory data corruption in the second memory, stores a first UCNA error associated with the memory data corruption in the buffer implemented within the first memory, determines whether the buffer is full, and erases an oldest in time UCNA error from the buffer in response to the buffer being full.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: April 28, 2020
    Assignee: Dell Products, L.P.
    Inventors: David K. Chalfant, Tuyet-Huong Nguyen, Jose M. Grande
  • Patent number: 10592367
    Abstract: Systems, apparatuses, and methods for efficiently increasing reliability of memory accesses are described. In various embodiments, write data and write mask data are shifted by redundancy logic in a memory. The redundancy logic receives write data bits, which are segmented into one or more write groups in addition to one or more mask bits and one or more shift bits per write group. If the redundancy logic detects a first shift bit assigned to a first write group is asserted, then the redundancy logic selects a second mask bit assigned to a second write group different from the first write group. Otherwise, a first mask bit assigned to the first write group is selected. Following, the redundancy logic combines the selected mask bit with the first data bit of the first write group.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: March 17, 2020
    Assignee: Apple Inc.
    Inventors: Steven Frederick Schicht, William R. Weier
  • Patent number: 10461777
    Abstract: An apparatus includes a convergence detector circuit coupled to an error locator polynomial generator circuit. The convergence detector circuit includes at least two computation circuits configured to generate at least two convergence signals based on a mutual error locator polynomial from the error locator polynomial generator circuit and on at least two different sets of syndromes. Each of the different sets of syndromes corresponds to a different one of the convergence signals.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: October 29, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Ishai Ilani, Kiran Kumar Gunnam
  • Patent number: 10298919
    Abstract: A manufacturing method for a polarizing stereo electronic large screen display system, including disposing a plurality of physical pixels a display screen; disposing two individual pixels each including three primary colors inside one physical pixel for respectively emitting light for the left eye and the right eye; and disposing a plurality of polarizing films on the plurality of physical pixels. The method results in a display system having high resolution.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: May 21, 2019
    Assignee: CENTRAL CHINA DISPLAY LABORATORIES, LTD.
    Inventors: Chao Li, Daxin Shi, Xianbin Kang, Bin Xiong, Shuzheng Li
  • Patent number: 10142102
    Abstract: An integrated circuit having a Physically Unclonable Function (PUF) circuit is provided. The PUF circuit may reside as part of a secure subsystem, which also includes a random number generator, a syndrome generator, non-volatile memory, and control circuitry. A predetermined syndrome of a desired PUF response is stored in the non-volatile memory. During normal operation, a current PUF response may be read out from the PUF circuit. The current PUF response may include erroneous bits that differ from the desired PUF response. The random number generator may generator a random number that masks the current PUF response, whereas the syndrome generator outputs a syndrome of the current PUF response. This information may then be passed to a separate error-correcting code (ECC) processor. The ECC processor may return information back to the secure subsystem, and the control circuitry may then obtain a corrected PUF response that matches the desired PUF response.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: November 27, 2018
    Assignee: Altera Corporation
    Inventor: Bruce Pedersen
  • Patent number: 10102003
    Abstract: Intelligent context management for thread switching is achieved by determining that a register bank has not been used by a thread for a predetermined number of dispatches, and responsively disabling the register bank for use by that thread. A counter is incremented each time the thread is dispatched but the register bank goes unused. Usage or non-usage of the register bank is inferred by comparing a previous checksum for the register bank to a current checksum. If the previous and current checksums match, the system concludes that the register bank has not been used. If a thread attempts to access a disabled bank, the processor takes an interrupt, enables the bank, and resets the corresponding counter. For a system utilizing transactional memory, it is preferable to enable all of the register banks when thread processing begins to avoid aborted transactions from register banks disabled by lazy context management techniques.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: October 16, 2018
    Assignee: International Business Machines Corporation
    Inventor: Randal C. Swanberg
  • Patent number: 10078518
    Abstract: Intelligent context management for thread switching is achieved by determining that a register bank has not been used by a thread for a predetermined number of dispatches, and responsively disabling the register bank for use by that thread. A counter is incremented each time the thread is dispatched but the register bank goes unused. Usage or non-usage of the register bank is inferred by comparing a previous checksum for the register bank to a current checksum. If the previous and current checksums match, the system concludes that the register bank has not been used. If a thread attempts to access a disabled bank, the processor takes an interrupt, enables the bank, and resets the corresponding counter. For a system utilizing transactional memory, it is preferable to enable all of the register banks when thread processing begins to avoid aborted transactions from register banks disabled by lazy context management techniques.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: September 18, 2018
    Assignee: International Business Machines Corporation
    Inventor: Randal C. Swanberg
  • Patent number: 9639422
    Abstract: Memory devices having a first plurality of data buffers coupled to sense circuitry, a second plurality of data buffers coupled to sense circuitry, and an error correction controller coupled to the first and second plurality of data buffers and configured to synchronize data from the first and second plurality of data buffers prior to transmitting the data, as well as systems containing such memory devices.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: May 2, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Alberto Troia
  • Patent number: 9389940
    Abstract: Error data is read from error registers and written into a buffer. A computing node uses a BIOS to read the error data, rearm the error register and write the data into a memory mapped buffer. A hub chip supports creation of a shared memory system of computing nodes. A management controller in the computing node extracts error data from the buffer. The error data preferably consists essentially of the error register identifiers and the contents of the error registers. A system management node receives the error data from the management controllers in the computing nodes. The system management node may be coupled to but separate from the computing nodes.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: July 12, 2016
    Assignee: Silicon Graphics International Corp.
    Inventors: Mark Larson, Michael Brown, Gary Meyer
  • Patent number: 9391638
    Abstract: Some of the embodiments of the present disclosure provide a method including receiving data to be stored in a memory, the data including (i) data bits and (ii) a tag indicating that one or more of the data bits are corrupted; generating eight error correction code (ECC) bits corresponding to the data bits of the data; in response to the data including the tag indicating that one or more of the data bits are corrupted, modifying seven bits of the eight ECC bits to generate modified ECC bits, wherein the seven bits of the eight ECC bits are modified to indicate that one or more of the corresponding data bits are corrupted; and writing the data bits, along with the modified ECC bits, to the memory. Other embodiments are also described and claimed.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: July 12, 2016
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventor: Assaf Metuki
  • Patent number: 9317360
    Abstract: In some implementations, a processor may include a machine check architecture having a plurality of error reporting registers able to receive data for machine check errors. A summary register may include a plurality of settable locations that each represents at least one of the error reporting registers. One or more of the settable locations in the summary register may be set to indicate whether one or more of the error reporting registers maintain data for a machine check error. Accordingly, when a machine check error occurs, the summary register may be accessed to identify if any error reporting registers in a processor's view contain valid error data, rather than having to read each of the error reporting registers in the processor's view.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: April 19, 2016
    Assignee: Intel Corporation
    Inventors: Jose A. Vargas, Mohan J. Kumar, James B. Crossland, Murugasamy K. Nachimuthu, Theodros Yigzaw
  • Patent number: 9275757
    Abstract: The system and methods allow for emulation of random hardware failure of an internal embedded memory array of an integrated circuit (IC) device. Emulation of potential defects is performed in order to evaluate the behavior of the rest of the design. This non-intrusive emulation is performed in a pseudo-functional mode in order to evaluate the behavior of one or more memory cores in their standard functional mode. The solution enables the creation of failures and tracking both the detection of the failures and the time required time for detection. Specifically, the emulation of an internal memory array with respect of random failures and the associated diagnostic mechanism ensures that detection and correction mechanisms work as expected. A typical non-limiting use case is to ensure that safety control logic of an IC behaves as expected in cases of data corruption within an embedded memory core.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: March 1, 2016
    Assignee: Scaleo Chip
    Inventor: Mathieu Thomas
  • Patent number: 9218243
    Abstract: A memory system supporting error detection and correction (EDC) coverage. The system includes a memory controller and a memory buffer. The memory buffer includes an interface to a first group of memory devices and an interface to a second group of memory devices. The memory buffer accesses data from the first group of memory devices and accesses first error information corresponding to the data from the second group of devices. The memory buffer also accesses additional data from the second group of memory devices and accesses second error information corresponding to the additional data from a device in the first group of memory devices. EDC coverage may also be configured by the memory controller so that some data accesses have EDC coverage and other data accesses do not have EDC coverage.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: December 22, 2015
    Assignee: Rambus Inc.
    Inventor: Ian P. Shaeffer
  • Patent number: 9146809
    Abstract: A method of operating a memory device storing ECCs for corresponding data is provided. The method includes writing an extended ECC during a first program operation, the extended ECC including an ECC and an extended bit derived from the ECC. The method includes overwriting the extended ECC with a pre-determined state during a second program operation to indicate the second program operation. The method includes, setting the ECC to an initial ECC state before the first program operation; during the first program operation, computing the ECC, changing the ECC to the initial ECC state if the computed ECC equals the pre-determined state; and changing the extended bit to an initial value if the ECC equals the initial ECC state. The method includes reading an extended ECC including an extended bit and an ECC for corresponding data, and determining whether to enable ECC logic using the extended ECC.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: September 29, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Shih-Chang Huang, Ken-Hui Chen, Chun-Hsiung Hung
  • Patent number: 9141473
    Abstract: A system implementing parallel memory error detection and correction divides data having a word length of K bits into multiple N-bit portions. The system has a separate error processing subsystem for each of the N-bit portions, and utilizes each error processing subsystem to process the associated N-bit portion of the K-bit input data. During memory write operations, each error processing subsystem generates parity information for the N-bit data, and writes the N-bit data and parity information into a separate memory array that corresponds to the error processing subsystem. During memory read operations, each error processing subsystem reads N-bits of data and the associated parity information. If, based on the parity information, an error is detected from the N-bit data, the error processing subsystem attempts to correct the error. The corrected N-bit data from each of the error processing subsystems are combined to reproduce the K-bit word.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: September 22, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Xiao Luo, Adrian E. Ong
  • Patent number: 9094047
    Abstract: Data that are stored in cells of a multi-bit-per cell memory, according to a systematic or non-systematic ECC, are read and corrected (systematic ECC) or recovered (non-systematic ECC) in accordance with estimated probabilities that one or more of the read bits are erroneous. In one method of the present invention, the estimates are a priori. In another method of the present invention, the estimates are based only on aspects of the read bits that include significances or bit pages of the read bits. In a third method of the present invention, the estimates are based only on values of the read bits. Not all the estimates are equal.
    Type: Grant
    Filed: March 11, 2009
    Date of Patent: July 28, 2015
    Assignee: Ramot at Tel Aviv University Ltd.
    Inventors: Simon Litsyn, Idan Alrod, Eran Sharon, Mark Murin, Menahem Lasser
  • Patent number: 9053050
    Abstract: A desirable number of segments for a multi-segment single error correcting (SEC) coding scheme is determined based on scrambling information for a memory. The desirable number of segments can be the minimum number of segments required to satisfy a masked write segmentation requirement and a multi-bit upset size requirement. In one aspect, the memory scrambling information can specify the different scrambling techniques employed by the memory (e.g., Input-Output (IO) cell scrambling, column scrambling, column twisting, strap distribution, etc.). Based on the scrambling information, a mapping between the logical structure and physical layout for the memory can be derived. The mapping can be used to determine the least number of segments needed to satisfy the masked write requirement and the multi-bit upset size requirement.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: June 9, 2015
    Assignee: Synopsys, Inc.
    Inventors: Hayk Grigoryan, Gurgen Harutyunyan, Samvel Shoukourian, Valery Vardanian, Yervant Zorian
  • Patent number: 9036661
    Abstract: Systems, devices, processors, and methods are described which may be used for the reception of a wireless broadband signal at a user terminal from a gateway via a satellite. A wireless signal may include a series of physical layer frames, each frame including a physical layer header and payload. The received signal is digitized and processed using various novel physical layer headers and related techniques to synchronize the physical layer frames and recover data from physical layer headers for purposes of demodulation and decoding.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: May 19, 2015
    Assignee: ViaSat, Inc.
    Inventors: Donald W. Becker, Matthew D. Nimon, William H. Thesling
  • Patent number: 8806316
    Abstract: Circuits, integrated circuits, and methods are disclosed for interleaved parity computation. In one such example circuit, an interleaved parity computation circuit includes a first parity circuit that receives a first set of bits and a second parity circuit that receives a second set of bits. The first set of bits includes a first parity bit, and is received in the first parity circuit during a first clock cycle. The first parity circuit generates a first signal indicative of the parity of the first set of bits. The second set of bits includes a second parity bit, and is received in the second parity circuit during a second clock cycle. The second parity circuit generates a second signal indicative of the parity of the second set of bits. A combining circuit combines the first signal and the second signal into an alert signal.
    Type: Grant
    Filed: January 11, 2012
    Date of Patent: August 12, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Guorjuh Thomas Hwang, Chia Jen Chang
  • Patent number: 8788900
    Abstract: According to one embodiment, a semiconductor memory device includes semiconductor memory chips in which data requested to be written. The data has one or more pieces of first data in a predetermined unit. The device includes a write controller that writes the first data and redundancy information calculated by using a predetermined number of pieces of the first data and used for correcting an error in the predetermined number of pieces of the first data into different semiconductor memory chips; and a storage unit that stores identification information and region specifying information so as to be associated with each other. The identification information associates the first data and the redundancy information, and the region specifying information specifies a plurality of storage regions in the semiconductor memory chips to which the pieces of the first data and the redundancy information associated with each other are written.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: July 22, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigehiro Asano, Kenichiro Yoshii, Kazuhiro Fukutomi, Shinichi Kanno
  • Patent number: 8782493
    Abstract: Methods of correcting data in a memory, and memories adapted to correct data, include prioritizing error correction of the read data in response to locations and likely states of known bad or questionable data positions of a segment of a memory array selected for reading.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: July 15, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Brady L. Keays, Shuba Swaminathan, William H. Radke
  • Patent number: 8689077
    Abstract: A computer system includes a memory controller coupled to a memory module containing several DRAMs. The memory module also includes a non-volatile memory storing row addresses identifying rows containing DRAM memory cells that are likely to lose data during normal refresh of the memory cells. Upon power-up, the data from the non-volatile memory are transferred to a comparator in the memory controller. The comparator compares the row addresses to row addresses from a refresh shadow counter that identify the rows in the DRAMs being refreshed. When a row of memory cells is being refreshed that is located one-half of the rows away from a row that is likely to loose data, the memory controller causes the row that is likely to loose data to be refreshed. The memory controller also includes error checking circuitry for identifying the rows of memory cells that are likely to lose data during refresh.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: April 1, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Dean A. Klein
  • Patent number: 8510633
    Abstract: Provided is an operation method which can be applied to a PRAM, an ReRAM, and a solid electrolyte memory which stores error correction codes, each of which comprises of symbols, each of which comprises bits, and which codes allow error correction in units of symbols. In the operation method, the respective symbols are read by using different reference cells 12. When a correctable error is detected in read data from data cells forming the error correction codes and corresponding to an input address, a data in a data cell corresponding to the error bit is corrected for a first error symbol of an one bit error pattern, and data in a reference cell that is used to read the second error symbol are corrected for a second error symbol related to a multi-bit error pattern.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: August 13, 2013
    Assignee: NEC Corporation
    Inventors: Noboru Sakimura, Tadahiko Sugibayashi, Ryusuke Nebashi
  • Patent number: 8510634
    Abstract: Methods include receiving data and an ECC code read from a memory array, generating an ECC code from the received data, and determining whether the received data is corrupted by evaluating the generated ECC code against the ECC code read from the memory array. If the received data is determined to be corrupted, a correction algorithm and a recorded likely state of a known bad/questionable bit of the received data may be used to correct error in the received data. Alternatively, if the received data is determined to be corrupted, the correction algorithm and a recorded location of a known bad/questionable bit of the received data may be used to correct error in the received data.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: August 13, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Brady L. Keays, Shuba Swaminathan, William H. Radke
  • Patent number: 8468422
    Abstract: A method for predicting and preventing uncorrectable errors that may occur while accessing memory in a computer system. The method involves detecting two or more correctable errors from two or more different physical addresses on each of two or more different bit positions from the same DIMM within a specified period of time, with all of the correctable errors occurring within the same checkword. The method also involves detecting two or more correctable errors from two or more different physical addresses on each of three or more different outputs from the same DRAM within a specified period of time, as long as the three outputs do not all correspond to the same relative bit position in their respective checkwords. This allows a computer system which encounters correctable errors to continue to reliably operate without the unnecessary replacement of functioning memory systems.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: June 18, 2013
    Assignee: Oracle America, Inc.
    Inventors: Stephen A. Chessin, Louis Tsien
  • Patent number: 8448256
    Abstract: According to an embodiment, a programmable logic device includes a plurality of logic blocks, memory and a logic unit. The logic blocks are grouped into one or more partitions. The memory stores authentication and partition information uploaded to the programmable logic device prior to partition programming. The logic unit authenticates programming access to the one or more partitions based on the authentication information and controls programming of the one or more partitions based on the partition information.
    Type: Grant
    Filed: February 2, 2009
    Date of Patent: May 21, 2013
    Assignee: Infineon Technologies AG
    Inventors: Joerg Borchert, Jurijus Cizas, Shrinath Eswarahally, Mark Stafford, Rajagopalan Krishnamurthy
  • Patent number: 8448034
    Abstract: According to one embodiment, a semiconductor memory device includes semiconductor memory chips in which data requested to be written. The data has one or more pieces of first data in a predetermined unit. The device includes a write controller that writes the first data and redundancy information calculated by using a predetermined number of pieces of the first data and used for correcting an error in the predetermined number of pieces of the first data into different semiconductor memory chips; and a storage unit that stores identification information and region specifying information so as to be associated with each other. The identification information associates the first data and the redundancy information, and the region specifying information specifies a plurality of storage regions in the semiconductor memory chips to which the pieces of the first data and the redundancy information associated with each other are written.
    Type: Grant
    Filed: September 23, 2010
    Date of Patent: May 21, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigehiro Asano, Kenichiro Yoshii, Kazuhiro Fukutomi, Shinichi Kanno
  • Patent number: 8438452
    Abstract: In one embodiment, a method provides determining one of an occurrence and a non-occurrence of an event, the one of the occurrence and the non-occurrence resulting in an event determination; and processing a code having an event bit, said processing in accordance with the determination and the code, by determining if the event bit corresponds to the event determination, and if the event bit does not correspond to the event determination, encoding the code to generate a poison bit that corresponds to the event determination.
    Type: Grant
    Filed: December 29, 2008
    Date of Patent: May 7, 2013
    Assignee: Intel Corporation
    Inventors: Rajat Agarwal, Scott Huddleston, Dennis Brzezinski
  • Patent number: 8418043
    Abstract: A method of error detection for a data packet, the method comprising the steps of: i) identifying a set of non-compliances (N), the non-compliances being illegal bit sequences according to a coding standard; ii) identifying a first subset (N+) of non-compliances that are to be treated as errors; iii) identifying a second subset (N.) of non-acceptable near-compliances; iv) decoding the data packet according to the coding standard; and v) adaptively deciding based on the first and second subsets whether to treat a detected non-compliance within the decoded data packet as an error or as an acceptable near-compliance.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: April 9, 2013
    Assignee: Entropic Communications, Inc.
    Inventors: Catalin-Bogdan Visan, Cosmin Ionescu, Eric Barrau
  • Patent number: 8402375
    Abstract: A system and method is disclosed for managing bookmark buttons on a web browser toolbar. A web browser stores the number of times it is used to navigate to a website. On navigating to a website a predetermined number of times, a bookmark button that links to the website is automatically generated and displayed on the toolbar. The number of bookmark buttons displayed at any one time is limited, and they are arranged by the number of times their associated websites have been viewed. On determining that a new website has been viewed more than a website associated with a currently displayed bookmark button, the currently displayed bookmark button is replaced by a new bookmark button that links to the new website.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: March 19, 2013
    Assignee: Google Inc.
    Inventors: Travis Michael Skare, Brandon Bilinski
  • Patent number: 8401038
    Abstract: Systems, devices, processors, and methods are described which may be used for the reception of a wireless broadband signal at a user terminal from a gateway via a satellite. A wireless signal may include a series of physical layer frames, each frame including a physical layer header and payload. The received signal is digitized and processed using various novel physical layer headers and related techniques to synchronize the physical layer frames and recover data from physical layer headers for purposes of demodulation and decoding.
    Type: Grant
    Filed: June 17, 2009
    Date of Patent: March 19, 2013
    Assignee: ViaSat, Inc.
    Inventors: Donald W. Becker, Matthew D. Nimon, William H. Thesling
  • Patent number: 8365039
    Abstract: In a non-volatile memory that reads a binary value from a storage cell by comparing the voltage level of a stored charge in that cell against a reference voltage, the accumulated errors in a range of memory locations may be analyzed to determined if there are more errors in one direction than the other (for example, more 0-to-1 errors than 1-to-0 errors). If so, the reference voltage may be adjusted up or down so that subsequent reads from that range may produce approximately the same number of errors in each direction. For multiple-bits-per-cell memories, where there are multiple reference voltages for each cell, each reference voltage may be adjusted separately by keeping track of the errors related to that particular threshold.
    Type: Grant
    Filed: September 16, 2008
    Date of Patent: January 29, 2013
    Assignee: Intel Corporation
    Inventors: Chun Fung Man, Jonathan E. Schmidt
  • Patent number: 8327228
    Abstract: Methods and apparatus relating to home agent data and memory management are described. In one embodiment, a scrubber logic corrects an error at a location in a memory corresponding to a target address by writing back the corrected version of data to the target location. In an embodiment, a map out logic maps out an index or way of a directory cache in response to a number of errors, corresponding to the directory cache, exceeding a threshold value. Other embodiments are also disclosed.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: December 4, 2012
    Assignee: Intel Corporation
    Inventors: Ganesh Kumar, Dheemanth Nagaraj, Vincent R. Freytag, Eric Delano, Gregory S. Averill
  • Patent number: 8307270
    Abstract: An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.
    Type: Grant
    Filed: September 3, 2009
    Date of Patent: November 6, 2012
    Assignee: International Business Machines Corporation
    Inventors: Kyu-Hyoun Kim, George L. Chiu, Paul W. Coteus, Daniel M. Dreps, Kevin C. Gower, Hillery C. Hunter, Charles A. Kilmer, Warren E. Maule
  • Patent number: 8291297
    Abstract: When an error correction code (ECC) unit finds uncorrectable errors in a solid state non-volatile memory device, a process may be used in an attempt to locate and correct the errors. This process may first identify ‘low confidence’ memory cells that are likely to contain errors, and then determine what data is more likely to be correct in those cells, based on various criteria. The new data may then be checked with the ECC unit to verify that it is sufficiently correct for the ECC unit to correct any remaining errors.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: October 16, 2012
    Assignee: Intel Corporation
    Inventors: Richard Coulson, Albert Fazio, Jawad Khan
  • Patent number: 8250438
    Abstract: Methods and apparatus are provided for improved iterative error-erasure decoding. A signal is decoded by obtaining a plurality of symbols associated with the signal and one or more corresponding reliability values; generating at least one erasure list comprised of L symbols and at least one shortened erasure list comprised of L? symbols, where L? is less than L; and constructing an erasure set by taking erasures from at least one of the erasure list and the shortened erasure list. A signal is also processed by generating one or more reliability values using a soft-output detector; generating an erasure list of symbols by comparing the reliability values to at least one reliability threshold value (or by sorting); and performing error erasure decoding using the erasure list. The size of the erasure list can optionally be adjusted using feedback information.
    Type: Grant
    Filed: July 31, 2009
    Date of Patent: August 21, 2012
    Assignee: Agere Systems Inc.
    Inventor: Erich F. Haratsch
  • Patent number: 8239732
    Abstract: Systems and/or methods that facilitate error correction of data are presented. An error correction code (ECC) control component facilitates enabling or disabling error correction of data being written to or read from memory, such as flash memory, based on ECC indicator data associated with a piece of data. The ECC control component can analyze data, parity code, and/or indicator data associated with the incoming data and/or data stored in the memory location where the incoming data is to be written to determine whether parity code can be written for the incoming data and/or whether error correction can be enabled with respect to the incoming data. Error correction can be enabled when an indicator bit associated with the data is unprogrammed (e.g., bit set to ‘1’ state) and can be disabled by programming the indicator bit (e.g., bit set to a ‘0’ state).
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: August 7, 2012
    Assignee: Spansion LLC
    Inventors: Tat Hin Tan, Ed Bautista, Bryan W. Hancock, Jackson Huang, Allan Parker
  • Patent number: 8201021
    Abstract: A method of creating backup files having less redundancy. The method creates a backup file by creating an overhead segment for each file that is to be backed up and creating a data segment containing the data that is to be backed up for each file. After creating the overhead segment and the data segment, the overhead segment is placed into an overhead stream data segment is stored in memory. The overhead segment is also positioned in the overhead stream with a pointer that identifies the data segment within the memory. For backups of subsequent servers or the same server at a later time, the backup software will create a separate overhead stream. However, a plurality of overhead streams may contain pointers to the same data segments such that redundant data segments do not need to be stored in a backup server.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: June 12, 2012
    Assignee: Symantec Corporation
    Inventors: Sunil Shah, Kirk L. Searls, Ynn-Pyng “Anker” Tsaur
  • Patent number: 8176390
    Abstract: Several methods and apparatus to single XOR operation weaver reconstruction of a failed drive of a raid are disclosed. A failed drive of the drive group implemented in a WEAVER code with an (n,t,t) layout is determined. A set of scatter/gather lists is produced from a number of the other drives of the drive group. A scatter/gather list is created by modifying a pointer data of the set of scatter/gather lists. An additional scatter/gather list is generated from the set of scatter/gather lists. A single XOR operation is performed on the data segment, the parity segment, the additional data segment and the additional parity segment to form a resulting scatter/gather list including a resulting data segment and a resulting parity segment. The resulting data segment and the resulting parity segment are written as sequenced in the resulting scatter/gather list to a replacement drive.
    Type: Grant
    Filed: April 16, 2009
    Date of Patent: May 8, 2012
    Assignee: LSI Corporation
    Inventor: Kevin Lee Kidney
  • Patent number: 8122321
    Abstract: Methods of data handling include receiving data having a previously-generated error correction code and generating one or more error correction codes for the data, with each error correction code corresponding to the data having one or more particular bits of the data in differing data states. Such methods further include comparing the generated one or more error correction codes to the previously-generated error correction code, and if a particular one of the generated one or more error correction codes matches the previously-generated error correction code, transmitting the data having its one or more particular bits in the data states corresponding to that particular one of the generated one or more error correction codes. Methods of data handling may further include prioritizing the error correction in response to at least locations of known bad or questionable bits of the data.
    Type: Grant
    Filed: August 9, 2010
    Date of Patent: February 21, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Brady L. Keays, Shuba Swaminathan, William H. Radke
  • Patent number: 8112693
    Abstract: An Error Control Code (ECC) apparatus applied to a memory of a Multi-Level Cell (MLC) method may include: a bypass control signal generator generating a bypass control signal; and an ECC performing unit that may include at least two ECC decoding blocks, determining whether to bypass a portion of the at least two ECC decoding blocks based on the bypass control signal, and/or performing an ECC decoding. In addition or in the alternative, the ECC performing unit may include at least two ECC encoding blocks, determining whether to bypass a portion of the at least two ECC encoding blocks based on the bypass control signal, and/or performing an ECC encoding. An ECC method applied to a memory of a MLC method and a computer-readable recording medium storing a program for implementing an EEC method applied to a memory of a MLC method are also disclose.
    Type: Grant
    Filed: October 3, 2007
    Date of Patent: February 7, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun Jin Kong, Seung-Hwan Song, Dong Hyuk Chae, Kyoung Lae Cho, Seung Jae Lee, Nam Phil Jo, Sung Chung Park, Dong Ku Kang