Abstract: The present invention provides a method and system for error correction in optical media data processing. The method includes demodulating a data using a conversion table; marking errors which occur during the demodulation; utilizing estimated values for the marked errors; and performing error correction. The method and system marks errors which occur during demodulation. A logic array is used to obtain estimated values for the marked errors. The marking of errors and the use of values from the logic array for the marked errors increases the probability of the C1 and C2 correction processes being able to correct the errors. Fewer “not correctable” data results. This increases the integrity of the read data.

Abstract: A low noise and lower power consumption receiver including a CRC error correction circuit which is constructed at low cost, prolongs a life of a battery and enhances a receiving sensitivity. The receiver comprises a data processing unit which continuously determines errors in received data encoded by a CRC code and corrects them by comparing with reference syndrome patterns, a microprocessor circuit including a data RAM connected with local data buses and local address buses and a serial data receiving apparatus including state control means, a synchronizing circuit, an ID comparing circuit and a circuit for gating system clock. The high performance and low power consumption receiver may be realized with less additional circuits, having more flexibility to the increase of services.

Abstract: A recording apparatus is provided with a recording medium, an error correction circuit and an error processing circuit. The error correction circuit corrects errors in read data which are read from the recording medium. The error processing circuit inserts a data pattern in data which are output from the error correction circuit in a case where a missing error remains in the data. The data pattern indicates that the missing error remains.

Abstract: System and methods for propagating error status over an error checking and correcting (ECC) protected channel. A first device receives data and an error status associated with the data. The first device generates check bits for the data based on a first ECC code and combines the check bits with the data to form one or more code words. The first device sends the code words across the channel where the first device inserts a triple error into a nibble of at least one codeword sent if the error status indicated an uncorrectable error. A second device connected to the channel receives the code words sent across the channel. The second device detects triple errors within a nibble of any code word and any other single error in the code word using a second ECC code, where the second ECC code is the first ECC code with columns for check bits inserted.

Abstract: One aspect of the invention provides a novel scheme to preserve the failure state of a memory location. According to one embodiment, the data is read from a memory location in a read-destructive memory device. If the data is found to be valid (uncorrupted) it is written back to the memory location from where it was read in order to preserve it. If the data is found to be invalid (corrupted) then a failure codeword is written in the memory location to indicate a failure of the memory location. The failure codeword may be preselected or dynamically calculated so that it has a mathematical distance greater than all correctable data patterns.

Abstract: An enhanced interleave type error correction method is provided in which decoding of an enhanced interleave block is done. Subsequently the decoding may be done by decoding the estimated codewords multiple times using a single error correction code. In addition, a decoder and a digital communication system for implementing the enhanced interleave type error correction method are provided.

Abstract: The error correcting decoder using an erasure flag process for a digital signal, according to the present invention, comprises: a row code word corrector for correcting errors in each row; a column code word corrector for correcting errors in each column; a first counter for counting the respective numbers of the uncorrectable rows and of the error corrected rows; a second counter for counting the number of error corrected symbols in each column; a storage device for storing the states of the corrected symbols; and an erasure flag selector for appropriately setting erasure flags for each column, based on the count results and the stored data.

Abstract: A burn-in testing system for evaluating a circuit under test, the system including a burn-in board having a plurality of receptacles, at least one of which being sized to receive the circuit under test, test interface circuitry supported by the board and coupled to the receptacles, the test interface circuitry including a transmitter and receiver; power conductors supported by the board, coupled to the receptacles and configured to be connected to a power supply to power the circuit under test during burn-in testing, control and data signal conductors, a bum-in oven having a compartment selectively receiving the burn-in board and being configured to apply heat within the compartment, and an interrogator unit supported by the burn-in oven, the interrogator unit being configured to send commands to the test interface circuitry to exercise the circuit under test optically or via radio communication and to receive responses to the commands optically or via radio communication.

Abstract: A synchronization detector has three registers to memorize individual patterns of three successive frames. A decoder produces a frame location signal on the basis of the individual patterns. A pointer circuit counts the number of the frame location signal to produce a pointer signal. The decoder produces a count-up signal when it can decode the individual patterns. The decoder produces a reset signal when it can not decode the individual patterns. A counter counts the count-up signal and is reset by the reset signal. A register holds a predetermined value. A comparator compares the count value of the counter with the predetermined value. The comparator produces a comparing order signal when the predetermined value is less than the count value. A comparing circuit compares the frame location signal with the pointer signal. If the frame location signal is not equal to the pointer signal, it happens that an optical head skips a few frames or slips to a next truck.

Abstract: Encoders, syndrome generators, and methods for generating ECC check bytes and partial syndromes from a user data sector using a single RAM unit. The user data includes a plurality of data bytes. The encoder includes a storage unit and encoder circuitry. The storage unit is configured to receive and store a plurality of interim check bytes. The encoder circuitry is configured to receive the data bytes of the user data sector sequentially and the interim check bytes to generate a plurality of new interim check bytes in accordance with a generator polynomial. The new interim check bytes is generated after each data bytes of the data sector is received. The encoder circuitry is arranged to receive the interim check bytes from the storage unit such that the encoder circuitry generates the new interim check bytes and stores the generated new interim check bytes in the storage unit as the interim check bytes.

Abstract: A hard disk drive replaces a defective sector with a spare sector. When accessing a track having the defective sector, all normal sectors except for the defective sector are formerly accessed and then, a re-allocation sector which has replaced the defective sector is later accessed. In this manner, the number of searches is reduced during reading/writing (accessing) a track having defectives, thereby improving a data transmission of a hard disk drive.

Abstract: A coding and decoding system which uses CRC check bits is disclosed. When a coding apparatus performs coding, symbol interleaving is performed after coding by an outer code of a concatenated code, and coding by an inner code is performed after CRC check bits are added. Then, upon decoding by a decoding apparatus, error detection using the CRC check bits is performed after decoding of the inner code. After symbol deinterleaving is performed, decoding of the outer code by erasure decoding or error correction is performed depending upon the number of symbols included in a frame in which an error has been detected.

Abstract: In a transmission system or recording system, a detector (16,30) using quality measures indicating the quality of the received signal is applied.In contradistinction with the prior art system the quality measure comprises the deviation of the position of transitions in the input signal from the nominal positions of said transitions. The advantage of using this type of quality measure is that the required information for determining it, is already available within the PLL (34) needed for clock recovery.

Abstract: A method and system for resolving error or erasure in binary data streams read back using MR heads from a cyclic, multitracked recording medium. The method assesses whether an erasure or error was coincident with a thermal asperity. If the coincidence occurred, the method branches to and executes an ordered list of data recovery procedures tuned to thermal asperity. This list emphasizes early use of burst ECC correction and alteration of MR head and read channel attributes.

Abstract: An error correcting memory system, which writes and reads m-bit data and an error marking n-bit pointer by a predetermined rule, includes a first memory for m-bit data; a second memory for the n-bit pointer, an address generating unit for generating address signals for the first and second memories by a predetermined rule, and a writing/reading control signal generating unit for generating the respective writing and reading control signals of the first and second memories by receiving the writing and reading control signals and responding to a data/pointer differentiating signal. Therefore, the memory size of the error correcting memory system can be reduced.

Abstract: The original firmware of a computing device is stored in a fixed non-volatile ROM-type memory while any subsequently issued replacement firmware correcting or upgrading erroneous firmware contained within the original firmware is stored in a reprogrammable EEPROM-type non-volatile memory. The locations in the fixed and reprogrammable memories storing the corresponding erroneous and replacement firmware, respectively, are identified in a data table that is also stored in the reprogrammable memory. A field programmable gate array connected to the reprogrammable memory uses the data table to identify computing device requests to the fixed memory for erroneous firmware and in response thereto inhibit output of erroneous firmware. The gate array further uses the data table to access the reprogrammable memory and output corresponding replacement firmware in substitution for the device requested original, but erroneous, firmware.

Abstract: A multiple bank memory device is described which can be tested by accessing the multiple memory banks simultaneously. The memory includes a test mode trigger which initiates a test which writes and reads from memory cells located in different memory banks. Error detection circuitry evaluates data read from different memory banks and determines if a defect is present in the memory cells. Different test patterns and techniques are described for identifying defective memories.

Abstract: Channel data obtained from a reproduced signal is input to a demodulation ROM as an address and demodulated. In the demodulated channel data, the data whose data pattern is not consistent with a 2-7 modulation method is recognized as an error data. When a resync code, given in the channel data at every 15 bytes is not detected within a predetermined time period, a resync code undetected signal is generated. The demodulated data is arranged in a matrix, and the position of the error data in the matrix and the resync code undetected generation position are specified. An error correction circuit carries out the error correction (erasure correction) by using these positions and an error correction code relating to one direction of a row or a column of the matrix.

Abstract: The invention relates to a multi-level storage device including: at least a first plurality of cells storing an identical first number (greater than one) of binary data, and at least a corresponding for second plurality of cells for storing a second number of error check and correcting words equal to said first number, said words being respectively associated with sets of binary data, each including at least one binary data for each cell in said first plurality. In this way, many of the known error correction algorithms can be applied to obtain comparable results to those provided by binary memories. In addition, where multi-level cells are used for storing the error check and correcting words, the device dimension requirements can also be comparable.