Solid State Memory Patents (Class 714/773)
  • Patent number: 11119848
    Abstract: The present disclosure is directed to logic based read sample offset operations in a memory sub-system. A processing device performs a first read, a second read, and a third read of data from a memory devices using a first center value corresponding to a first read level threshold, a negative offset value, and a positive offset value, respectively. The processing device performs a XOR operation on results from the first and second reads to obtain a first value and a XOR operation on results from the second and third reads to obtain a second value. The processing device performs a first count operation on the first value to determine a first difference bit count and a second count operation on the second value to determine a second difference bit count. The processing device can store or output the first difference bit count and the second difference bit count.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: September 14, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Bruce A. Liikanen, Michael Sheperek
  • Patent number: 11120879
    Abstract: A processing device determines a set of difference error counts corresponding to multiple programming distributions of a memory sub-system. A valley having a lowest valley margin is identified based on a comparison of the set of difference error counts. Based on the set of difference error counts, a program targeting rule from a set of rules. A program targeting operation is performed, based on the program targeting rule, a program targeting operation to adjust a voltage associated with an erase distribution of the memory sub-system.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: September 14, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Bruce A. Liikanen, Michael Sheperek, Larry J. Koudele
  • Patent number: 11112971
    Abstract: A storage device includes one or more FMPKs including a FM chip capable of storing data and a storage controller that controls storing of write data of a predetermined write request for the FMPK. The FMPK includes a compression/decompression circuit that compresses data according to a second compression algorithm different from a first compression algorithm. The storage controller compresses data using the first compression algorithm, and determines whether the write data will be compressed using the storage controller or the compression/decompression circuit based on a predetermined condition. The write data is compressed by the determined storage controller or compression/decompression circuit and is stored in the FMPK.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: September 7, 2021
    Assignee: HITACHI, LTD.
    Inventors: Ai Satoyama, Tomohiro Kawaguchi, Yoshihiro Yoshii
  • Patent number: 11106518
    Abstract: A method for error correction in a memory system includes determining a bit error ratio for a memory block of the memory system during a read operation. The method further includes determining whether the bit error ratio is between a first threshold and a second threshold. The method further includes based on a determination that the bit error ratio is between the first threshold and the second threshold, performing a select gate drain (SGD) read operation on a SGD word line of the memory block. The method further includes generating first soft bit data using SGD data corresponding to the SGD read operation. The method further includes performing a low-density parity-check correction using the first soft bit data on the memory block.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: August 31, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Indu Kumari, Narendhiran CR, Abhinand Amarnath, Balakumar Rajendran, Muralitharan Jayaraman
  • Patent number: 11086705
    Abstract: A computer-implemented method, according to one embodiment, includes: performing a first read of one or more pages in a first page region of a first block. In response to determining that the highest RBER experienced during the first read is not in a first predetermined range, a first calibration procedure is performed on the one or more pages. A second read of the one or more pages is performed. In response to determining that the highest RBER experienced during the second read is not in a second predetermined range, a second calibration procedure on the one or more pages is performed, and a third read of the one or more pages is performed. In response to determining that the highest RBER experienced during the third read is not in the second predetermined range, a reliability counter which corresponds to the first page region of the first block is incremented.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: August 10, 2021
    Assignee: International Business Machines Corporation
    Inventors: Nikolaos Papandreou, Roman A. Pletka, Sasa Tomic, Nikolas Ioannou, Charalampos Pozidis, Timothy J. Fisher, Aaron D. Fry
  • Patent number: 11086719
    Abstract: Disclosed in some examples are methods, systems, storage devices, and machine readable mediums that utilize the ability of ECC to correct errors to actively prevent errors. The memory device determines whether a request to place data of a requested value at a requested location in the storage media is likely to interfere with other data stored at other locations on the storage media, and if so, changes the requested value to a second value that will not interfere (or has a lower probability of interfering) with neighboring data. The second value may be corrected to the requested value when a read request is made for that data using ECC.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: August 10, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Amer Aref Hassan, Roy D. Kuntz, David Anthony Lickorish
  • Patent number: 11080135
    Abstract: An example apparatus to monitor memory includes an error manager to compare a first memory location of a first error in the memory to a plurality of memory locations in an error history log, the plurality of memory locations previously identified in the error history log based on errors detected in the memory locations, ones of the memory locations associated with corresponding counters that track the errors detected in the memory locations, and update a first one of the counters corresponding to the first memory location when a first address of the first memory location matches a second address of one of the memory locations in the error history log. The example apparatus further includes a command generator to transmit a command to an error corrector to perform error correction on the first memory location when the first one of the counters satisfies a threshold.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: August 3, 2021
    Assignee: INTEL CORPORATION
    Inventors: Yingwen Chen, Anil Agrawal, Fang Yuan, Qing Huang
  • Patent number: 11074182
    Abstract: Systems, apparatuses, and methods related to three tiered hierarchical memory systems are described herein. A three tiered hierarchical memory system can leverage persistent memory to store data that is generally stored in a non-persistent memory, thereby increasing an amount of storage space allocated to a computing system at a lower cost than approaches that rely solely on non-persistent memory. An example apparatus may include a persistent memory, and one or more non-persistent memories configured to map an address associated with an input/output (I/O) device to an address in logic circuitry prior to the apparatus receiving a request from the I/O device to access data stored in the persistent memory, and map the address associated with the I/O device to an address in a non-persistent memory subsequent to the apparatus receiving the request and accessing the data.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: July 27, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Vijay S. Ramesh, Anton Korzh, Richard C. Murphy, Scott Matthew Stephens
  • Patent number: 11061768
    Abstract: A black box device for a vehicle includes a data storage system for recording event data fed to the black box from various vehicle sensors. The data storage system includes a memory having memory cells and a controller in communication with the memory. The controller is configured to receive data and determine one or more memory cells as a destination for the data to be written. The controller is configured to determine a wear level of the memory cells and select a subset of program states of the memory cells based on the wear level; and program the memory cells using respective subsets of program states for each respective memory cell.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: July 13, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Idan Alrod, Judah Gamliel Hahn, Ariel Navon, Eran Sharon, Dudy Avraham
  • Patent number: 11056177
    Abstract: A memory system includes a memory device configured to store data through a write operation and output the stored data as read data through a read operation; a buffer memory configured to store the read data output from the memory device; a controller configured to control the memory device such that the memory device performs the read operation in response to a read request received from a host, and to control the buffer memory to store the read data in the buffer memory. When the read request corresponds to an asynchronous read operation, the controller may allocate a partial area of the buffer memory as storage space for the read data after the read operation of the memory device is completed.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: July 6, 2021
    Assignee: SK hynix Inc.
    Inventors: Yong Jin, Seung Ok Han, Sun Hong Min
  • Patent number: 11049531
    Abstract: A nonvolatile memory device includes a memory cell array, a page buffer including a first latch configured to store data to be programmed in a first state, a second latch configured to store the data in a second state, and a third latch configured to store the data in a third state when the data is received from an external apparatus, and a control logic configured to control the page buffer to store the data of the first state in the first latch, the data of the second state in the second latch, and the data of the third state in the third latch when a multi-conversion program command and the data are received from the external apparatus.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: June 29, 2021
    Assignee: SK hynix Inc.
    Inventor: Do Hyun Kim
  • Patent number: 11038533
    Abstract: A computer-implemented method includes encoding an array of (p?1)×k symbols of data into a p×(k+r) array. The method includes p is a prime number, r?1, and k?p. The method includes each column in the p×(k+r) array has an even parity and symbol i in column r+j, for 0?i?p?1 and 0?j?r?1, is the XOR of symbols in a line of slope j taken with a toroidal topology modulo p in the k columns starting in symbol i of column 0.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: June 15, 2021
    Assignee: International Business Machines Corporation
    Inventors: Mario Blaum, Steven R. Hetzler
  • Patent number: 11036596
    Abstract: A system includes a plurality of solid-state storage devices and a storage controller coupled to the plurality of solid-state storage devices. The storage controller includes a processing device, the processing device to receive a write request from a host computing device. The write request includes data to be stored at one or more of the plurality of solid-state storage devices. The processing device is to send an acknowledgement to the host computing device in response to receipt of the write request, store the data at the one or more of the plurality of solid-state storage devices, determine whether the data stored at the one or more of the plurality of solid-state storage devices is readable, and in response to determining that the data is readable, notify, by the processing device, the host computing device that the stored data is readable from the one or more of the plurality of solid-state storage devices.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: June 15, 2021
    Assignee: Pure Storage, Inc.
    Inventors: Gordon James Coleman, Andrew R. Bernat, Peter E. Kirkpatrick
  • Patent number: 11017112
    Abstract: The present invention discloses a system for storing a blockchain on a distributed network. The system includes a distributed network containing a plurality of nodes. The system stripes a blockchain into individual blocks where each individual block is separately encrypted and stored on a different node of the distributed network. The system forms a parity block from the individual blocks striped from the single blockchain. The parity block is separately encrypted and stored on a node of the distributed network separate from the other nodes storing the individual blocks for the blockchain. The system uses a blockchain distributed network map identifying where all of the individual blocks and the parity block are stored on the distributed network to reassemble all of the individual blocks into an undivided single blockchain.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: May 25, 2021
    Inventor: Tyson York Winarski
  • Patent number: 10977122
    Abstract: Embodiments described herein provide a system for facilitating modulation-assisted error correction. The system can include a plurality of flash memory cells, an organization module, a mapping module, and a modulation module. During operation, the organization module groups bits of a cluster of cells in the plurality of flash memory cells into a first group and a second group. A respective of the first and second groups includes bits from a respective cell of the cluster of cells. The mapping module generates a modulation map that maps a subset of bits indicated by the first group in such a way that the subset of bits is repeated in a respective domain of bits indicated by the second group. The modulation module then programs user data bits in the cluster of cells based on the modulation map.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: April 13, 2021
    Assignee: Alibaba Group Holding Limited
    Inventor: Shu Li
  • Patent number: 10969987
    Abstract: A memory system includes: a memory cell array including a plurality of memory blocks; a peripheral circuit configured to perform a read operation on a selected memory block among the plurality of memory blocks and a backup program operation on a backup block among the plurality of memory blocks; and a control circuit configured to control the peripheral circuit to backup data of logical pages included in the selected memory block in the backup block, when a read count of a selected physical page of the selected memory block is equal to or larger than a set value in the read operation on the selected memory block.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: April 6, 2021
    Assignee: SK hynix Inc.
    Inventors: Hyun Woo Lee, Young Gyun Kim
  • Patent number: 10963335
    Abstract: A data storage device is provided. The data storage device includes a flash memory and a controller. The flash memory includes a plurality of blocks for storing data and each block includes a plurality of pages. The controller is configured to convert a host read command into a read-operation instruction to the flash memory to perform a default read operation to read page data from the flash memory. The default read operation has a default read threshold voltage. In response to a failure of the default read operation, the controller is configured to sequentially perform a read operation on the flash memory using a read threshold voltage with respect to each entry of a plurality of entries in a read-retry table, and replace the default read threshold voltage with the read threshold voltage corresponding to the read operation being successfully performed.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: March 30, 2021
    Assignee: SHANNON SYSTEMS LTD.
    Inventor: Xueshi Yang
  • Patent number: 10956323
    Abstract: Examples include techniques for emulating a non-volatile dual inline memory module (NVDIMM) in a computing platform using a non-volatile storage device. When a power up event occurs for the computing platform, a host memory buffer may be allocated in a system memory device and a backing store for the host memory buffer may be copied from the non-volatile storage device to the host memory buffer in the system memory device. When a power down event or a flush event occurs for the computing platform, the host memory buffer may be copied from the system memory device to the corresponding backing store for the host memory buffer in the non-volatile storage device. Thus, virtual NVDIMM functionality may be provided without having NVDIMM hardware in the computing platform.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: March 23, 2021
    Assignee: INTEL CORPORATION
    Inventors: Dale J. Juenemann, James A. Boyd, Robert J. Royer, Jr.
  • Patent number: 10949099
    Abstract: A memory system includes: a memory device including a plurality of memory blocks; and a controller suitable for selecting one or more first memory blocks based on a predetermined condition among the plurality of the memory blocks in a booting section, and increasing a read reclaim count value of one or more second memory blocks among the one or more first memory blocks for which a number of failed bits of read data exceeds a predetermined threshold.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: March 16, 2021
    Assignee: SK hynix Inc.
    Inventor: Se-Hyun Kim
  • Patent number: 10929474
    Abstract: The present disclosure includes apparatuses and methods for proactive corrective actions in memory based on a probabilistic data structure. A number of embodiments include a memory, and circuitry configured to input information associated with a subset of data stored in the memory into a probabilistic data structure and proactively determine, at least partially using the probabilistic data structure, whether to take a corrective action on the subset of data stored in the memory.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: February 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Saeed Sharifi Tehrani, Sivagnanam Parthasarathy
  • Patent number: 10922174
    Abstract: A memory device can include three-dimensional memory entities each including a plurality of two-dimensional memory entities. A controller can read data from the memory at a first resolution and collect error rate information from the memory at a second resolution including a portion of a two-dimensional memory entity. The controller can determine a quantity of two-dimensional memory entities that have a greater error rate than a remainder of the two-dimensional memory entities based on the error rate information. The controller can determine a quantity of portions of three-dimensional memory entities that have a greater error rate than a remainder of the portions of three-dimensional memory entities based on the error rate information excluding error rate information for portions of the two-dimensional memory entities associated with the quantity of two-dimensional memory entities.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: February 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Justin M. Eno, Samuel E. Bradshaw
  • Patent number: 10917112
    Abstract: A first error-detecting code (EDC) is computed based on a first segment of a block of information that is to be encoded, and a second EDC is computed based on at least a second segment of the block of information. The first EDC is masked with a first masking segment and the second EDC with a second masking segment to generate a first masked EDC and a second masked EDC. The first masking segment and the second masking segment are associated with a target receiver of the block of information. A codeword is generated based on a code and an input vector that includes the first segment, the first masked EDC, the second segment, and the second masked EDC. This type of coding could be useful to support early termination of blind detection at a decoder, for example.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: February 9, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yiqun Ge, Ran Zhang, Nan Cheng, Wuxian Shi
  • Patent number: 10915249
    Abstract: The present disclosure includes apparatuses and methods for in-memory operations. An example apparatus includes a memory device including a plurality of subarrays of memory cells, where the plurality of subarrays includes a first subset of the respective plurality of subarrays and a second subset of the respective plurality of subarrays. The memory device includes sensing circuitry coupled to the first subset, the sensing circuitry including a sense amplifier and a compute component. The apparatus also includes a controller configured to direct a first movement of a number of data values from a subarray in the second subset to a subarray in the first subset and performance of a sequential plurality of operations in-memory on the number of data values by the first sensing circuitry coupled to the first subset.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: February 9, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Perry V. Lea
  • Patent number: 10915399
    Abstract: A storage system includes: a control processor, configured to: read user data with a read threshold, detect an uncorrectable error in the user data, detect a sector balanced when the number of 1's and 0's in the user data is within the difference stored in a range register, apply an XOR RAID recovery to correct the uncorrectable error in the user data; and a non-volatile memory array, coupled to the control processor, configured to store the user data; and wherein the control processor is further configured to forego an additional read of a sector N with a different value of the read threshold when the sector balanced initiates the XOR RAID recovery.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: February 9, 2021
    Assignee: CNEX LABS, Inc.
    Inventors: Jun Tao, Chih-Chieng Cheng, Bo Jiang, Shanying Luo
  • Patent number: 10884628
    Abstract: Improving performance of a read in a memory system. Various methods include: reading data from a word line in a memory block, where during the read, associated parameters are generated that include: a value indicative of a throughput time, and a value indicative of a bit error rate (BER); retrieving the value indicative of the throughput time and the value indicative of the BER; and performing a read improvement process if the value indicative of the throughput time is above a threshold value. The method also includes performing the read improvement process by: flagging the memory block if the value indicative of the BER is at or below and expected BER; and performing cleanup operations if the value indicative of the BER is higher than the expected BER.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: January 5, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Niles Yang, Phil Reusswig, Alexandra Bauche
  • Patent number: 10877840
    Abstract: A storage system includes memory cells arranged in an array and a memory controller coupled to the memory cells for controlling operations of the memory cells. The memory controller is configured to perform a read operation in response to a read command from a host, perform a first soft decoding of data from the read operation using existing LLR (log likelihood ratio) values stored in the memory controller, update existing LLR values using LLR values from neighboring memory cells and existing weight coefficients that account for influence from the neighboring memory cells. The memory controller is also configured to perform a second soft decoding using the updated LLR values. If the second soft decoding is successful, the memory controller performs a recursive update of weight coefficients to reflect updated influence from neighboring memory cells and stores the updated weight coefficient in the memory controller for use in further decoding.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: December 29, 2020
    Assignee: SK hynix Inc.
    Inventors: Naveen Kumar, Aman Bhatia, Yu Cai, Fan Zhang
  • Patent number: 10866859
    Abstract: A non-volatile (NV) memory accessing method using data protection with aid of look-ahead processing, and associated apparatus such as memory device, controller and encoding circuit thereof are provided. The NV memory accessing method may include: receiving a write command and data from a host device; obtaining at least one portion of data to be a plurality of messages, to generate a plurality of parity codes through look-ahead type encoding, wherein regarding a message: starting encoding a first partial message to generate a first encoded result; applying predetermined input response information to a second partial message to generate a second encoded result, and combining the first and the second encoded results to generate a first partial parity code; and starting encoding the message to generate a second partial parity code, and outputting the first and the second partial parity codes to generate a parity code; and writing into the NV memory.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: December 15, 2020
    Assignee: Silicon Motion, Inc.
    Inventor: Shiuan-Hao Kuo
  • Patent number: 10838638
    Abstract: The present invention provides a flash memory controller, wherein the flash memory controller includes a read-only memory, a microprocessor and a decoder, wherein the read-only memory is configured to store a program code, the microprocessor is configured to execute the program code to access a flash memory module, and the decoder includes a hard decoding function and a soft decoding function. In the operations of the flash memory controller, when the flash memory controller and the flash memory module are powered-on, the flash memory controller reads data from a specific block of the flash memory module, and the decoder determines if disabling the soft decoding function or not according to a status of the specific block or a status of the data.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: November 17, 2020
    Assignee: Silicon Motion, Inc.
    Inventor: Wen-Sheng Lin
  • Patent number: 10831652
    Abstract: In a memory system and an operating method thereof, the method includes: receiving a read command and a read logical address; reading a raw map slice stored in a nonvolatile memory device, in a map read phase, in response to the read command, wherein the raw map slice includes a read physical address corresponding to the read logical address; generating a compressed map slice by compressing the raw map slice; storing a compression class corresponding to a ratio of a size of the compressed map slice to a size of the raw map slice in a compression class description table; storing the compressed map slice in a buffer memory; and reading data corresponding to the read command from the nonvolatile memory device, in a data read phase, based on the compressed map slice stored in the buffer memory.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: November 10, 2020
    Assignee: SK hynix Inc.
    Inventor: Dong Sop Lee
  • Patent number: 10824502
    Abstract: Methods, apparatuses, and systems for error recovery in memory devices are described. A die-level redundancy scheme may be employed in which parity data associated with particular die may be stored. An example apparatus may include a printed circuit board and memory devices. Each memory device may be each disposed on a planar surface of the printed circuit board and may each include two or more memory die. The apparatus may also include multiple channels communicatively coupled to the two or more memory die and a memory controller. The memory controller may be communicatively coupled to the multiple channels and may deterministically maintain a redundancy scheme via data transmission through the multiple channels. The memory controller may also update memory operation information appended to the enhanced codeword in response to a memory operation request.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: November 3, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Reshmi Basu
  • Patent number: 10802958
    Abstract: A storage device determines whether or not reading target data subjected to a first conversion process is divided and stored into multiple pages. When the data subjected to the first conversion process is stored in one of a plurality of pages, the data is read from the page, and a second conversion process for returning the data to a state before the data is subjected to the first conversion process is executed to the data. When the reading target data is divided and stored into two or more of the plurality of pages, a portion of the data is read from each of the two or more pages in which the portion of the data is stored, the portion of the data is stored in the buffer memory, the data subjected to the first conversion process is restored, and the second conversion process is executed to the restored data.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: October 13, 2020
    Assignee: HITACHI, LTD.
    Inventors: Hiroki Fujii, Hideyuki Koseki, Atsushi Kawamura
  • Patent number: 10796772
    Abstract: A semiconductor memory device includes a memory cell array, a peripheral circuit, and a control logic. The memory cell array includes a plurality of memory blocks. The peripheral circuit performs a read operation on a selected memory block among the plurality of memory blocks. The control logic controls the read operation of the peripheral circuit. The selected memory block is coupled to a plurality of bit lines, and the plurality of bit lines are grouped into a plurality of bit line groups. The peripheral circuit performs data sensing by applying different reference currents to the plurality of bit line groups, respectively.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: October 6, 2020
    Assignee: SK hynix Inc.
    Inventor: Heon Jin Choo
  • Patent number: 10783035
    Abstract: One embodiment provides a system and method for storing data. During operation, the system receives a to-be-written data chunk, sends the to-be-written data chunk to a first and second storage devices. The system performs first and second error-correction-code (ECC) encoding operations on the to-be-written data chunk prior to writing the to-be-written data chunk to the first and second storage media associated with the first and second storage devices, respectively. The first storage medium has a first access granularity and a first raw-error-rate (RER). The second storage medium has a second access granularity and a second RER. The first access granularity is smaller than the second access granularity, the first RER is greater than the second RER, and the second ECC encoding operation has a stronger error-correction capability than the first ECC encoding operation.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: September 22, 2020
    Assignee: Alibaba Group Holding Limited
    Inventor: Shu Li
  • Patent number: 10783982
    Abstract: A data storage system can receive a data write request to write data to a physical address of a non-volatile semiconductor memory prior to detecting an error while storing the write data to the physical address. The detected error is corrected with a monitor module connected to the non-volatile semiconductor memory and a counter associated with the physical address is incremented with the monitor module in response to the corrected error. The write data can be subsequently read to a host in response to a data read request.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: September 22, 2020
    Assignee: Seagate Technology LLC
    Inventor: Stephen H. Perlmutter
  • Patent number: 10783959
    Abstract: A method of compensating charge loss and source line bias in programing of non-volatile memory device including the steps of reading a previous program page with a low reference voltage to make an original previous program pattern, merging the original previous program pattern and a current program pattern to make a merged program pattern, reading the previous program page with a high reference voltage to make a verified previous program pattern, and merging the verified previous program pattern and the merged program pattern to make a compensated current program pattern.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: September 22, 2020
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Chun-Yi Tu, Ming-Chang Tsai, Jui-Lung Weng
  • Patent number: 10783024
    Abstract: A computer-implemented method, according to one embodiment, includes: detecting that an error count resulting from reading a first page in a block of storage space in memory is above a first threshold, and reading a second page in the block of storage space. The second page is one which had a highest error count of the pages in the block of storage space following a last calibration of the block of storage space. Moreover, a determination is made as to whether an error count resulting from reading the second page is above the first threshold. In response to determining that the error count resulting from reading the second page is above the first threshold, the block of storage space is calibrated. Other systems, methods, and computer program products are described in additional embodiments.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: September 22, 2020
    Assignee: International Business Machines Corporation
    Inventors: Sasa Tomic, Timothy J. Fisher, Nikolaos Papandreou, Roman A. Pletka, Nikolas Ioannou, Charalampos Pozidis, Aaron D. Fry
  • Patent number: 10768855
    Abstract: A memory management method is provided. The method includes: performing a read operation on a target word line; reading a plurality of target physical pages of the target word line to obtain a plurality of hard bit codewords respectively corresponding to the target physical pages; generating soft information of each of a plurality of target memory cells of the target word line according to the hard bit codewords; identifying a plurality of confidence values corresponding to the target physical pages of each of the target memory cells according to a plurality of confidence tables and the soft information of the target memory cells; and performing an adjusted preset decoding operation according to the confidence values and the soft information, so as to obtain a plurality of final decoded codewords respectively corresponding to the target physical pages and complete the read operation.
    Type: Grant
    Filed: May 26, 2019
    Date of Patent: September 8, 2020
    Assignee: Shenzhen EpoStar Electronics Limited CO.
    Inventor: Yu-Hua Hsiao
  • Patent number: 10761749
    Abstract: First and second vectors each respectively having first and second magnitudes and first and second phase angles relative to a reference axis are determined by a processing device based on a set of error values corresponding a current processing level for processing data in memory operations on memory cells of a memory component. An estimated processing level offset is generated based on a comparison between at least one of a difference between the first magnitude and the second magnitude or a difference between the first phase angle and the second phase angle. An updated processing level is generated based on the estimated processing level offset, and the updated processing level replaces the current processing level.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: September 1, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Michael Sheperek, Larry J. Koudele
  • Patent number: 10754768
    Abstract: A memory system includes a nonvolatile memory device; In an embodiment, a memory system comprising: a nonvolatile memory device; a working memory configured to store a first layer and a second layer as firmwares, each of which drives the nonvolatile memory device; a control component configured to control the nonvolatile memory device based on the firmwares; a buffer memory configured to store a first table which is managed by the first layer and a second table which is managed by the second layer; and a memory controller configured to store a descriptor for setting information of the nonvolatile memory device, and interface with the nonvolatile memory device based on control of the control component, wherein the second layer stores position information of the descriptor in the second table, and wherein the first layer accesses the memory controller by referring to the second table.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: August 25, 2020
    Assignee: SK hynix Inc.
    Inventor: Joo Young Lee
  • Patent number: 10747471
    Abstract: A data writing method, a memory control circuit unit, and a memory storage device are provided. The method includes: determining whether to use a first programming mode or a second programming mode to program memory cells according to a first data amount and a second data amount; when the first data amount is greater than the second data amount, programming the memory cells by using the first programming mode; and when the first data amount is not greater than the second data amount, programming the memory cells by using the second programming mode.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: August 18, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chao-Han Wu
  • Patent number: 10740181
    Abstract: Methods and systems for rebuilding a failed storage device in a data storage system. For example, a method including identifying a first garbage collection group (GCG) in a storage array for garbage collection; extracting valid data and redundancy information from functioning storage devices in the storage array associated with the first GCG; reconstructing data of a failed storage device associated with the first GCG based on the extracted valid data and redundancy information from the functioning storage devices associated with the first GCG; consolidating the extracted valid data from the functioning storage devices and the reconstructed data of the failed storage device associated with the first GCG; writing the consolidated extracted valid data from the functioning storage devices and the reconstructed data of the failed storage device associated with the first GCG to a second GCG in the storage array; and reclaiming the first GCG identified for garbage collection.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: August 11, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Vladislav Bolkhovitin, Siva Munnangi
  • Patent number: 10714192
    Abstract: According to one embodiment, a controller is configured to write four-bit data in each of memory cells, and read first data item from the memory cells through application of a first voltage to a word line. The controller is configured to read second data items by repeating a first operation of reading data including data of respective first bits of the memory cells through application of two voltages to the word line at different timings while changing the two voltages in each first operation from the two voltages in another first operation. The controller is configured to mask part of each of the second data items using the first data.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: July 14, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Tsukasa Tokutomi, Masanobu Shirakawa
  • Patent number: 10714191
    Abstract: Methods of operating a memory include determining a voltage level of a plurality of voltage levels at which a memory cell is deemed to first activate in response to applying the to a control gate of that memory cell for each memory cell of a plurality of memory cells, determining a plurality of voltage level distributions from numbers of memory cells of a first subset of memory cells deemed to first activate at each voltage level of the plurality of voltage levels, determining a transition between a pair of voltage level distributions for each adjacent pair of voltage level distributions, and assigning a respective data state to each memory cell of a second subset of memory cells responsive to the determined voltage level at which that memory cell is deemed to first activate and respective voltage levels of the transitions for each adjacent pair of voltage level distributions.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: July 14, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Tommaso Vali, Luca De Santis, Ramin Ghodsi
  • Patent number: 10692558
    Abstract: A memory device includes a memory with a plurality of memory blocks and a first storage circuit to store a first data table and a first refresh value, and a memory controller with a second storage circuit to store a second data table and a second refresh value. When the memory controller meets a refresh request, the memory controller reads the second refresh value and compares the corresponding access address to the corresponding bit in the second data table to determine whether valid data are stored in a specific memory block of the memory. The memory controller sends a valid-data refresh command to the memory when valid data are stored in the specific memory block, but sends an invalid-data refresh command to the memory when invalid data are stored in the specific memory block.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: June 23, 2020
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chih-Yen Lo, Jenn-Shiang Lai
  • Patent number: 10685735
    Abstract: The invention provides a memory management method, a memory storage device, and a memory control circuit unit. The method includes: recording an error bit number of each upper physical programming unit and an error bit number of each lower physical programming unit of each of the physical erasing units; determining whether a first physical erasing unit is a bad physical erasing unit according to distributions of the error bit numbers of the upper physical programming units and the lower physical programming units of the first physical erasing unit of the physical erasing units; and performing a data transfer operation on data in the first physical erasing unit if the first physical erasing unit is determined as the bad physical erasing unit.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: June 16, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Ping-Chuan Lin, Shii-Yeu Chern, Hsiang-Jui Huang, Ping-Yu Hsieh, Zih-Jia Wang, Yun-You Lin
  • Patent number: 10671477
    Abstract: A method for operating a memory device includes: receiving a first read command and a first address; reading a first read data and a first error correction code from memory cells selected based on the first address; detecting and correcting an error of the first read data using the first error correction code; storing the first address as an error detection address in an address latch circuit; storing an error-corrected bit of the first read data and a position of the error-corrected bit of the first read data in a data latch circuit; and transmitting an error-corrected first read data to an external device.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: June 2, 2020
    Assignee: SK hynix Inc.
    Inventor: Youk-Hee Kim
  • Patent number: 10672479
    Abstract: A nonvolatile memory device includes a memory cell array including a plurality of nonvolatile memory cells; a page buffer circuit connected to the memory cell array through a plurality of bit lines; a calculation circuit configured to perform a calculation on information bits and weight bits based on a calculation window having a first size, the information bits and weight bits being included in a user data set, the memory cell array being configured to store the user data set, the calculation circuit being further configured to receive the user data set through the page buffer circuit; and a data input/output (I/O) circuit connected to the calculation circuit, wherein the calculation circuit is further configured to provide an output data set to the data I/O circuit in response to the calculation circuit completing the calculation with respect to all of the information bits and the weight bits, and wherein the output data set corresponds to a result of the completed calculation.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: June 2, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Taek-Soo Kim, Chan-Ik Park, Hyun-Sung Shin, Sang-Hoan Chang
  • Patent number: 10671478
    Abstract: A scrubbing controller of a semiconductor memory device includes a scrubbing address generator and a weak codeword address generator. The scrubbing address generator generates a scrubbing address for all codewords in a first bank array of a plurality of bank arrays in a first scrubbing mode. The scrubbing address is associated with a normal scrubbing operation and changes in response to an internal scrubbing signal and a scrubbing command. The weak codeword address generator generates a weak codeword address for weak codewords in the first bank array in a second scrubbing mode. The weak codeword address is associated with a weak scrubbing operation and is generated in response to the internal scrubbing signal.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: June 2, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Uhn Cha, Ye-Sin Ryu
  • Patent number: 10671527
    Abstract: A method for operating a data storage device including a non-volatile memory device including a first region and a second region includes: storing data from a data cache memory in memory blocks in the first region; determining a first garbage collection cost with respect to a first target memory block having the least valid page among the memory blocks in the first region in which the data are kept; determining a second garbage collection cost with respect to a second target memory block having the least valid page among the memory blocks in the first region from which the data are cleared; and performing a garbage collection operation to copy valid data of a garbage collection target memory block into memory blocks in the second region based on a comparison result of the first garbage collection cost and the second garbage collection cost.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: June 2, 2020
    Assignee: SK hynix Inc.
    Inventors: Yong Tae Kim, Duck Hoi Koo, Soong Sun Shin, Cheon Ok Jeong
  • Patent number: 10656875
    Abstract: A method for re-reading page data is provided. The method for re-reading page data classifies each of the retry tables into one of a plurality of retry types, and when starting the re-reading procedure, the method will firstly select a retry type based on the environmental parameters related to reading the target page, and select a retry table from the selected retry type and re-read the data of the target page according to the read parameters of the retry table, thereby reducing a number of times of repetitively reading the target page and preventing read disturbance caused by frequent reading.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: May 19, 2020
    Assignee: Silicon Motion, Inc.
    Inventor: Ying-Chun Hung