Solid State Memory Patents (Class 714/773)
  • Patent number: 10446252
    Abstract: A data storage device with high security is disclosed. A nonvolatile memory provides a storage space divided into a plurality of first-level cells. The first-level cells are grouped into a plurality of second-level cells with each second-level cell containing several first-level cells. Each of the plurality of first-level cells is provided with checking and correcting code by a control unit. When reading a specified first-level cell, the control unit checks data in the specified first-level cell based on the checking and correcting code of the specified first-level cell and thereby performs a self-test on another space of a specified second-level cell. The specified first-level cell is provided in the specified second-level cell.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: October 15, 2019
    Assignee: SHANNON SYSTEMS LTD.
    Inventor: Xueshi Yang
  • Patent number: 10439647
    Abstract: An operation method of a controller includes: generating a predetermined number of sub-messages by dividing an original message; generating a first parity added message by adding a cyclic redundancy check (CRC) parity message of a predetermined length to each of the sub-messages; and generating an encoded message by performing a polar encoding operation to the first parity added message.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: October 8, 2019
    Assignees: SK hynix Inc., Korea Advanced Institute of Science and Technology
    Inventors: Jaekyun Moon, Beongjun Choi, Sung Whan Yoon
  • Patent number: 10437484
    Abstract: A data protecting method, a memory control circuit unit and a memory storage device are provided. The method includes repeatedly reading data from a first physical programming unit of a first physical erasing unit during an initialization operation after the memory storage device is powered on, wherein the first physical programming unit is the last programmed physical programming unit before the memory storage device is powered off. The method also includes updating a logical-physical mapping table according to the first physical programming unit if a number of error bits of data read each time is not greater than an error bits amount threshold and a reading count of the first physical programming unit is greater than a predetermined count.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: October 8, 2019
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Kai-Hsiang Yang
  • Patent number: 10430278
    Abstract: A redundant array of inexpensive disks (RAID) system including nonvolatile memory and an operating method of the same is provided. A nonvolatile memory device implemented as a RAID and including a plurality of first memory chips, which store data chunks, and a second memory chip, in which spare memory regions are defined. A RAID controller controls RAID operations and a rebuild operation of the nonvolatile memory device. The RAID controller monitors a failure probability of each of the first memory chips, and in response to detecting a failure probability of two or more first memory chips that satisfies a predefined threshold value, a first rebuild on data stored in each of the first memory chips is performed to store the data in the second memory chip. A second rebuild on data stored in the first memory chip having the failure using data stored in the second memory chip.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: October 1, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Ju Pyung Lee
  • Patent number: 10395754
    Abstract: A method is proposed for decoding read bits including information bits from memory cells of a solid state drive. The method comprises determining a reliability indication indicative of a reliability of the read bits, and iterating the following sequence of steps: soft decoding the read bits based on said reliability indication in order to obtain said information bits, determining at least one among a time indication indicative of a time elapsed since a last writing of the memory cells and a temperature indication indicative of a temperature of the memory cells, and applying at least one among said time indication and said temperature indication to said reliability indication. A corresponding solid state drive is also proposed.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: August 27, 2019
    Assignee: NandEXT Srl
    Inventor: Margherita Maffeis
  • Patent number: 10394652
    Abstract: A memory system includes a semiconductor memory device including memory cells and an internal Random Access Memory (RAM); and a controller suitable for transmitting read retry table information to the semiconductor memory device when a read operation for the memory cells fails, wherein the internal RAM stores a read retry table during operation of the memory system, and wherein the semiconductor memory device performs a read retry operation with a read retry voltage determined based on the read retry table and the read retry table information.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: August 27, 2019
    Assignee: SK hynix Inc.
    Inventors: Gil Bok Choi, Suk Kwang Park, Min Sang Park
  • Patent number: 10389380
    Abstract: Efficient data path architecture for flash devices requiring multi-pass programming utilizes an external memory as an intermediate buffer to store the encoded data used for a first pass programming of the flash device. The stored encoded data can be read from the external memory for subsequent passes programming instead of fetching the data from an on-chip memory, which stores the data received from a host system. Thus, the on-chip memory can be made available to speed up the next data transfer from the host system.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: August 20, 2019
    Assignee: SK Hynix Inc.
    Inventors: Wei-Hao Yuan, Johnson Yen, ChunHok Ho
  • Patent number: 10372533
    Abstract: A non-volatile memory (NVM) apparatus and an empty page detection method thereof are provided. The NVM apparatus includes a NVM and a controller. The controller reads the content of a memory page of the NVM. The controller performs Low Density Parity Check (LDPC) decoding for at least one codeword of the memory page to obtain a decoded codeword and a check-result vector. The controller determines that the memory page is not an empty page when the LDPC decoding for the codeword is successful. The controller counts an amount of the bits being 1 (or 0) in the check-result vector when the LDPC decoding for the codeword is fail. Based on the amount of the bits being 1 (or 0) in the check-result vector, the controller determines whether the memory page is an empty page.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: August 6, 2019
    Assignee: VIA Technologies, Inc.
    Inventors: Ying Yu Tai, Jiangli Zhu
  • Patent number: 10353776
    Abstract: A memory system includes a semiconductor memory device including memory cells and an internal Random Access Memory (RAM); and a controller suitable for transmitting read retry table information to the semiconductor memory device when a read operation for the memory cells fails, wherein the internal RAM stores a read retry table during operation of the memory system, and wherein the semiconductor memory device performs a read retry operation with a read retry voltage determined based on the read retry table and the read retry table information.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: July 16, 2019
    Assignee: SK hynix Inc.
    Inventors: Gil Bok Choi, Suk Kwang Park, Min Sang Park
  • Patent number: 10348332
    Abstract: A method for accessing a flash memory module is provided. The flash memory module is a 3D flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, each block includes a plurality of pages, and the method includes: configuring the flash memory chips to set at least a first super block and at least a second super block of the flash memory chips; and allocating the second super block to store a plurality of temporary parities generated when data is written into the first super block.
    Type: Grant
    Filed: September 16, 2018
    Date of Patent: July 9, 2019
    Assignee: Silicon Motion Inc.
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu
  • Patent number: 10338835
    Abstract: According to one embodiment, a memory device includes a memory cell; a first circuit that performs a first read on the memory cell, writes first data in the memory cell on which the first read has been performed, performs a second read on the memory cell in which the first data has been written, determines data from a result of the first read based on a result of the second read, and writes back the determined data into the memory cell; and an error correcting circuit that performs error correction on the determined data.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: July 2, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yoshiaki Osada, Katsuhiko Hoya, Yorinobu Fujino, Kosuke Hatsuda
  • Patent number: 10296260
    Abstract: A method and system for write amplification analysis are provided. In one embodiment, a method is provided that is performed in a computing device. The method comprises determining an amount of data written from the computing device to a storage system over a time period, wherein the storage system comprises a memory; determining an amount of data written to the memory by the storage system over the time period; calculating a write amplification factor over the time period; and simultaneously displaying graphs of the amount of data written from the computing device over the time period, the amount of data written to the memory over the time period, and the write amplification factor over the time period. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: May 21, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Yacov Duzly, Eyal Sobol, Tal Shaked, Liat Hod, Omer Gilad, Zevulun Einat Inna
  • Patent number: 10282251
    Abstract: A system and method is disclosed for managing firmware in a non-volatile memory system having a multi-processor controller. The controller may be configured with a plurality of processors. Each of the plurality of processors may retrieve and check the integrity of firmware for a respective one of the other processors while the processor engaged in checking the respective one of the other processors is in an idle state.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: May 7, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Ilya Gusev, Yevgeny Zagalsky, Beniamin Kantor, Shay Benisty, Judah Gamliel Hahn
  • Patent number: 10269436
    Abstract: According to one embodiment, there is provided a non-volatile semiconductor storage device including a non-volatile memory, a monitoring section, a determining section, and a notification processing section. The non-volatile memory includes a plurality of memory cells driven by word lines and a voltage generating section that generates a read voltage to be applied to the word lines. The monitoring section monitors a change in a threshold distribution of the plurality of memory cells upon performing a read processing to read data from the plurality of memory cells by applying the read voltage to the word lines. The determining section determines a degree of deterioration of the non-volatile memory in accordance with a monitoring result by the monitoring section. The notification processing section notifies a life of the non-volatile memory in accordance with a determining result by the determining section.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: April 23, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Naoki Matsunaga
  • Patent number: 10268540
    Abstract: A data storage device includes at least one nonvolatile memory device; and a controller suitable for: generating parity data for data; performing a write operation for storing the data in at least one first memory region corresponding to at least one word line of the nonvolatile memory device; and selectively storing the parity data in at least one second memory region corresponding to the word line according to a size of the data, wherein the controller generates a plurality of parity data for the data according to respective types of the first memory region where the data are to be stored, and performs the write operation by storing parity data corresponding to respective types of the second memory region among the plurality of parity data, in the second memory region.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: April 23, 2019
    Assignee: SK hynix Inc.
    Inventor: Ji Seon Yang
  • Patent number: 10261857
    Abstract: A memory system includes a memory that includes a plurality of memory cells, and a controller. During a write operation to write data to the memory cells, the controller encodes first data to be written at a first code rate. During a read operation to read data from the memory cells, the controller decodes second data read from the memory cells at the first code rate. The controller changes the first code rate to a second code rate that is less than the first code rate upon determining that the number of error bits during the read operation of the second data is above a threshold number for error bits or upon determining that the number of memory cells having a threshold voltage that is in a voltage range that includes a read voltage is above a threshold number for memory cells.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: April 16, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Katsuhiko Ueki, Sumio Kuroda, Yasuyuki Ozawa
  • Patent number: 10248559
    Abstract: The present disclosure provides a weighting-type data relocation control device for controlling data relocation of a non-volatile memory which includes used blocks and unused blocks. Each used block is associated with a first parameter and a second parameter. The control device executes the following steps: multiplying the first and second parameters by a first and a second weightings respectively to obtain a priority index, in which at least one of the parameters and/or at least one of the weightings relate(s) to a thermal detection result; comparing the priority index with at least a threshold to obtain a comparison result; and if the comparison result corresponding to a used storage block of the used blocks reaches a predetermined threshold, transferring valid data of the used storage block to one of the unused blocks.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: April 2, 2019
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Yen-Chung Chen, Chih-Ching Chien, Fu-Hsin Chen
  • Patent number: 10223231
    Abstract: Exemplary systems, apparatus, and methods may write data to data blocks defining health levels corresponding to the quality-of-service levels of the data. Further, when health levels of the data blocks change over time, the data may be moved in an attempt to maintain the data in data blocks defining health levels that correspond to the quality-of-service levels of the data.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: March 5, 2019
    Assignee: Seagate Technology LLC
    Inventors: Sumanranjan Mitra, Kantanu Kumar Mohapatra, Nilesh Kumar Singh
  • Patent number: 10210041
    Abstract: Techniques and systems are provided for copying, with or without error-fixing or corrections, data associated with a first set of locations to a second set of locations in a flash memory. Example methods disclosed, when performed by a flash memory controller, can significantly improve latency of operations. Embodiments of the disclosure can be used, for example, in a garbage collection process of a NAND flash memory.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: February 19, 2019
    Assignee: SK Hynix Inc.
    Inventors: Fan Zhang, Yu Cai, June Lee
  • Patent number: 10209914
    Abstract: A system and method for managing data writes in a non-volatile memory including SLC and MLC blocks of non-volatile memory and a MLC block health rating data structure tracking relative MLC block health. A controller in the system may be configured to select MLC blocks for receiving host data and then route the host data over a direct MLC write path for healthy blocks, or over a two-step indirect write path that includes a SLC write and a SLC-MLC fold for unhealthy MLC blocks. The method may include assigning a health designation based on BER determined for each MLC block and assigning a direct write number to healthy MLC blocks based on the determined BER that limits the number of program/erase cycles for direct writes for a particular MLC block until a re-assessment of block health is needed.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: February 19, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Dinesh Agarwal, Hitesh Golechchha, Guruswamy Ganesh
  • Patent number: 10210943
    Abstract: A memory system or flash card may include a mechanism for memory cell measurement and analysis that independently measures/predicts memory wear/endurance, data retention (DR), read disturb, and/or remaining margin. These effects may be independently quantified by analyzing the state distributions of the individual voltage levels of the cells. In particular, a histogram of cell voltage distributions of the memory cells can be analyzed to identify signatures for certain effects (e.g. wear, DR, read disturb, margin, etc.). Those measurements may be used for block cycling, data loss prediction, or adjustments to memory parameters. Pre-emptive action at the appropriate time based on the measurements may lead to improved memory management and data management. That action may include calculating the remaining useful life of data stored in memory, cycling blocks, predicting data loss, trade-off or dynamic adjustments of memory parameters.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: February 19, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Neil Richard Darragh, Sergey Anatolievich Gorobets, Liam Michael Parker
  • Patent number: 10205469
    Abstract: Techniques for reducing the latency for decoding product codewords with minimal hardware architecture changes are described. In an example, a system accesses and decodes a generalized product code (GPC) codeword by using at least one of a plurality of Chase decoding procedures available on the system. A first Chase decoding procedure is configured according to first values for a set of decoding parameters. A second Chase decoding procedure is configured according to second values for the set of decoding parameters. The second values are different from the first values. The first Chase decoding procedure has a smaller latency and a higher bit error rate (BER) relative to the second Chase decoding procedure based on the first values and the second values for the set of decoding parameters.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: February 12, 2019
    Assignee: SK Hynix Inc.
    Inventors: Naveen Kumar, Aman Bhatia, Yi-Min Lin, Fan Zhang
  • Patent number: 10198180
    Abstract: A storage management method and a storage management apparatus are provided. In some embodiments, the method includes: detecting, during a preset length of time, a writing amount per time unit of service data of a target network service in a target storage; retrieving a correspondence relationship between the writing amount per time unit and an amount of a redundant storage, wherein the relationship indicates the amount of the redundant storage increases with the increasing of the writing amount per time unit; determining a first amount of the redundant storage corresponding to the first writing amount per time unit according to the correspondence relationship; and configuring the redundant storage for the target network service in accordance with the first amount of the redundant storage.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: February 5, 2019
    Assignee: Tencent Technology (Shenzhen) Company Limited
    Inventor: Hao Xu
  • Patent number: 10180794
    Abstract: The subject technology provides reduced overhead in Low Density Parity Check decoding operations. A method includes receiving a hard decode fail indication from a decoder that decoding first raw data read from non-volatile memory in response to a first read command using a first set of voltages failed. The method includes determining a count of available soft decoders of a plurality of soft decoders of the decoder. The method includes determining, based on the count of available soft decoders and a pending number of soft decoding requests, a number of soft decoding requests to issue. The method includes issuing the determined number of soft decoding requests to respective ones of the available soft decoders for soft decoding the first raw data in parallel. The method includes receiving from the decoder a success indication of successful decoding.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: January 15, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Niang-Chu Chen, Jun Tao
  • Patent number: 10162700
    Abstract: A method, according to one embodiment, includes selecting, from a buffer, a combination of compressed logical pages of data to maximize an amount of used space in an error correction code container. The method also preferably includes processing the combination of compressed logical pages to generate error correction code data. Furthermore, the method may include writing the data corresponding to the combination of compressed logical pages and the associated error correction code data to a non-volatile random access memory. Other systems, methods, and computer program products are described in additional embodiments.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: December 25, 2018
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Camp, Thomas Mittelholzer, Nikolaos Papandreou, Thomas Parnell, Charalampos Pozidis
  • Patent number: 10127106
    Abstract: A redundant disk array system and a data storage method thereof are provided. The redundant disk array system includes a plurality of disks, a plurality of data stripes, and a processing unit. The processing unit stores, in a log manner into a write page, first logic page numbers corresponding to the pieces of write data, and records write locations of the first logic page numbers; the processing unit performs garbage collection on invalid page numbers of the first logic page numbers; and after executing garbage collection, the processing unit writes, in a log manner, second logic page numbers corresponding to the pieces of write data into the write pages traversed by a data stripe of the data stripes that has the most invalid page numbers, and records write locations of the second logic page numbers.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: November 13, 2018
    Assignee: ACCELSTOR LTD.
    Inventors: Shih-Chiang Tsao, Ting-Fang Chien, An-Nan Chang
  • Patent number: 10120818
    Abstract: Aspects include sending a request to perform a unit of work that includes a synchronous I/O operation. The sending is from an operating system (OS) executing on a server to firmware located on the server. The synchronous I/O request includes a command request block that includes an operation code identifying the synchronous I/O operation and a identifier of a persistent storage control unit (SCU). The OS waits for the synchronous I/O to complete and the unit of work remains active during the waiting. The firmware detects that the synchronous I/O operation has completed. A command response block that includes completion status information about the synchronous I/O operation is received by the OS from the firmware. The unit of work is completed in response to the I/O operation completing.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: November 6, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David F. Craddock, Beth A. Glendening, Dale F. Riedy, Harry M. Yudenfriend
  • Patent number: 10120589
    Abstract: An operating method of a nonvolatile memory system includes receiving a read request for at least one page from a host. Upon receiving the read request, read voltages are adjusted using a read history table to perform a first read operation in which data stored at the nonvolatile memory is read. An optimal read voltage set is detected when data read according to the first read operation includes an uncorrectable error, and a second read operation is performed in which the stored data is read based on the detected optimal read voltage set. The read history table is updated based on a reliability parameter indicating a characteristic of the nonvolatile memory, a characteristic of the data at the first or second read operation, the optimal read voltage, or the read history table.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: November 6, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Bong-Kil Jung
  • Patent number: 10109361
    Abstract: A memory programmer apparatus may include a first-level programmer to program a first-level cell portion of a multi-level memory in a first pass, a coarse programmer to coarse program a second-level cell portion of the multi-level memory in the first pass, wherein the second-level cell portion includes more levels than the first-level cell portion, and a fine programmer to fine program the second-level cell portion of the multi-level memory in a second pass from data programmed in the first-level cell portion in the first pass.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: October 23, 2018
    Assignee: Intel Corporation
    Inventors: Ali Khakifirooz, Pranav Kalavade, Rohit S. Shenoy, Aliasgar S. Madraswala, Donia Sebastian, Xin Guo
  • Patent number: 10108358
    Abstract: Aspects include sending a request to perform a unit of work that includes a synchronous I/O operation. The sending is from an operating system (OS) executing on a server to firmware located on the server. The synchronous I/O request includes a command request block that includes an operation code identifying the synchronous I/O operation and a identifier of a persistent storage control unit (SCU). The OS waits for the synchronous I/O to complete and the unit of work remains active during the waiting. The firmware detects that the synchronous I/O operation has completed. A command response block that includes completion status information about the synchronous I/O operation is received by the OS from the firmware. The unit of work is completed in response to the I/O operation completing.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: October 23, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David F. Craddock, Beth A. Glendening, Dale F. Riedy, Harry M. Yudenfriend
  • Patent number: 10090858
    Abstract: A storage device includes a nonvolatile memory device and a controller configured to read data from the nonvolatile memory device, to divide the read data into a plurality of segments, and to sequentially perform error correction decoding with respect to the plurality of segments. When the error correction decoding of each segment is completed, the controller adds error correction parity to each of the decoded segments and sends the decoded segments with added error correction parity to an external host device. When error correction decoding of a second segment is not completed after a threshold time has elapsed after sending a first segment of which error correction decoding is completed, the controller adds an incorrect error correction parity to dummy data and sends the dummy data with the added incorrect error correction parity to the external host device.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: October 2, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yongwon Cho, Hynsoo Bae, Hyotaek Leem, Dong-Ryoul Lee, Hyun Ju Yi, Taehack Lee
  • Patent number: 10055168
    Abstract: Memory systems may include a memory storage, and a controller suitable for measuring a write amplification (WA) value of a first, current window, comparing the WA value for the first window with a previous WA value for a previous window, and calculating and setting a value of a ratio threshold based on the comparison of the WA value for the current window threshold to the WA value of the previous window threshold.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: August 21, 2018
    Assignee: SK Hynix Inc.
    Inventors: Frederick K. H. Lee, Xiangyu Tang, Lingqi Zeng
  • Patent number: 10042789
    Abstract: The present disclosure is related to programming interruption management. An apparatus can be configured to detect an interruption during a programming operation and modify the programming operation to program a portion of the memory array to an uncorrectable state in response to detecting the interruption.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: August 7, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Preston A. Thomson, Kishore K. Muchherla, Sampath K. Ratnam
  • Patent number: 10031845
    Abstract: Provided are an apparatus and method for processing sequential writes to a block group of physical blocks in a memory device. Sequential write data for a plurality of consecutive logical addresses is received and a determination is made of consecutive physical blocks comprising a block group. Each of the physical blocks has data for a plurality of the consecutive logical addresses. The sequential write data is written to consecutive physical data locations having data for the determined consecutive physical blocks of the block group. The block group metadata for the block group is updated.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: July 24, 2018
    Assignee: INTEL CORPORATION
    Inventor: Frank T. Hady
  • Patent number: 10019314
    Abstract: A method used for a flash memory module having a plurality of storage blocks each can be used as a first block or a second block includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate a first corresponding parity check code to store the groups of data and the first corresponding parity check code into the flash memory module as first blocks; reading out the groups of data from the first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon the de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon the randomized data to generate a second corresponding parity check code; and storing the randomized data and the second corresponding parity check code into the flash memory module as the second block.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: July 10, 2018
    Assignee: Silicon Motion Inc.
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu, Jian-Dong Du
  • Patent number: 9996415
    Abstract: A data correcting method for a rewritable non-volatile memory module is provided. The method includes: if a first user data read from a first physical programming unit cannot be corrected by a corresponding first parity code, reading at least one group parity code of a first encoded group that the first physical programming unit belongs to into a buffer, sending the group parity code to a correcting circuit, and reading a user data from physical programming units belonging to the first encoded group into the buffer and sending the user data and the group parity code to the correcting circuit in batches to obtain a corrected first user data corresponding to the first user data.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: June 12, 2018
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Ming-Jen Liang, Kheng-Chong Tan
  • Patent number: 9984768
    Abstract: Apparatuses, systems, methods, and computer program products are disclosed for distributing error-correction codes. A correction module is configured to determine an error correction code (ECC) code word for storage on one or more non-volatile storage media. A mapping module is configured to determine one or more addresses for the ECC code word so that a portion of the ECC code word is stored at a first physical address within a first set of strings of storage cells of the one or more non-volatile storage media and a portion of the ECC code word is stored at a different physical address within a second set of strings of storage cells of the one or more non-volatile storage media. A storage module is configured to cause the ECC code word to be stored in the one or more non-volatile storage media based on the determined one or more addresses.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: May 29, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Jea Hyun, James Peterson, John Strasser
  • Patent number: 9965354
    Abstract: A method includes converting, by a first computing device of a DSN, a user virtual memory address of a data object identified in a data access request into a DSN virtual memory address. The method further includes processing, by at least one of the first computing device and a second computing device of the DSN, the DSN virtual address to determine that a first storage units of the storage units stores first encoded data slices of each set of at least some of the plurality of sets of encoded data slices; and a second storage units of the storage units stores second encoded data slices of each set of the at least some of the plurality of sets of encoded data slices. The method further includes converting, by the first storage unit, DSN virtual addresses of the first encoded data slices into physical addresses within the first storage unit.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: May 8, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Jason K. Resch
  • Patent number: 9946594
    Abstract: A flash memory codeword architecture is provided. A non-integer count of logical pages is packed into a codeword payload data container. A codeword payload header is generated. The codeword payload header includes an offset to a first logical page that is packed, at least in part, into the codeword payload data container. The codeword payload data container and the codeword payload header are concatenated to generate a codeword payload. Error-correcting code data is generated based, at least in part, on the codeword payload using a systematic error-correcting code. The codeword payload and error-correcting code data is concatenated to generate a codeword. A physical page is programmed with the codeword.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: April 17, 2018
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Lincoln T. Simmons, Adalberto G. Yanes
  • Patent number: 9940034
    Abstract: A mechanism is provided in a non-volatile memory controller for reducing read access latency by straddling pages across non-volatile memory channels. Responsive to a request to write a logical page to a non-volatile memory array, the non-volatile memory controller determines whether the logical page fits into a current physical page. Responsive to determining the logical page does not fit into the current physical page, the non-volatile memory controller writes a first portion of the logical page to a first physical page in a first block and writes a second portion of the logical page to a second physical page in a second block. The first physical page and the second physical page are on different non-volatile memory channels.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: April 10, 2018
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Nikolas Ioannou, Thomas Parnell, Roman Pletka, Sasa Tomic
  • Patent number: 9928063
    Abstract: Instructions and logic provide vector horizontal majority voting functionality. Some embodiments, responsive to an instruction specifying: a destination operand, a size of the vector elements, a source operand, and a mask corresponding to a portion of the vector element data fields in the source operand; read a number of values from data fields of the specified size in the source operand, corresponding to the mask specified by the instruction and store a result value to that number of corresponding data fields in the destination operand, the result value computed from the majority of values read from the number of data fields of the source operand.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: March 27, 2018
    Assignee: Intel Corporation
    Inventors: Elmoustapha Ould-Ahmed-Vall, Kshitij A. Doshi, Suleyman Sair, Charles R. Yount
  • Patent number: 9928154
    Abstract: A method and computer program product for causing a processor to perform the method are provided. The method includes monitoring a plurality of operating parameters for each of multiple components of a compute node, wherein the multiple components have the same component type, and determining a stress factor score for each of the multiple components, wherein the stress factor score is a function of the plurality of operating parameters. The method further includes reducing use of a first component from among the multiple components, wherein the first component has a stress factor score that is greater than the stress factor score for any of the other components of the same component type. Optionally, the method may prioritize use of each of the multiple components in an order of ascending stress factor score.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: March 27, 2018
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Paul D. Kangas, Daniel M. Ranck
  • Patent number: 9916906
    Abstract: Log likelihood ration (LLR) values that are computed in a flash memory controller during read retries change over time as the number of program-and-erase cycles (PECs) that the flash memory die has been subjected to increases. Therefore, in cases where an LLR table is used to provide pre-defined, fixed LLR values to the error-correcting code (ECC) decoding logic of the controller, decoding success and the resulting BER will degrade over time as the number of PECs to which the die has been subjected increases. In accordance with embodiments, a storage system, a flash memory controller for use in the storage system and method are provided that periodically measure the LLR values and update the LLR table with new LLR values. Periodically measuring the LLR values and updating the LLR table with new LLR values ensures high decoding success and a low BER over the life of the flash memory die.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: March 13, 2018
    Assignee: Seagate Technology LLC
    Inventors: Yunxiang Wu, Yu Cai, Zhengang Chen, Erich Haratsch
  • Patent number: 9904593
    Abstract: A device includes a reference circuit, a readout circuit, and an error correction coding circuit. The reference circuit is configured to generate a reference signal. The readout circuit is configured to generate data values of second data according to the reference signal and first data. The error correction coding circuit is configured to reset the reference circuit when errors occur in all of the data values of the second data.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: February 27, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Fu Lee, Yu-Der Chih
  • Patent number: 9898215
    Abstract: In at least one embodiment, a non-volatile memory array including a plurality of blocks each including a plurality of physical pages is controlled by a controller. The controller implements a plurality of nested page retirement classes each defined by a respective one of a plurality of different nested subsets of page indices of physical pages within the plurality of blocks that are to be considered retired from use. For each block among the plurality of blocks, the controller updating an indication of a page retirement class to which the block belongs in response to detection of a retirement-causing error in a data page stored in a physical page of the block. The controller forms block stripes for storing data from the plurality of blocks based on the page retirement classes of the blocks.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: February 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Camp, Timothy J. Fisher, Nikolas Ioannou, Thomas Parnell, Roman A. Pletka, Sasa Tomic
  • Patent number: 9900027
    Abstract: A method, non-transitory computer readable medium and circuit for detecting and correcting errors in a communication channel are disclosed. The circuit includes error monitoring logic for monitoring the communication channel in real time for a performance metric, a fixed-operating point encoder/decoder coupled to the error monitoring logic for generating a bit stream containing redundant data used for the detecting and correcting, a reconfigurable controller coupled to the fixed-operating point encoder/decoder, wherein a configuration of the reconfigurable controller determines an amount of the redundant data contained in the bit stream, and a data structure implemented in a logic fabric of the circuit and coupled to the error monitoring logic, for generating the configuration of the reconfigurable controller responsive to a value of the performance metric controller.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: February 20, 2018
    Assignee: XILINX, INC.
    Inventor: Benjamin S. Devlin
  • Patent number: 9881682
    Abstract: Embodiments described herein provide for linking retention parameters that affect data retention in flash to data stored in the flash. One embodiment includes a flash memory and a controller. The controller receives a plurality of write requests from a host, and stores data for the write request in flash pages of the flash memory along with indicators. The controller identifies at least one retention parameter that affects data retention of the stored data, and adds one or more of the indicators to an entry in a journal along with the at least one retention parameter. In response to determining that a data refresh is warranted based on the at least one retention parameter, the controller identifies the one or more indicators associated with the at least one retention parameter in the entry, locates the stored data corresponding to the one or more indicators, and refreshes the stored data.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: January 30, 2018
    Assignee: Seagate Technology LLC
    Inventors: Alex Tang, Timothy Canepa, Ramdas Kachare
  • Patent number: 9875153
    Abstract: A flash memory codeword architecture is provided. A non-integer count of logical pages is packed into a codeword payload data container. A codeword payload header is generated. The codeword payload header includes an offset to a first logical page that is packed, at least in part, into the codeword payload data container. The codeword payload data container and the codeword payload header are concatenated to generate a codeword payload. Error-correcting code data is generated based, at least in part, on the codeword payload using a systematic error-correcting code. The codeword payload and error-correcting code data is concatenated to generate a codeword. A physical page is programmed with the codeword.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: January 23, 2018
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Lincoln T. Simmons, Adalberto G. Yanes
  • Patent number: 9824778
    Abstract: A nonvolatile memory system includes a nonvolatile memory device including a distribution table suitable for storing recovery read level intervals that are set by being changed through multiple stages according to a distribution value of threshold voltage levels of a plurality of memory cells, measured at a reference read level, is changed through the multiple stages; and a memory controller suitable for reading measurement data from the memory cells by additionally using a measurement read level, searching for a difference value between the normal data and the measurement data from the multiple stages of distribution values stored in the distribution table, and recovering the normal data based on a recovery read level interval corresponding to a searched distribution value, when an error occurs in normal data read from the memory cells by using the reference read level.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: November 21, 2017
    Assignee: SK Hynix Inc.
    Inventor: Hyung-Min Lee
  • Patent number: 9811419
    Abstract: A flash memory codeword architecture is provided. A non-integer count of logical pages is packed into a codeword payload data container. A codeword payload header is generated. The codeword payload header includes an offset to a first logical page that is packed, at least in part, into the codeword payload data container. The codeword payload data container and the codeword payload header are concatenated to generate a codeword payload. Error-correcting code data is generated based, at least in part, on the codeword payload using a systematic error-correcting code. The codeword payload and error-correcting code data is concatenated to generate a codeword. A physical page is programmed with the codeword.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: November 7, 2017
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Lincoln T. Simmons, Adalberto G. Yanes