Abstract: A system includes a memory component, and a processing device coupled with the memory component. The processing device to identify a group of management units of the memory component, wherein the group of management units is included in a set of retired groups of management units, select a management unit from the group of management units, perform a media integrity check on the management unit to determine a failed bit count of the management unit, and in response to the failed bit count of the management unit failing to satisfy a threshold criterion, remove the group of management units from the set of retired groups of management units.

Abstract: A method, apparatus, non-transitory computer readable medium, and system for selecting program voltages for a memory device are described. Embodiments of the method, apparatus, non-transitory computer readable medium, and system may map a set of information bits to voltage levels of one or more memory cells based on a plurality of embedding parameters, program the set of information bits into the one or more memory cells based on the mapping, detect the voltage levels of the one or more memory cells to generate one or more detected voltage levels, and identify a set of predicted information bits based on the one or more detected voltage levels using a neural network comprising a plurality of network parameters, wherein the network parameters are trained together with the embedding parameters.

Abstract: A data storage device, and an error tolerance selecting method thereof which includes: writing data to data blocks of the data storage device; reading written data of the data blocks as read data; comparing the read data and the written data of each data column in the data blocks, and calculating a number of error bits in each chunk including a plurality of data columns accordingly; calculating a difference value between the number of error bits in the chunk and a first threshold value to store the difference value in an error tolerance list; and selecting a largest difference value in the error tolerance list as an error tolerance.

Abstract: A three-dimensional (3D) storage device using wafer-to-wafer bonding is disclosed. In the storage device, a first chip including a peripheral circuit region including a first control logic circuit configured to control operation modes of a nonvolatile memory (NVM) device is wafer-bonded with a second chip including 3D arrays of NVM cells, and a memory controller includes a third chip including a control circuit region. The control circuit region of the third chip includes a second control logic circuit associated with operation conditions of the NVM device, and the second control logic circuit includes a serializer/deserializer (SERDES) interface configured to share random access memory (RAM) in the memory controller and transmit and receive data to and from the NVM device.

Abstract: A method for page writes for triple or higher level cell flash memory is provided. The method includes receiving data in a storage system, from a client that is agnostic of page write requirements for triple or higher level cell flash memory, wherein the page write requirements specify an amount of data and a sequence of writing data for a set of pages to assure read data coherency for the set of pages. The method includes accumulating the received data, in random-access memory (RAM) in the storage system to satisfy the page write requirements for the triple or higher level cell flash memory in the storage system. The method includes writing at least a portion of the accumulated data in accordance with the page write requirements, from the RAM to the triple level cell, or the higher level cell, flash memory in the storage system as an atomic write.

Abstract: A method performed by a controller of a solid state drive (SSD) comprising receiving from a host a write request to store write data in a nonvolatile semiconductor storage device of the SSD. The method also comprises identifying a first codeword and a second codeword stored in the nonvolatile storage device, the first codeword and the second codeword configured to store write data corresponding to the write request. Responsive to the write request, the method comprises writing a first portion of the write data to the first codeword and writing a second portion of the write data to the second codeword, and sending a message to the host once the write data has been written to the nonvolatile semiconductor storage device. The first and second codewords are adjacently stored, and the write data has a length that is greater than the length of the first and second codewords.

Abstract: Error detection and correction (EDAC) logic of a memory subsystem may be monitored for error corrections, with the EDAC logic configured to use a first EDAC level. The number of error corrections made by the EDAC logic while using the first EDAC level during a time interval may be determined. The EDAC logic may be switched from using the first EDAC level to using a second EDAC level when the number of error corrections using the first EDAC level during the time interval exceeds a threshold.

Abstract: A signal associated with performance of a memory operation can be applied to a memory cell of a first group of memory cells that have undergone PECs within a first range. The signal can have a first magnitude corresponding to a second range of PECs. Whether differences between a first target voltage and the signal and between a second target voltage and the applied signal are at least the threshold value can be determined. Responsive to determining that the differences are at least the threshold value, the first group of memory cells can be associated with a first calibration cluster and the signal having a second magnitude corresponding to a third range of PECs can be applied to a memory cell of a second group of memory cells that have undergone respective quantities of PECs within the second range.

Abstract: A data storage device and method for legitimized data transfer are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to receive a request from a host for a frame of media data; read the frame of media data from the memory, wherein the frame of media data comprises a plurality of fragments; determine whether a fragment of the plurality of fragments contains an error that would prevent playback of other fragments of the plurality of fragments, even if the other fragments do not contain an error; and in response to determining that the fragment contains the error, refrain from sending the other fragments to the host. Other embodiments are provided.

Abstract: A data processing system includes a memory configured to receive memory access requests. Each memory access request having a corresponding access address and having a corresponding parity bit for an address value of the corresponding access address. The corresponding access address is received over a plurality of address lines and the parity bit is received over a parity line. The memory includes a memory array having a plurality of memory cells arranged in rows, each row having a corresponding word line of a plurality of word lines, and a row decoder coupled to the plurality of address lines, the parity line, and the plurality of word lines. The row decoder is configured to selectively activate a selected word line of the plurality of word lines based on the corresponding access address and the corresponding parity bit of a received memory access request.

Abstract: An improved buffer for networking and other computing devices comprises multiple memory instances, each having a distinct set of entries. Transport data units (“TDUs”) are divided into storage data units (“SDUs”), and each SDU is stored within a separate entry of a separate memory instance in a logical bank. One or more grids of the memory instances are organized into overlapping logical banks. The logical banks are arranged into views. Different destinations or other entities are assigned different views of the buffer. A memory instance may be shared between logical banks in different views. When overlapping logical banks are accessed concurrently, data in a memory instance that they share may be recovered using a parity SDU in another memory instance. The shared buffering enables more efficient buffer usage in a network device with a traffic manager shared amongst egress bocks. Example read and write algorithms for such buffers are disclosed.

Abstract: A data processor includes provides memory commands to a memory channel according to predetermined criteria. The data processor includes a first error code generation circuit, a second error code generation circuit, and a queue. The first error code generation circuit generates a first type of error code in response to data of a write request. The second error code generation circuit generates a second type of error code for the write request, the second type of error code different from the first type of error code. The queue is coupled to the first error code generation circuit and to the second error code generation circuit, for provides write commands to an interface, the write commands including the data, the first type of error code, and the second type of error code.

Abstract: A memory performance optimization method, a memory control circuit unit, and a memory storage device are provided. The method includes the following. An idle time of the memory storage device is counted in an active mode. The memory storage device is instructed to enter a first low electricity consumption mode from the active mode in response to the idle time being greater than an idle threshold. A first waiting time of the memory storage device is counted in the first low electricity consumption mode. The memory storage device is instructed to enter a second low electricity consumption mode from the first low electricity consumption mode in response to the first waiting time being greater than a first waiting threshold. Electricity consumption of the second low electricity consumption mode is lower than electricity consumption of the first low electricity consumption mode.

Abstract: In an approach to improve resolving defects within computer hardware, programs, software, or systems, embodiments pause mainline traffic and isolating interface or retention issues, and determine one or more types of errors in an event of a mainline traffic fail, wherein debug techniques are applied to fail information to resolve or further diagnose the one or more types of errors, and wherein the debug techniques are tracked and categorized. Additionally, embodiments apply corrective read actions to a detected error based on previously stored corrective actions associated with the detected error, and responsive to identifying no additional actions are required, restoring a collected system data. Further, embodiments, resume the paused mainline traffic.

Abstract: Methods, systems, and devices for techniques for managing temporarily retired blocks of a memory system are described. In some examples, aspects of a memory system or memory device may be configured to determine an error for a block of memory cells. For example, a controller may determine an existence of the error and may temporarily retire the block. A media management operation may be performed on the temporarily retired block and, depending on one or more characteristics of the error, the temporarily retired block may be enabled or retired.

Abstract: An encoder of a storage medium receives, at a plurality of latches respectively associated with a plurality of memory cells, soft data corresponding to data subject to a read operation specified by the a storage controller, compresses the soft data, and stores the compressed soft data in a buffer before transmitting the compressed soft data to the storage controller. Upon the buffer being full, the encoder writes uncompressed soft data back to at least a subset of the plurality of latches, and upon completion of the writing of the uncompressed soft data, the encoder resumes compressing and storing of soft data in the buffer, and transmits the compressed soft data to the storage controller.

Abstract: A method for managing a host memory buffer, a memory storage apparatus, and a memory control circuit unit are provided. The method includes: detecting whether a system abnormality occurs; copying a first command and first data corresponding to the first command stored in a data buffer of a host system to the memory storage apparatus in response to determining that the system abnormality occurs; executing an initial operation after copying the first command and the first data, wherein the initial operation initializes a part of a hardware circuit in the memory storage apparatus and does not initialize another part of the hardware circuit in the memory storage apparatus; and re-executing the first command stored in the memory storage apparatus after initializing the part of the hardware circuit.

Abstract: Embodiments of the present invention include a memory controller including a buffer memory configured to store program data, an instruction set configurator configured to configure an instruction set describing a procedure for programming the program data stored in the buffer memory to target memory blocks, an instruction set performer configured to sequentially perform instructions in the instruction set and generate an interrupt at a time of completion of performance of a last instruction among the instructions, and a central processing unit configured to erase the program data stored in the buffer memory when the interrupt is received from the instruction set performer. The instruction set configurator may configure the instruction set differently according to whether a non-interleaving block group exists among the target memory blocks.

Abstract: A method of operating a storage system is provided. The storage system includes memory cells and a memory controller, wherein each memory cell is an m-bit multi-level cell (MLC), where m is an integer, and the memory cells are arranged in m pages. The method includes determining initial LLR (log likelihood ratio) values for each of the m pages, comparing bit error rates in the m pages, identifying a programmed state in one of the m pages that has a high bit error rate (BER), and selecting an assist-read threshold voltage of the identified page. The method also includes performing an assist-read operation on the identified page using the assist-read threshold voltage, determining revised LLR values for the identified page based on results from the assist-read operation, and performing soft decoding using the revised LLR values for the identified page and the initial LLR values for other pages.

Abstract: The invention relates to methods, and an apparatus for data reads in a host performance acceleration (HPA) mode. One method is performed by a host side to include: searching an HPA buffer in a system memory for a logical-block-address to physical-block-address (L2P) mapping entry corresponding to a logical block address (LBA); issuing a switch command to a flash controller to request the flash controller to activate an HPA function, and does not activate an acquisition function for an L2P mapping table, where the host side and the flash controller communicate with each other in an embedded multi-media card (eMMC) protocol; issuing a write_multiple_block command to the flash controller to transfer a first data block to the flash controller, which includes the first L2P mapping entry; and issuing a read_multiple_block command to obtain data corresponding to the first L2P mapping entry from the flash controller.

Abstract: The invention relates to methods, and an apparatus for data reads in a host performance acceleration (HPA) mode. One method is performed by a host side to include: issuing a switch command to a flash controller to request the flash controller to activate an HPA function, and an acquisition function for a logical-block-address to physical-block-address (L2P) mapping table; issuing a write_multiple_block command to the flash controller to transfer a data block to a flash controller, where the data block includes a region number and a sub-region number; issuing a read_multiple_block command to the flash controller to obtain a plurality of L2P mapping entries corresponding to the region number and the sub-region number from the flash controller. The host side and the flash controller communicate with each other in an embedded multi-media card (eMMC) protocol.

Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. When a program operation occurs, the controller is configured to determine a decode time for the data prior to programming the data to the memory device. The decode time determined by decoding the encoded data. A number of program loop cycles is determined using the decode time. The data is programmed to the memory device with the number of program loop cycles determined.

Abstract: A method performed by a controller of a solid state drive (SSD) comprising receiving from a host a write request to store write data in a nonvolatile semiconductor storage device of the SSD. The method also comprises identifying a first codeword and a second codeword stored in the nonvolatile storage device, the first codeword and the second codeword configured to store write data corresponding to the write request. Responsive to the write request, the method comprises writing a first portion of the write data to the first codeword and writing a second portion of the write data to the second codeword, and sending a message to the host once the write data has been written to the nonvolatile semiconductor storage device. The first and second codewords are adjacently stored, and the write data has a length that is greater than the length of the first and second codewords.

Abstract: An improved buffer for networking and other computing devices comprises multiple memory instances, each having a distinct set of entries. Transport data units (“TDUs”) are divided into storage data units (“SDUs”), and each SDU is stored within a separate entry of a separate memory instance in a logical bank. One or more grids of the memory instances are organized into overlapping logical banks. The logical banks are arranged into views. Different destinations or other entities are assigned different views of the buffer. A memory instance may be shared between logical banks in different views. When overlapping logical banks are accessed concurrently, data in a memory instance that they share may be recovered using a parity SDU in another memory instance. The shared buffering enables more efficient buffer usage in a network device with a traffic manager shared amongst egress bocks. Example read and write algorithms for such buffers are disclosed.

Abstract: A method that includes writing a plurality of codewords to a plurality of memory blocks of a memory device, where each of the plurality of codewords has a physical codeword index corresponding to a respective memory block in which each codeword is written, and assigning a virtual codeword index to each of the plurality of codewords to provide a plurality of virtual codeword indices, where assigning the virtual codeword index to each of the plurality of codewords is based, at least in part, on a location in a virtual block among a plurality of virtual blocks of memory cells corresponding to the physical codeword index of each codeword among the plurality of codewords.

Abstract: A controller including: control pins for providing control signals to a nonvolatile memory; a buffer memory configured to store first to third tables; and an error correction code (ECC) circuit configured to correct an error in first data read from the nonvolatile memory according to a first read command, wherein the first table stores first offset information, the second table stores second offset information, and the third table stores third offset information, wherein the third offset information corresponds to a history read level and is determined by the first and second offset information, and when the error of the first data is uncorrectable, an on-chip valley search operation is performed by the nonvolatile memory according to a second read command, detection information of the on-chip valley search operation is received according to a specific command, and the second offset information which corresponds to the detection information is generated.

Abstract: Described herein are embodiments related to first-pass continuous read level calibration (cRLC) operations on memory cells of memory systems. A processing device determines that a first programming pass of a programming operation has been performed on a memory cell of a memory component. The processing device performs a cRLC operation on the memory cell to calibrate a read level threshold between a first first-pass programming distribution and a second first-pass programming distribution before a second programming pass of the programming operation is performed on the memory cell.

Abstract: Methods, systems, and devices for techniques for failure management in memory systems are described. A memory system may include one or more non-volatile memory devices. A set of physical blocks of memory cells of the one or more non-volatile memory devices may be grouped into virtual blocks, where each physical block of a virtual may block may be within a different plane of the one or more non-volatile memory devices. The memory system may detect a failure within a physical block of a virtual block and may transfer data from the physical block to one or more other physical blocks within the same virtual block in response to detecting the failure.

Abstract: A command to read specific data stored at a memory die is received. A read operation is performed while operating both a memory controller and the memory die simultaneously at a first frequency. A processor determines whether a first error rate associated with the memory die satisfies a first error threshold criterion (e.g., UECC). Responsive to determining that the first error rate satisfies the first error threshold criterion, the read operation is repeated while operating at least one of the memory controller or the memory die at a second frequency that is different from the first frequency. The processor determines whether a second error rate associated with the memory die satisfies a second error threshold criterion. Responsive to determining that the second error rate satisfies the second error threshold criterion (e.g. UECC persists), determining that the read operation has failed.

Abstract: Systems and methods presented herein provide for testing degradation in a storage device. In one embodiment, a storage controller is operable to test individual portions of a first of the plurality of storage areas of the storage device by: analyzing individual portions of the first storage area; determining that one or more of the individual portions of the first storage area have failed; and retire the failed one or more portions of the first storage area. The storage controller is further operable to write to the first storage area using an error correction code (ECC), and to test the remaining portions of the first storage area to determine whether the first storage area should be retired in response to writing to the first storage area.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory including physical blocks, and a controller. The controller manages namespaces. The namespaces include at least a first namespace for storing a first type of data, and a second namespace for storing a second type of data having a lower update frequency than the first type of data. The controller allocates a first number of physical blocks as a physical resource for the first namespace, and allocates a second number of physical blocks as a physical resource for the second namespace, based on a request from a host device specifying an amount of physical resources to be secured for each of the namespaces.

Abstract: Data redundancy arrangements for memory and storage devices are discussed herein. In one example, a method of operating a data storage system includes identifying a data page for storage in a non-volatile memory die, and generating one or more data redundancy bits for the data page. The method also includes writing the data page to the non-volatile memory die by at least spanning bits of the data page and the one or more data redundancy bits across a quantity of data storage cells that share a structural property in the non-volatile memory die.

Abstract: A storage system has a resiliency scheme to enhance storage system performance. The storage system composes a RAID stripe. The storage system mixes an ordering of portions of the RAID stripe, based on reliability differences across portions of the solid-state memory. The storage system writes the mixed ordering RAID stripe across the solid-state memory.

Abstract: A method of reordering memory bits includes steps of: providing multiple pieces of bit repair data corresponding to memory bits and used to mark whether any one of the memory bits is defective bit; generating selection signals based on multiple pieces of bit repair data; selecting and coupling good memory bits of the memory bits to multiple input/output terminals of a memory, respectively, based on the multiple pieces of bit repair data and the selection signals or based on the selection signals.

Abstract: Systems, apparatus and methods are provided for providing fast non-volatile storage access with ultra-low latency. A method may comprise dividing a user data unit into a plurality of data chunks, generating a plurality of error correction code (ECC) codewords and at least one ECC parity block and transmitting the plurality of ECC codewords and the at least one ECC parity block to a plurality of channels of the non-volatile storage device for each of the plurality of ECC codewords and the at least one ECC parity block to be stored in different channels of the plurality of channels.

Abstract: A controller determines whether or not a read threshold voltage, other than a history read threshold voltage being a read threshold voltage that was used in previously successful read operation, is to be used for a next read operation, based on a fail bit count associated with the read operation, an error correction capability of a decoder and utilization of a queue in the decoder. When it is determined that the history read threshold voltage is not to be used for the next read operation, the controller determines fail bit counts associated with read operations on memory cells of a memory device using read threshold voltages. The controller determines an optimal read threshold voltage based on the fail bit counts. The controller transmits, to the memory device, a first command including a parameter associated with setting the optimal read threshold voltage.

Abstract: A signal associated with performance of a memory operation can be applied to a memory cell of a first group of memory cells that have undergone PECs within a first range. The signal can have a first magnitude corresponding to a second range of PECs. Whether differences between a first target voltage and the signal and between a second target voltage and the applied signal are at least the threshold value can be determined. Responsive to determining that the differences are at least the threshold value, the first group of memory cells can be associated with a first calibration cluster and the signal having a second magnitude corresponding to a third range of PECs can be applied to a memory cell of a second group of memory cells that have undergone respective quantities of PECs within the second range.

Abstract: A storage device includes a first memory device including a plurality of memory blocks, and a plurality of pages included in each of the plurality of memory blocks, a second memory device configured to store first degradation information of the first memory device, and a controller configured to perform a first read operation on the first memory device using a first read voltage, to acquire the first degradation information, and to perform a second read operation on the first memory device using a second read voltage. The second read voltage is calculated using second degradation information of the first memory device estimated using the first degradation information. Each of the first degradation information and the second degradation information includes the number of error bits of each of the plurality of pages.

Abstract: A storage device includes a nonvolatile memory device and a memory controller. The memory controller receives first data from the nonvolatile memory device based on a first read command, and performs error correction on the first data. When the error correction fails, the memory controller transmits a second read command and second read voltage information to the nonvolatile memory device, receives second data from the nonvolatile memory device, transmits a third read command and third read voltage information to the nonvolatile memory device, and receives third data from the nonvolatile memory device. The memory controller adjusts an offset based on the second data and the third data, transmits a fourth read command, fourth read voltage information, and the offset to the nonvolatile memory device, receives fourth data from the nonvolatile memory device, and performs a soft decision process based on the fourth data.

Abstract: A storage device includes a main storage including a plurality of nonvolatile memory devices, the main storage device configured to store data; and a storage controller configured to control the main storage. The storage controller is configured to, divide a plurality of memory blocks of the plurality of nonvolatile memory devices into a plurality of banks, assign each one of the plurality of banks into one of a) a plurality of sets and b) one free bank, each of the plurality of sets including at least one bank, perform data migration operation to transfer the data among the sets by using the one free bank in response to an input/output (I/O) request from an external host device while securing a specific I/O execution time, and control the data migration operation such that the I/O request is independent of the data migration operation.

Abstract: A level count disparity is determined based at least in part on an expected count of a plurality of cells in a solid state storage and an observed count of the plurality of cells in the solid state storage, where the observed count is obtained from a read performed on the solid state storage using a previous read threshold. A next read threshold is determined based at least in part on the level count disparity. A read is performed on the solid state storage using the next read threshold to obtain read data and error correction decoding is performed on the read data.

Abstract: Hard errors are determined for an unsuccessful decoding of codeword bits read from NAND memory cells via a read channel and input to a low-density parity check (LDPC) decoder. A bit error rate (BER) for the hard errors is estimated and BER for the read channel is estimated. Hard error regions are found using a single level cell (SLC) reading of the NAND memory cells. A log likelihood ratio (LLR) mapping of the codeword bits input to the LDPC decoder is changed based on the hard error regions, the hard error BER, and/or the read channel BER.

Abstract: A method for page writes for triple or higher level cell flash memory is provided. The method includes receiving data in a storage system, from a client that is agnostic of page write requirements for triple or higher level cell flash memory, wherein the page write requirements specify an amount of data and a sequence of writing data for a set of pages to assure read data coherency for the set of pages. The method includes accumulating the received data, in random-access memory (RAM) in the storage system to satisfy the page write requirements for the triple or higher level cell flash memory in the storage system. The method includes writing at least a portion of the accumulated data in accordance with the page write requirements, from the RAM to the triple level cell, or the higher level cell, flash memory in the storage system as an atomic write.

Abstract: A memory device that performs internal ECC (error checking and correction) can selectively return read data with application of the internal ECC or without application of the internal ECC, in response to different read commands from the memory controller. The memory device can normally apply ECC and return corrected data in response to a normal read command. In response to a retry command, the memory device can return the read data without application of the internal ECC.

Abstract: A dual in-line memory module (DIMM) includes a memory storage device having data rows and redundant rows. The DIMM further includes a post-package repair module configured to remap an address within the DIMM physical address space from a data row to a redundant row. A memory controller is configured to determine an exact number of un-remapped redundant rows.

Abstract: The signal collection method is a method that collects internal states indicated by signals in an electronic circuit device including a bus, the signal collection method including: storing the internal states with a fine resolution data storage by obtaining the internal states per a first period; per a second period, which is longer than the first period: obtaining a first data transfer amount, which is a data amount transferred by the bus, via a coarse resolution data storage; calculating a difference between a second data transfer amount and the first data transfer amount obtained in the obtaining, the second data transfer amount being calculated in advance and obtained from a cycle pattern generator; and determining whether the difference calculated in the calculating is within a predetermined range to stop storing in the storing when it is determined that the difference is not within the predetermined range.

Abstract: Embodiments of the present disclosure provide an a circuit including: first logic to compare output data from the shift register with output data from error correcting code circuitry (ECC), to output an error signal in response to a data bit output from the shift register being different from a data bit output from the ECC; second logic for receiving the error signal from the first logic gate, and a correctability signal from the ECC, to output an overwrite signal in response to receiving the error signal and the correctability signal; and a selector receiving the overwrite signal and the data bit of the output data from the ECC, and coupled between a data source and an input line to the shift register. The selector causes the shift register to receive the ECC output in response to receiving the overwrite signal.

Abstract: Devices and techniques for a flash memory block retirement policy are disclosed herein. In an example embodiment, a first memory block is provisionally removed from service in response to encountering read errors in the first memory block. Memory pages of the first memory block are tested in a second mode comprising reading memory pages at different read voltages. A raw bit error rate (RBER) or a read window budget (RWB) is determined for memory pages at the different read voltages and the provisionally removed first memory block is returned to service or retired based on the determined RBER or the RWB.

Abstract: The disclosed technology is generally directed towards selecting storage devices, based on predicted reliability, for storing erasure coded data fragments and coding fragments. In general, to increase data availability, data fragments, are stored to more reliable storage devices, while coding fragments are stored to less reliable storage devices. For example, solid state drives (SSDs) tend to fail based on the total number of writes they receive over time, whereby the total number of writes can be used to determine predicted reliability data for an SSD. Before writing the data and coding fragments to a number of storage devices, the storage devices can be sorted based on their predicted reliability such that the data fragments are written to (likely) more reliable devices and coding fragments to less likely storage devices.