Abstract: A non-volatile (NV) memory accessing method using data protection with aid of look-ahead processing, and associated apparatus such as memory device, controller and encoding circuit thereof are provided. The NV memory accessing method may include: receiving a write command and data from a host device; obtaining at least one portion of data to be a plurality of messages, to generate a plurality of parity codes through look-ahead type encoding, wherein regarding a message: starting encoding a first partial message to generate a first encoded result; applying predetermined input response information to a second partial message to generate a second encoded result, and combining the first and the second encoded results to generate a first partial parity code; and starting encoding the message to generate a second partial parity code, and outputting the first and the second partial parity codes to generate a parity code; and writing into the NV memory.

Abstract: The present invention provides a flash memory controller, wherein the flash memory controller includes a read-only memory, a microprocessor and a decoder, wherein the read-only memory is configured to store a program code, the microprocessor is configured to execute the program code to access a flash memory module, and the decoder includes a hard decoding function and a soft decoding function. In the operations of the flash memory controller, when the flash memory controller and the flash memory module are powered-on, the flash memory controller reads data from a specific block of the flash memory module, and the decoder determines if disabling the soft decoding function or not according to a status of the specific block or a status of the data.

Abstract: In a memory system and an operating method thereof, the method includes: receiving a read command and a read logical address; reading a raw map slice stored in a nonvolatile memory device, in a map read phase, in response to the read command, wherein the raw map slice includes a read physical address corresponding to the read logical address; generating a compressed map slice by compressing the raw map slice; storing a compression class corresponding to a ratio of a size of the compressed map slice to a size of the raw map slice in a compression class description table; storing the compressed map slice in a buffer memory; and reading data corresponding to the read command from the nonvolatile memory device, in a data read phase, based on the compressed map slice stored in the buffer memory.

Abstract: Methods, apparatuses, and systems for error recovery in memory devices are described. A die-level redundancy scheme may be employed in which parity data associated with particular die may be stored. An example apparatus may include a printed circuit board and memory devices. Each memory device may be each disposed on a planar surface of the printed circuit board and may each include two or more memory die. The apparatus may also include multiple channels communicatively coupled to the two or more memory die and a memory controller. The memory controller may be communicatively coupled to the multiple channels and may deterministically maintain a redundancy scheme via data transmission through the multiple channels. The memory controller may also update memory operation information appended to the enhanced codeword in response to a memory operation request.

Abstract: A storage device determines whether or not reading target data subjected to a first conversion process is divided and stored into multiple pages. When the data subjected to the first conversion process is stored in one of a plurality of pages, the data is read from the page, and a second conversion process for returning the data to a state before the data is subjected to the first conversion process is executed to the data. When the reading target data is divided and stored into two or more of the plurality of pages, a portion of the data is read from each of the two or more pages in which the portion of the data is stored, the portion of the data is stored in the buffer memory, the data subjected to the first conversion process is restored, and the second conversion process is executed to the restored data.

Abstract: A semiconductor memory device includes a memory cell array, a peripheral circuit, and a control logic. The memory cell array includes a plurality of memory blocks. The peripheral circuit performs a read operation on a selected memory block among the plurality of memory blocks. The control logic controls the read operation of the peripheral circuit. The selected memory block is coupled to a plurality of bit lines, and the plurality of bit lines are grouped into a plurality of bit line groups. The peripheral circuit performs data sensing by applying different reference currents to the plurality of bit line groups, respectively.

Abstract: A computer-implemented method, according to one embodiment, includes: detecting that an error count resulting from reading a first page in a block of storage space in memory is above a first threshold, and reading a second page in the block of storage space. The second page is one which had a highest error count of the pages in the block of storage space following a last calibration of the block of storage space. Moreover, a determination is made as to whether an error count resulting from reading the second page is above the first threshold. In response to determining that the error count resulting from reading the second page is above the first threshold, the block of storage space is calibrated. Other systems, methods, and computer program products are described in additional embodiments.

Abstract: One embodiment provides a system and method for storing data. During operation, the system receives a to-be-written data chunk, sends the to-be-written data chunk to a first and second storage devices. The system performs first and second error-correction-code (ECC) encoding operations on the to-be-written data chunk prior to writing the to-be-written data chunk to the first and second storage media associated with the first and second storage devices, respectively. The first storage medium has a first access granularity and a first raw-error-rate (RER). The second storage medium has a second access granularity and a second RER. The first access granularity is smaller than the second access granularity, the first RER is greater than the second RER, and the second ECC encoding operation has a stronger error-correction capability than the first ECC encoding operation.

Abstract: A method of compensating charge loss and source line bias in programing of non-volatile memory device including the steps of reading a previous program page with a low reference voltage to make an original previous program pattern, merging the original previous program pattern and a current program pattern to make a merged program pattern, reading the previous program page with a high reference voltage to make a verified previous program pattern, and merging the verified previous program pattern and the merged program pattern to make a compensated current program pattern.

Abstract: A data storage system can receive a data write request to write data to a physical address of a non-volatile semiconductor memory prior to detecting an error while storing the write data to the physical address. The detected error is corrected with a monitor module connected to the non-volatile semiconductor memory and a counter associated with the physical address is incremented with the monitor module in response to the corrected error. The write data can be subsequently read to a host in response to a data read request.

Abstract: A memory management method is provided. The method includes: performing a read operation on a target word line; reading a plurality of target physical pages of the target word line to obtain a plurality of hard bit codewords respectively corresponding to the target physical pages; generating soft information of each of a plurality of target memory cells of the target word line according to the hard bit codewords; identifying a plurality of confidence values corresponding to the target physical pages of each of the target memory cells according to a plurality of confidence tables and the soft information of the target memory cells; and performing an adjusted preset decoding operation according to the confidence values and the soft information, so as to obtain a plurality of final decoded codewords respectively corresponding to the target physical pages and complete the read operation.

Abstract: First and second vectors each respectively having first and second magnitudes and first and second phase angles relative to a reference axis are determined by a processing device based on a set of error values corresponding a current processing level for processing data in memory operations on memory cells of a memory component. An estimated processing level offset is generated based on a comparison between at least one of a difference between the first magnitude and the second magnitude or a difference between the first phase angle and the second phase angle. An updated processing level is generated based on the estimated processing level offset, and the updated processing level replaces the current processing level.

Abstract: A memory system includes a nonvolatile memory device; In an embodiment, a memory system comprising: a nonvolatile memory device; a working memory configured to store a first layer and a second layer as firmwares, each of which drives the nonvolatile memory device; a control component configured to control the nonvolatile memory device based on the firmwares; a buffer memory configured to store a first table which is managed by the first layer and a second table which is managed by the second layer; and a memory controller configured to store a descriptor for setting information of the nonvolatile memory device, and interface with the nonvolatile memory device based on control of the control component, wherein the second layer stores position information of the descriptor in the second table, and wherein the first layer accesses the memory controller by referring to the second table.

Abstract: A data writing method, a memory control circuit unit, and a memory storage device are provided. The method includes: determining whether to use a first programming mode or a second programming mode to program memory cells according to a first data amount and a second data amount; when the first data amount is greater than the second data amount, programming the memory cells by using the first programming mode; and when the first data amount is not greater than the second data amount, programming the memory cells by using the second programming mode.

Abstract: Methods and systems for rebuilding a failed storage device in a data storage system. For example, a method including identifying a first garbage collection group (GCG) in a storage array for garbage collection; extracting valid data and redundancy information from functioning storage devices in the storage array associated with the first GCG; reconstructing data of a failed storage device associated with the first GCG based on the extracted valid data and redundancy information from the functioning storage devices associated with the first GCG; consolidating the extracted valid data from the functioning storage devices and the reconstructed data of the failed storage device associated with the first GCG; writing the consolidated extracted valid data from the functioning storage devices and the reconstructed data of the failed storage device associated with the first GCG to a second GCG in the storage array; and reclaiming the first GCG identified for garbage collection.

Abstract: According to one embodiment, a controller is configured to write four-bit data in each of memory cells, and read first data item from the memory cells through application of a first voltage to a word line. The controller is configured to read second data items by repeating a first operation of reading data including data of respective first bits of the memory cells through application of two voltages to the word line at different timings while changing the two voltages in each first operation from the two voltages in another first operation. The controller is configured to mask part of each of the second data items using the first data.

Abstract: Methods of operating a memory include determining a voltage level of a plurality of voltage levels at which a memory cell is deemed to first activate in response to applying the to a control gate of that memory cell for each memory cell of a plurality of memory cells, determining a plurality of voltage level distributions from numbers of memory cells of a first subset of memory cells deemed to first activate at each voltage level of the plurality of voltage levels, determining a transition between a pair of voltage level distributions for each adjacent pair of voltage level distributions, and assigning a respective data state to each memory cell of a second subset of memory cells responsive to the determined voltage level at which that memory cell is deemed to first activate and respective voltage levels of the transitions for each adjacent pair of voltage level distributions.

Abstract: A memory device includes a memory with a plurality of memory blocks and a first storage circuit to store a first data table and a first refresh value, and a memory controller with a second storage circuit to store a second data table and a second refresh value. When the memory controller meets a refresh request, the memory controller reads the second refresh value and compares the corresponding access address to the corresponding bit in the second data table to determine whether valid data are stored in a specific memory block of the memory. The memory controller sends a valid-data refresh command to the memory when valid data are stored in the specific memory block, but sends an invalid-data refresh command to the memory when invalid data are stored in the specific memory block.

Abstract: The invention provides a memory management method, a memory storage device, and a memory control circuit unit. The method includes: recording an error bit number of each upper physical programming unit and an error bit number of each lower physical programming unit of each of the physical erasing units; determining whether a first physical erasing unit is a bad physical erasing unit according to distributions of the error bit numbers of the upper physical programming units and the lower physical programming units of the first physical erasing unit of the physical erasing units; and performing a data transfer operation on data in the first physical erasing unit if the first physical erasing unit is determined as the bad physical erasing unit.

Abstract: A scrubbing controller of a semiconductor memory device includes a scrubbing address generator and a weak codeword address generator. The scrubbing address generator generates a scrubbing address for all codewords in a first bank array of a plurality of bank arrays in a first scrubbing mode. The scrubbing address is associated with a normal scrubbing operation and changes in response to an internal scrubbing signal and a scrubbing command. The weak codeword address generator generates a weak codeword address for weak codewords in the first bank array in a second scrubbing mode. The weak codeword address is associated with a weak scrubbing operation and is generated in response to the internal scrubbing signal.

Abstract: A method for operating a data storage device including a non-volatile memory device including a first region and a second region includes: storing data from a data cache memory in memory blocks in the first region; determining a first garbage collection cost with respect to a first target memory block having the least valid page among the memory blocks in the first region in which the data are kept; determining a second garbage collection cost with respect to a second target memory block having the least valid page among the memory blocks in the first region from which the data are cleared; and performing a garbage collection operation to copy valid data of a garbage collection target memory block into memory blocks in the second region based on a comparison result of the first garbage collection cost and the second garbage collection cost.

Abstract: A method for operating a memory device includes: receiving a first read command and a first address; reading a first read data and a first error correction code from memory cells selected based on the first address; detecting and correcting an error of the first read data using the first error correction code; storing the first address as an error detection address in an address latch circuit; storing an error-corrected bit of the first read data and a position of the error-corrected bit of the first read data in a data latch circuit; and transmitting an error-corrected first read data to an external device.

Abstract: A nonvolatile memory device includes a memory cell array including a plurality of nonvolatile memory cells; a page buffer circuit connected to the memory cell array through a plurality of bit lines; a calculation circuit configured to perform a calculation on information bits and weight bits based on a calculation window having a first size, the information bits and weight bits being included in a user data set, the memory cell array being configured to store the user data set, the calculation circuit being further configured to receive the user data set through the page buffer circuit; and a data input/output (I/O) circuit connected to the calculation circuit, wherein the calculation circuit is further configured to provide an output data set to the data I/O circuit in response to the calculation circuit completing the calculation with respect to all of the information bits and the weight bits, and wherein the output data set corresponds to a result of the completed calculation.

Abstract: A method for re-reading page data is provided. The method for re-reading page data classifies each of the retry tables into one of a plurality of retry types, and when starting the re-reading procedure, the method will firstly select a retry type based on the environmental parameters related to reading the target page, and select a retry table from the selected retry type and re-read the data of the target page according to the read parameters of the retry table, thereby reducing a number of times of repetitively reading the target page and preventing read disturbance caused by frequent reading.

Abstract: A storage device includes a nonvolatile memory device and a controller configured to read data from the nonvolatile memory device, to divide the read data into a plurality of segments, and to sequentially perform error correction decoding with respect to the plurality of segments. When the error correction decoding of each segment is completed, the controller adds error correction parity to each of the decoded segments and sends the decoded segments with added error correction parity to an external host device. When error correction decoding of a second segment is not completed after a threshold time has elapsed after sending a first segment of which error correction decoding is completed, the controller adds an incorrect error correction parity to dummy data and sends the dummy data with the added incorrect error correction parity to the external host device.

Abstract: A data storage device includes a memory device and a controller. The memory device includes multiple memory blocks. Each memory block includes multiple pages. The controller is coupled to the memory device and includes an ECC engine configured to check and correct errors that have occurred in data stored in the memory blocks. When a number of error bits in a page of one of the memory blocks exceeds a threshold, the controller is configured to add a block number of the memory block in a predetermined queue and when a garbage collection procedure has been triggered, the controller is configured to perform garbage collection on the memory block.

Abstract: An embodiment of a semiconductor apparatus may include technology to determine an error rate associated with a read request for a persistent storage media, compare the determined error rate against a pre-fail threshold, and adjust a read voltage shift direction for the persistent storage media if the determined error rate exceeds the pre-fail threshold. Other embodiments are disclosed and claimed.

Abstract: A memory device includes a semiconductor memory unit, a controller circuit configured to communicate with a host through a serial interface, store write data to be written into a page of the semiconductor memory unit in a data buffer, and an error-correcting code (ECC) circuit configured to generate an error correction code from the write data if the ECC circuit is enabled. The controller circuit writes the error correction code with the write data into the page if the ECC circuit is enabled. A maximum column address of the page which is accessible from the host changes depending on whether or not the ECC circuit is enabled.

Abstract: Embodiments of the invention provide a computer-implemented method for managing cryptographic objects in a key management system. This system comprises a set of one or more hardware security modules (HSMs), as well as clients interacting with the HSMs on behalf of users who interact with the clients. The method comprises monitoring, for each HSM of the set, an entropy pool and/or a load at each HSM. The entropy pool of a HSM is the entropy that is available at this HSM for generating cryptographic objects. The load induced at a HSM is the load due to the users interacting with the clients to obtain cryptographic objects. Cryptographic objects are generated, at each HSM, according to the monitored entropy pool and/or load. The extent to which such objects are generated depends on the monitored entropy pool and/or load.

Abstract: Apparatuses, systems, and methods to perform continuous read operations are described. A system configured to perform such continuous read operations enables improved access to and processing of data for performance of associated functions. For instance, one apparatus described herein includes a memory device having an array that includes a plurality of pages of memory cells. The memory device includes a page buffer coupled to the array and a continuous read buffer. The continuous read buffer includes a first cache to receive a first segment of data values and a second cache to receive a second segment of the data values from the page buffer. The memory device is configured to perform a continuous read operation on the first and second segments of data from the first cache and the second cache of the continuous read buffer.

Abstract: A solid state storage device includes a control circuit and a non-volatile memory. The control circuit includes a retry table. In addition, plural retry read-voltage sets are recorded in the retry table, and the retry table is divided into plural retry sub-tables. The plural retry read-voltage sets are classified into plural groups. The plural retry read-voltage sets are recorded into the corresponding retry sub-tables. The non-volatile memory is connected with the control circuit. During a read retry process of a read cycle, the control circuit performs a hard decoding process according to a retry sub-table of the plural retry sub-tables. If the hard decoding process fails, the control circuit performs a soft decoding process according to another retry sub-table of the plural retry sub-tables.

Abstract: A nonvolatile memory device includes multiple memory blocks. A first memory block stores first data. A reference memory block stores an indicator indicating the first memory block as an indication in response to a first direct access command received from the outside. A first physical area of the first memory block is accessed according to a page address received from the outside together with the first direct access command, and the indication of the indicator.

Abstract: A non-volatile memory unit receives a request from a controller to read encoded data stored in a non-volatile memory of the non-volatile memory unit. In response to determining by logic included in the non-volatile memory unit that the controller is estimated to be able to successfully decode the encoded data more than a predetermined percentage of times, the encoded data is transferred from the non-volatile memory unit to the controller.

Abstract: A high-density storage system includes a memory device, and a controller including a range allocation and program order block configured to determine a range of a threshold voltage for each level of each memory cell of the memory device, based on initial data and an interference in the memory device, and determine an order in which groups of memory cells of the memory device are programmed, based on the interference. The controller further includes a statistical cell correction block configured to perform statistical cell correction on the range of the threshold voltage for each level of each memory cell, based on the order in which the groups of the memory cells are programmed and reference information of each level of each memory cell of the memory device that is received from the memory device.

Abstract: A method and system for visualizing a correlation between host commands and storage system performance are provided. In one embodiment, a method comprises receiving information concerning host operations of a host performed over a time period; receiving information concerning storage system operations of a storage system performed over the time period; and simultaneously displaying both the host operations and the storage system operations over the time period. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: According to an aspect of inventive concepts, there is provided a memory controller configured to control a memory device including a plurality of memory pages, the memory controller including an error correction code (ECC) region manager configured to manage the plurality of memory pages by dividing the plurality of memory pages into ECC enable regions and ECC disable regions, and an ECC engine configured to perform an ECC operation on data included in the ECC enable regions.

Abstract: Inventive aspects include An HBM+ system, comprising a host including at least one of a CPU, a GPU, an ASIC, or an FPGA; and an HBM+ stack including a plurality of HBM modules arranged one atop another, and a logic die disposed beneath the plurality of HBM modules. The logic die is configured to offload processing operations from the host. A system architecture is disclosed that provides specific compute capabilities in the logic die of high bandwidth memory along with the supporting hardware and software architectures, logic die microarchitecture, and memory interface signaling options. Various new methods are provided for using in-memory processing abilities of the logic die beneath an HBM memory stack. In addition, various new signaling protocols are disclosed to use an HBM interface. The logic die microarchitecture and supporting system framework are also described.

Abstract: The present invention discloses a system for storing a blockchain on a distributed network. The system includes a distributed network containing a plurality of nodes. The system stripes a blockchain into individual blocks where each individual block is separately encrypted and stored on a different node of the distributed network. The system forms a parity block from the individual blocks striped from the single blockchain. The parity block is separately encrypted and stored on a node of the distributed network separate from the other nodes storing the individual blocks for the blockchain. The system uses a blockchain distributed network map identifying where all of the individual blocks and the parity block are stored on the distributed network to reassemble all of the individual blocks into an undivided single blockchain.

Abstract: A memory system includes: a memory device including a plurality of memory blocks; and a controller suitable for selecting one or more first memory blocks based on a predetermined condition among the plurality of the memory blocks in a booting section, and increasing a read reclaim count value of one or more second memory blocks among the one or more first memory blocks for which a number of failed bits of read data exceeds a predetermined threshold.

Abstract: A bit tagging method, a memory control circuit unit and a memory storage device are provided. The method includes: reading first memory cells according to a first reading voltage to generate a first codeword and determining whether the first codeword is a valid codeword, and the first codeword includes X bits; if not, reading the first memory cells according to a second reading voltage to generate a second codeword and determining whether the second codeword is the valid codeword, and the second codeword includes X bits; and if the second codeword is not the valid codeword and a Yth bit in the X bits of the first codeword is different from a Yth bit in the X bits of the second codeword, recording the Yth bit in the X bits as an unreliable bit, and Y is a positive integer less than or equal to X.

Abstract: Various aspects directed towards facilitating error management within a shared non-volatile memory (NVM) architecture are disclosed. Data programmed into a plurality NVM cells is encoded prior to programming, and a range of programmability associated with each of the plurality of NVM cells is determined when the plurality of NVM cells are programmed A first error management scheme is then applied to NVM cells identified as limited-range programmable cells, and a second error management scheme is applied to NVM cells identified as full-range programmable cells, such that the second error management scheme is different than the first error management scheme.

Abstract: A data storage method and a solid state disk (SSD) are provided. The method comprises: obtaining, by the SSD, target data; determining a target buffer for storing the target data between a first buffer and a second buffer based on a data type of the target data, wherein the first buffer is a buffer preset in a memory of an electronic device which includes the SSD, and the second buffer is an inherent buffer in the SSD; and caching the target data into the target buffer.

Abstract: Technology for a NAND memory is described. The NAND memory can include a first-type dedicated memory block. The NAND memory can include a second-type dedicated memory block. The NAND memory can include logic to perform a data operation on the first-type dedicated memory block using a first first-type access mode. The NAND memory can include logic to perform a data operation on the variable-type memory block using a second first-type access mode.

Abstract: A data storage device includes a flash memory, a controller and a random-access memory. The flash memory includes a plurality of blocks, and each of the blocks includes a plurality of pages. The controller divides the pages of the blocks into a plurality of super pages which include a plurality of first pages and a plurality of second pages. The controller writes at least one super page data to one of the first pages, generates a parity code based on the at least one super page data, and stores the parity code on the random-access memory.

Abstract: In a layered coding approach, a code configuration parameter of a polar code is determined, and encoding graph parameters are determined based on the determined code configuration parameter. The encoding graph parameters identify inputs for one or more kernel operations in each of multiple encoding layers. Information symbols are encoded by applying the one or more kernel operations to the inputs identified in each encoding layer in accordance with the determined encoding graph parameters.

Abstract: A data storage device may include: a memory cell array, a data buffer configured to generate a data chunk including a plurality of pages from input data provided from a host, a data compressor configured to compress the data chunk and output the compressed data chunk as write data, a write queue configured to store the write data on a page basis, a mapping table configured to store a mapping relationship between a logical address and a data chunk address, and a mapping relationship between the data chunk address and a physical address; and a controller configured to control an operation of storing the write data outputted from the write queue in the memory cell array such that a page including both a part of any one compressed data chunk and a part of another compressed data chunk is written to the memory cell array.

Abstract: A data storage device with high security is disclosed. A nonvolatile memory provides a storage space divided into a plurality of first-level cells. The first-level cells are grouped into a plurality of second-level cells with each second-level cell containing several first-level cells. Each of the plurality of first-level cells is provided with checking and correcting code by a control unit. When reading a specified first-level cell, the control unit checks data in the specified first-level cell based on the checking and correcting code of the specified first-level cell and thereby performs a self-test on another space of a specified second-level cell. The specified first-level cell is provided in the specified second-level cell.

Abstract: An operation method of a controller includes: generating a predetermined number of sub-messages by dividing an original message; generating a first parity added message by adding a cyclic redundancy check (CRC) parity message of a predetermined length to each of the sub-messages; and generating an encoded message by performing a polar encoding operation to the first parity added message.

Abstract: A data protecting method, a memory control circuit unit and a memory storage device are provided. The method includes repeatedly reading data from a first physical programming unit of a first physical erasing unit during an initialization operation after the memory storage device is powered on, wherein the first physical programming unit is the last programmed physical programming unit before the memory storage device is powered off. The method also includes updating a logical-physical mapping table according to the first physical programming unit if a number of error bits of data read each time is not greater than an error bits amount threshold and a reading count of the first physical programming unit is greater than a predetermined count.

Abstract: A redundant array of inexpensive disks (RAID) system including nonvolatile memory and an operating method of the same is provided. A nonvolatile memory device implemented as a RAID and including a plurality of first memory chips, which store data chunks, and a second memory chip, in which spare memory regions are defined. A RAID controller controls RAID operations and a rebuild operation of the nonvolatile memory device. The RAID controller monitors a failure probability of each of the first memory chips, and in response to detecting a failure probability of two or more first memory chips that satisfies a predefined threshold value, a first rebuild on data stored in each of the first memory chips is performed to store the data in the second memory chip. A second rebuild on data stored in the first memory chip having the failure using data stored in the second memory chip.