Abstract: A data storage device includes a memory including a plurality of storage elements. The data storage device further includes a controller coupled to the memory. The controller includes an error correction code (ECC) engine. The controller further includes a reliability engine configured to access historical bit error data. The historical bit error data includes a first count of bit errors associated with a first set of storage elements of the plurality of storage elements. The reliability engine is configured to generate reliability information based on the historical bit error data and to provide the reliability information to the ECC engine.

Abstract: A system for error correction code (ECC) management of write-once memory (WOM) codes includes, for example, a controller for selecting between one of a WOM (Write-Only Memory) mode and an ECC (error correction code) mode. A codec is arranged to operate in the selected mode. The codec while operating in the ECC mode is arranged to identify a bit position of at least one bit error in response to ECC parity bits of a first received data word. The codec while operating in the WOM mode is arranged to receive a WOM-encoded word from an addressed location in a WOM device, to receive a second received data word to be encoded and written to the addressed location, and to generate WOM-encoded word for writing to the addressed location in the WOM device. The WOM-encoded word for writing to the addressed location is optionally ECC encoded.

Abstract: A processor or hard-wired logic circuit of an information processing device is configured to collect a life-expectancy index value of a first semiconductor storage device of primary semiconductor storage devices. The life-expectancy index value relates to a remaining number of times written data is able to be erased. The processor or hard-wired logic circuit is configured to collect read/write information regarding read/write access including read access of reading data from the first semiconductor storage device and write access of writing data to the first semiconductor storage device. The processor or hard-wired logic circuit is configured to determine, based on the collected read/write information, a criterion threshold used as a criterion for replacement of the first semiconductor storage device, and replace the first semiconductor storage device with a second semiconductor storage device of secondary semiconductor storage devices if the life-expectancy index value is less than the criterion threshold.

Abstract: A memory circuit is described comprising a plurality of memory elements, wherein each memory element is configured to store one data element of a plurality of data elements, an error correction information memory configured to store joint error correction information of the plurality of data elements, for each memory element, an error detection information memory storing error detection information for the data element stored in the memory element and a memory access circuit configured to, for an access to a memory element of the plurality of memory elements, check whether the error detection information for the data element stored in the memory element indicates an error of the data element stored in the memory element and, depending on whether the error detection information for the data element stored in the memory element indicates an error of the data element stored in the memory element, to process the error correction information for the access.

Abstract: Systems, methods, and/or devices are used to implement variable bit encoding per NAND flash cell to extend life of flash-based storage devices and preserve over-provisioning. In some embodiments, the method includes detecting a trigger condition with respect to one or more non-volatile memory portions (e.g., portions configured to store data encoded in a first encoding format and having a first storage density) of a plurality of non-volatile memory portions of a storage device. In response to detecting the trigger condition and in accordance with a first determination that a projected amount of over-provisioning (e.g., corresponding to over-provisioning for the storage device after reconfiguring the one or more non-volatile memory portions to store data encoded in a second encoding format and having a second storage density) meets predefined over-provisioning criteria, the method includes reconfiguring the one or more non-volatile memory portions to store data encoded in the second encoding format.

Abstract: A method for operating a memory controller includes: performing a hard decision read operation to read hard decision data from a memory device; if a hard decoding for the hard decision data fails, assigning log likelihood ratio (LLR) values to cells falling in a plurality of voltage regions corresponding to a plurality of read reference voltages; performing a soft decision read operation based on the LLR values and a soft decoding for the soft decision data to generate an error free data; performing a read operation to read data from the memory device using each of the plurality of read reference voltages to generate raw data for each of the plurality of read reference voltages; and determining an optimal read reference voltage among the plurality of the read reference voltages based on the raw data and the error free data.

Abstract: A method includes storing data in a memory that includes multiple analog memory cells. After storing the data, an interference caused by a first group of the analog memory cells to a second group of the analog memory cells is estimated. The data stored in the first group is reconstructed based on the estimated interference caused by the first group to the second group.

Abstract: According to one embodiment, a memory controller includes a writing destination management unit which determines a writing destination of user data, an encoding unit which generates a parity of the user data, and an ECC management unit which measures a fatigue degree of each certain memory area of a nonvolatile memory, selects an encoding method to instruct the encoding unit to be performed according to the encoding method, and changes the encoding method to an encoding method having a high error correction capability in a case where the fatigue degree corresponding to the writing destination is equal to or higher than a threshold and a total sum of parities is equal to or less than a predetermined amount.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for error correcting code (ECC) decoding. A soft information module may be configured to determine whether to obtain an indication of the accuracy of a data value for a variable node of an ECC decoder such as a low density parity check (LDPC) code decoder. A score module may be configured to assign and update a score for the variable node. The score may be based on the accuracy indication and on a count of unsatisfied check nodes of the ECC decoder that are associated with the variable node. A precision for the score may be based on an estimated number of errors for the received code word. A check node update module may be configured to update check nodes associated with the variable node based on the score.

Abstract: A flash memory codeword architecture is provided. A non-integer count of logical pages is packed into a codeword payload data container. A codeword payload header is generated. The codeword payload header includes an offset to a first logical page that is packed, at least in part, into the codeword payload data container. The codeword payload data container and the codeword payload header are concatenated to generate a codeword payload. Error-correcting code data is generated based, at least in part, on the codeword payload using a systematic error-correcting code. The codeword payload and error-correcting code data is concatenated to generate a codeword. A physical page is programmed with the codeword.

Abstract: A system and method reading, accumulating and processing soft information for use in LDPC decoding. In accordance with the present invention, an LDPC decoder includes accumulation circuitry to receive soft reads of a cell of the nonvolatile memory storage module and to produce an accumulated soft read that can be used to identify an appropriate LLR for the cell. The accumulation circuitry of the present invention may include, an accumulation RAM, an arithmetic logic unit (ALU) and a soft accumulation control and sequencing module for accumulating and processing soft information for use in LDPC decoding.

Abstract: Instructions and logic provide vector horizontal majority voting functionality. Some embodiments, responsive to an instruction specifying: a destination operand, a size of the vector elements, a source operand, and a mask corresponding to a portion of the vector element data fields in the source operand; read a number of values from data fields of the specified size in the source operand, corresponding to the mask specified by the instruction and store a result value to that number of corresponding data fields in the destination operand, the result value computed from the majority of values read from the number of data fields of the source operand.

Abstract: A memory system is provided. The memory system includes a memory device suitable for reading out data from memory cells by a plurality of read voltages having various levels, and a controller suitable for updating probabilistic information based on the read out data when the read out data is input to the controller, and performing an error correction operation by the updated probabilistic information, wherein the controller updates the probabilistic information a predetermined number of times that the memory device reads out the data.

Abstract: The present invention relates to a distributed storage scheme, wherein every file is optionally encrypted, optionally interleaved, fragmented, and the various fragments stored on different constituent storage systems commensurate with the storage mechanisms supported by those storage providers.

Abstract: An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/write operations. The memory may comprise a plurality of memory modules each having a size less than a total size of the memory. The controller may be configured to write user data using a redundancy scheme. Information about the redundancy is (i) stored in a location separate from the data and (ii) used to recover potentially corrupted user data.

Abstract: A composite semiconductor memory device, comprising: a plurality of nonvolatile memory devices; and an interface device connected to the plurality of nonvolatile memory devices and for connection to a memory controller, the interface device comprising an error correction coding (ECC) engine. Also, a memory system, comprising: a memory controller; and at least one composite semiconductor memory device configured for being written to and read from by the memory controller and comprising a built-in error correction coding (ECC) engine.

Abstract: A storage controller includes: an error information management section configured to manage information in a plurality of addresses of a memory; and a refresh object determination section configured to determine a refresh object address in the memory based on the error information.

Abstract: An apparatus having a circuit and an interface to a nonvolatile memory is disclosed. The circuit is configured to (i) perform one or more attempts of a soft-decision decode of data stored in the nonvolatile memory, where soft-decision decode uses a plurality of log likelihood ratio values stored in a table, (ii) generate one or more adjusted log likelihood ratio values by adding a constant value to one or more of the log likelihood ratio values in response to a failure to decode the data using the log likelihood ratio values and (iii) re-decode the data using the adjusted log likelihood ratio values.

Abstract: A method for analyzing a read error event is provided comprising reading a page of data stored in memory, determining a read error event for the page of data, and identifying a scope of the read error event in the memory. In another embodiment, a method for performing a preliminary read error recovery is provided comprising reading a first data unit from memory and identifying a bit error rate for a first data unit with a correction engine, determining that the bit error rate is above a threshold, accessing a data structure including entries identifying data units and read error event information associated with the data units, identifying a second data unit in an entry that matches the first data unit, and performing a preliminary read error recovery process on the first data unit using the information in the entry to reduce the bit error rate below the threshold.

Abstract: According to one embodiment, a memory controller that controls non-volatile memory including a data area and a parity area in which parity for data of a fixed length to be stored in the data area is stored, the memory controller including a coding unit configured to generate parity for each of two or more partial data, each of which has a length less than the fixed length, and the memory controller writing one of the parity generated by the coding unit onto the parity area as first parity, writing the partial data and second parity that is the parity, other than the first parity, generated by the coding unit, onto the data area as the data of the fixed length, and writing the second parity onto a position subsequent to the partial data corresponding to the second parity.

Abstract: A GNSD (Green NAND Solid State Drive) Driver coupled to host DRAM, and having a memory manager, a data grouper engine, a data ungrouper engine, a power manager, and a flush/resume manager. The GNSD driver is coupled to a GNSD application, and the host DRAM to a Non-Volatile Memory Device. The GNSD Driver further includes a compression/decompression engine, a de-duplication engine, an encryption/decryption engine, or a high-level error correction code engine. The encryption/decryption engine encrypts according to DES (Data Encryption Standard) or AES (Advanced Encryption Standard). A method of operating a GNSD Driver and a GNSD application coupled to DRAM of a host, includes coupling: Configuration and Register O/S Settings to the host and the GNSD Application; a data grouper and data ungrouper to the host DRAM and to Upper and a Lower Filter; a power manager and a memory manager to the host; a flush/resume manager to the DRAM; and the DRAM to an (Super Enhanced Endurance Device) SEED SSD (Solid State Drive).

Abstract: The present invention discloses a receiver and a method for data processing. The receiver includes a system on chip and a memory, where the system on chip is connected to the memory through an external buffer bus; the system on chip includes an LLR subsystem, a controller, a rate matching module, an incremental redundancy IR reconstructing module, and a combiner, where the LLR subsystem is connected to the controller and the rate matching module respectively; the controller is connected to the IR reconstructing module, and the rate matching module and the IR reconstructing module are connected to the combiner respectively; and the controller stores LLR data currently corresponding to a data block demodulated by the LLR subsystem into a memory, and read LLR data historically corresponding to the data block and stored in the memory into the IR reconstructing module when the data block is a retransmitted data block.

Abstract: A sequence code verification system can be designed to include a data reader, a validity engine, and an error notifier. The data reader can read sequence codes from consecutive logical blocks. The validity engine can invalidate write operations in response to checking data validity by applying comparison operations to sequence codes and block offsets of batch write operations. The error notifier can notify a user of an error for each invalidated write operation batch. The system can validate data written to logical blocks on a storage subsystem adapted so that, during write operations, an additional sequence code is written to each logical block of data. The sequence code can remain constant for each write operation batch and the sequence code can be incremented for each new write operation batch.

Abstract: Data protection across multiple memory blocks can include writing a first portion of a codeword in a first location of a first memory block and writing a second portion of the codeword in a second location of a second memory block. The second location of the second memory block can be different than the first location of the first memory block.

Abstract: A RAID storage system serializes data blocks to be stored in a RAID storage array and uses a primary map table and a number of secondary map tables to relate host addresses to logical block addresses in the storage array. Secondary map tables and other metadata can be cached from the storage array. The dual or two-tier map scheme and metadata caching promote scalability.

Abstract: A paging scheme for a Solid State Drive (SSD) error correction mechanism that exchanges portions of a parity component, such as a page, between SRAM and less expensive DRAM, which stores the remainder of a context of pages. A parity operation applies an XOR function to corresponding memory positions in the pages of the context. Dedicated error correction (parity) SRAM need only enough memory for portions of memory, typically a cache line of a page, upon which the parity operation (XOR) is operating. The remaining portions in the context are swapped, or paged out, by cache logic such that the entire context is iteratively processed (XORed) by the parity operation.

Abstract: A method includes receiving input blocks each having multiple bits to be transmitted. The method also includes applying a first encoding scheme to a first subset of the bits in the input blocks to generate first encoded bits and applying a second encoding scheme to a second subset of the bits in the input blocks to generate second encoded bits. The second encoding scheme has lower overhead than the first encoding scheme. The method further includes generating symbols using the first and second encoded bits. The first encoded bits include two or more first bits per symbol of each output block, and the second encoded bits include one or more second bits per symbol of each output block.

Abstract: A data storage device includes a memory having a three-dimensional (3D) memory configuration. A method includes encoding first data to be stored at a first physical page. The first physical page is disposed within the memory at a first distance from a substrate of the memory, and the first data is encoded using a first encoding technique. The method further includes encoding second data to be stored at a second physical page. The second physical page is disposed within the memory at a second distance from the substrate that is greater than the first distance. The second data is encoded using a second encoding technique that is different than the first encoding technique.

Abstract: A test apparatus that tests a device under test, comprising a control apparatus sequentially executing a plurality of test programs and controlling testing of the device under test; and a test module controlled by the control apparatus to test the device under test by communicating with the device under test and to transmit a test result of each test program to the control apparatus. The test module includes memories that store the test results of the test programs, and starts a subsequent test such that at least a portion of a result processing time period of a current test, from when a test result stored in a first memory begins being transmitted to the control apparatus to when processing of the test result by the control apparatus ends, overlaps with at least a portion of a test execution period in which the subsequent test is executed using a second memory.

Abstract: The present disclosure includes apparatuses and methods for memory system data management. A number of embodiments include writing data from a host to a buffer in the memory system, receiving, at the buffer, a notification from a memory device in the memory system that the memory device is ready to receive data, sending at least a portion of the data from the buffer to the memory device, and writing the portion of the data to the memory device.

Abstract: A memory card and methods for testing memory cards are disclosed herein. The memory card has a test interface that allows testing large numbers of memory cards together. Each memory card may have a serial data I/O contact and a test select contact. The memory cards may only send data via the serial data I/O contact when selected, which may allow many memory cards to be connected to the same serial data line during test. Moreover, existing test socket boards may be used without adding additional external circuitry. Thus, cost effective testing of memory cards is provided. In some embodiments, the test interface allows for a serial built in self test (BIST).

Abstract: Methods for data recovery and memory systems are provided. According to at least one such method, when defective data is read from a memory location, the data is recovered by an XOR operation on the remaining good data and associated RAID data to reconstruct the defective data. The defective data is excluded from the XOR operation.

Abstract: The present invention is a method for accessing more than one block of correctable information at a time when it is most efficient to access more bits of information at a time on a given dimension, for example from a multiple bit per cell (MLC) memory element, than the error correction algorithm can correct. Since it may be more efficient to access more bits of information at a time on a given dimension than the error correction algorithm can correct, that access is performed in this most efficient way, but the information is divided into correctable blocks within this information such that the error correction algorithm can still compensate for a serious fault along a given dimension. Furthermore, the present invention can be employed even when the number of bits retrieved along a given dimension is less than the number of correctable bits when it is desired to protect against a given number of faults which could, in total, exceed the number of correctable bits.

Abstract: Apparatuses and methods involving the determination of soft data from hard reads are provided. One example method can include determining, using a hard read, a state of a memory cell. Soft data is determined based, at least partially, on the determined state.

Abstract: A memory system includes: a first non-volatile memory used for storing data to be accessed in block units; a second non-volatile memory used for storing data to be accessed in word units in random accesses to the second non-volatile memory; and a control section configured to control operations of the first and second non-volatile memories, wherein error correction codes to be applied to data stored in the second non-volatile memory are held in the first non-volatile memory.

Abstract: Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be implemented using relatively inexpensive MLC Flash for an enterprise storage application. Predefined gears correspond to different predefined ECC schemes. Based on an observed bit error rate, a gear from a set of predefined gears is selected for use for a particular region of memory. Each gear of the set of predefined gears includes a lower-latency ECC decode option and one or more higher-latency ECC decode options.

Abstract: The present disclosure includes methods, devices, and systems for determining and using soft data in memory devices and systems. One or more embodiments include an array of memory cells and control circuitry coupled to the array. The control circuitry is configured to perform a number of sense operations on the memory cells using a number of sensing voltages to determine soft data associated with a target state of the memory cells, and adjust a sensing voltage used to determine the target state based, at least partially, on the determined soft data.

Abstract: A memory system includes a flash subsystem for storing data identified by page numbers. The memory system further includes a central processing unit (CPU), and a flash controller coupled to the CPU, the CPU being operable to pair a lower with an upper page. Further included in the memory system is a buffer including a page of data to be programmed in a block of the flash subsystem, wherein split segments of pages are formed and concatenated with split error correcting code (ECC), the ECC having a code rate associated therewith.

Abstract: According to one embodiment, a memory controller in an embodiment includes an encoding unit configured to generate a first parity group from first group data including first and second unit data using G1 (x), generate a second parity group from second group data including third and fourth unit data using G1 (x), and generate a third parity group from the first and second group data and the first and second parity groups using G2 (x), a root of which continues form a root of G1 (x). The memory controller writes the first to fourth unit data and the first to third parity groups in different pages of a nonvolatile memory.

Abstract: A method of operating a memory device to guarantee program reliability and a memory system using the same are provided. The method includes backing up data stored in the memory cells connected to a first word line, performing a dummy program operation on memory cells connected to a second word line adjacent to the first word line, and performing a recharge program operation on the memory cells connected to the first word line.

Abstract: Systems and methods are disclosed for monitoring the time it takes to perform a write operation, and based on the time it takes, a determination is made whether to retire a block that is a recipient of the write operation. The time duration of the write operation for a page or a combination of pages may indicate whether any block or blocks containing the page or combination of pages is experiencing a physical failure. That is, if the time duration of the write operation for a particular page exceeds time threshold, this may indicate that this page requires a larger number of program cycles than other pages. The longer programming cycle can be an indication of cell leakage or a failing block.

Abstract: A method may be performed in a data storage device that includes a memory including a three-dimensional (3D) memory and a controller, in response to a request to read data from the memory. The data is located within a first word line of the memory. The method includes accessing the data from the first word line and determining, based on a probability threshold, whether to perform a remedial action with respect to a second word line.

Abstract: Approaches for decoding data read from memory cells of a nonvolatile, solid state memory involve attempting to decode hard data using a hard decoding process prior to a time that soft data is available to the decoder. The hard data includes information about the digital symbols stored in the memory cells without data confidence information. The soft data includes information about the digital symbols stored in the memory cells and data confidence information. In response to the hard decoding process failing to achieve convergence, after the soft data becomes available to the decoder, the soft data is decoded using a soft decoding process. The decoder generates an output of the decoded data after the hard decoding process or the soft decoding process achieves convergence.

Abstract: A storage module is configured to store data segments, such as error-correcting code (ECC) codewords, within an array comprising a plurality of columns. The ECC codewords may comprise ECC codeword symbols. The ECC symbols of a data segment may be arranged in a horizontal arrangement, a vertical arrangement, a hybrid channel arrangement, and/or vertical stripe arrangement within the array. The individual ECC symbols may be stored within respective columns of the array (e.g., may not cross column boundaries). Data of an unavailable ECC symbol may be reconstructed by use of other ECC symbols stored on other columns of the array.

Abstract: In accordance with at least one embodiment, a method and apparatus for improving the ability to correct errors in memory devices is described. At least one embodiment provides a way to salvage the part even it has double-bit or multi-bit error from the same ECC section, thus improving product reliability and extending the product lifetime. During a normal read, if a double-bit or multiple-bit error happens, which ECC can detect but cannot fix, the error is corrected by adjusting the read voltage level and reading again to determine the proper read level (and, therefore, the correct value being read). This dynamic read scheme can apply to extrinsic bits from either erase state or program state. It can be also used in a single bit scenario to minimize ECC occurrence and save ECC capacity.

Abstract: A method of restoring an ECC syndrome in a non-volatile memory device having memory cells arranged in a plurality of sectors within a memory cell array, the method comprising identifying a first sector including at least one page having a disabled ECC (error correction code) flag; reading the value of all data bits in said at least one page; calculating values for ECC bits in said at least one page; and writing said data bit values and said calculated ECC bit values to a second sector in the memory cell array.

Abstract: Apparatus and methods store error recovery data in different dimensions of a memory array. For example, in one dimension, block error correction codes (ECC) are used, and in another dimension, supplemental error correction codes, such as convolutional codes, are used. By using separate dimensions, the likelihood that a defect affects both error recovery techniques is lessened, thereby increasing the probability that error recovery can be performed successfully. In one example, block error correction codes are used for data stored along rows, and this data is stored in one level of multiple-level cells of the array. Supplemental error correction codes are used for data stored along columns, such as along the cells of a string, and the supplemental error correction codes are stored in a different level than the error correction codes.

Abstract: A method for encoding a data word for writing an encoded data word in N cells of a solid state memory. Each of the N cells can be programmed in one of q nominal levels. The method includes encoding the data word as a codeword of a first codeword type having q symbol values or as a codeword of a second codeword type having (q?d) symbol values, d?[1, . . . , q?1], depending on a state of the N cells.

Abstract: The present invention relates to the field of data storage, and more particularly to an estimation technology in an error correction process of a flash memory. The present invention provides an error estimation module and an error estimation method thereof for a flash memory. The estimation module mainly includes a timer, a quantification index table, a storage page table, and an error index table. The error estimation method of a flash memory includes: creating rewriting and programming error a priori data, and estimating an error rate of the flash memory by using special physical signals in a flash memory device to provide proper error estimation for an error correction algorithm of the flash memory. The present invention is applicable to a solid-state hard disk controller, a flash memory controller, and the like, where the flash memory device is used as a storage medium, so that the reliability of the flash memory device is improved.

Abstract: An apparatus for reading a flash memory includes a read controller operable to read the flash memory to yield read patterns, a likelihood generator operable to map the read patterns to likelihood values, a decoder operable to decode the likelihood values, a data state storage operable to retrieve the likelihood values for which decoding failed, and a selective dampening controller operable to select at least one dampening candidate from among the likelihood values for which decoding failed, to dampen the likelihood values of the at least one dampening candidate to yield dampened likelihood values, and to provide the dampened likelihood values to the decoder for decoding.