Abstract: A method of storing data includes receiving data including a first group of bits and a second group of bits and initiating a shaping encoding operation on the second group of bits to generate a third group of bits. The third group of bits has more bits than the second group of bits. The shaping encoding operation is configured to produce a non-uniform probability distribution of bit values in the third group of bits. The first group of bits and first error correction coding (ECC) parity bits corresponding to the first group of bits are stored to a first logical page that is within a physical page of a MLC memory and the third group of bits and second ECC parity bits corresponding to the third group of bits are stored to a second logical page that is within the physical page of the MLC memory.

Abstract: Methods and apparatus related to PCMS (Phase Change Memory with Switch) write error detection are described. In one embodiment, a first storage unit stores a single bit to indicate whether an error corresponding to a write operation in any of one or more PCMS devices has occurred. Also, one or more storage units each store a plurality of bits to indicate whether the error corresponding to the write operation has occurred in a partition of a plurality of partitions of the one or more PCMS devices. Other embodiments are also disclosed and claimed.

Abstract: A method, system and computer program product are provided for implementing ECC (Error Correction Codes) redundancy using reconfigurable logic blocks in a computer system. When a fail is detected when reading from memory, it is determined if the incorrect data is in the data or the ECC component of the data. When incorrect data is found in the ECC component of the data, and an actionable threshold is not reached, a predetermined Reliability, Availability, and Serviceability (RAS) action is taken. When the actionable threshold is reached with incorrect data identified in the ECC component of the data, an analysis process is performed to determine if the ECC logic is faulty. When a fail in the ECC logic is detected, the identified ECC failed logic is replaced with a spare block of logic.

Abstract: According to one embodiment of the present invention, a method for operating a three dimensional (“3D”) memory device includes detecting, by a memory controller, a first error on the 3D memory device and detecting, by the memory controller, a second error in a first chip in a first rank of the 3D memory device, wherein the first chip has an associated first chip select. The method also includes powering up a second chip in a second rank, sending a command from the memory controller to the 3D memory device to replace the first chip in the first chip select with the second chip and correcting the first error using an error control code.

Abstract: A method includes storing data that is encoded with an Error Correction Code (ECC) in a group of analog memory cells. The memory cells in the group are read using multiple sets of read thresholds. The memory cells in the group are divided into two or more subsets. N partial syndromes of the ECC are computed, each partial syndrome computed over readout results that were read using a respective set of the read thresholds from a respective subset of the memory cells. For each possible N-bit combination of N bit values at corresponding bit positions in the N partial syndromes, a respective count of the bit positions in which the combination occurs is determined, so as to produce a plurality of counts. An optimal set of read thresholds is calculated based on the counts, and data recovery is performed using the optimal read thresholds.

Abstract: A memory storage device, a memory controller thereof and a data transmission method thereof are provided. The memory storage device includes a rewritable non-volatile memory module having a first and a second memory dies, and the first and the second memory dies are coupled to the memory controller through the same data input/output bus. The method includes transmitting a read command to the first memory die and then transmitting a write command to the second memory die by the memory controller. The method further includes controlling the first and the second memory dies to respectively read out and put data onto the data input/output bus in accordance with the read command and write the data from the data input/output bus into the second memory die in accordance with the write command at the same time by the memory controller.

Abstract: A method includes, in a memory controller that controls a memory, receiving from a host a read command that specifies data to be retrieved from the memory and further specifies a target error performance to be achieved in retrieving the data. A data retrieval configuration is selected in the memory controller depending on the target error performance specified in the read command. The data is retrieved from the memory using the selected data retrieval configuration, and the retrieved data is output to the host.

Abstract: According to one embodiment, a semiconductor memory device includes semiconductor memory chips in which data requested to be written. The data has one or more pieces of first data in a predetermined unit. The device includes a write controller that writes the first data and redundancy information calculated by using a predetermined number of pieces of the first data and used for correcting an error in the predetermined number of pieces of the first data into different semiconductor memory chips; and a storage unit that stores identification information and region specifying information so as to be associated with each other. The identification information associates the first data and the redundancy information, and the region specifying information specifies a plurality of storage regions in the semiconductor memory chips to which the pieces of the first data and the redundancy information associated with each other are written.

Abstract: According to one embodiment, a semiconductor memory device includes semiconductor memory chips in which data requested to be written. The data has one or more pieces of first data in a predetermined unit. The device includes a write controller that writes the first data and redundancy information calculated by using a predetermined number of pieces of the first data and used for correcting an error in the predetermined number of pieces of the first data into different semiconductor memory chips; and a storage unit that stores identification information and region specifying information so as to be associated with each other. The identification information associates the first data and the redundancy information, and the region specifying information specifies a plurality of storage regions in the semiconductor memory chips to which the pieces of the first data and the redundancy information associated with each other are written.

Abstract: A method for controlling flash memory is described. The method includes selecting a new forward error correction (FEC) parameter set that provides more redundancy than a current FEC parameter set. The method also includes coding source information bits, using the new FEC parameter set, during write operations to a first corrupted page in the flash memory. The method further includes mapping the first corrupted page and at least one additional corrupted page in the flash memory to a single logical page with an expected page size.

Abstract: A controller for a Super Enhanced Endurance Device (SEED) or Solid-State Drive (SSD) increases flash endurance using a DRAM buffer. Host accesses to flash are intercepted by the controller and categorized as data types of paging files, temporary files, meta-data, and user data files, using address ranges and file extensions read from meta-data tables. Paging files and temporary files are optionally written to flash. Full-page and partial-page data are grouped into multi-page meta-pages by data type in the DRAM before storage by lower-level flash devices such as eMMC, UFS, or iSSD. Caches in the DRAM buffer for storing each data type are managed and flushed to the flash devices by the controller. Write dates are stored for pages or blocks for management functions. A spare/swap area in DRAM reduces flash wear. Reference voltages are adjusted when error correction fails.

Abstract: Embodiments of solid-state storage system are provided herein include data recovery mechanism to recover data upon detection of a read error (e.g., an uncorrectable ECC error) in a storage element such as a page. In various embodiments, the system is configured to determine optimal reference voltage value(s) by evaluating the reference voltage value(s) of page(s) that are related to the page where the failure occurred. The related page(a) may include a page that is paired with the initial page where the failure occurred (e.g., the paired pages reside in a common memory cell), or a neighboring page that is physically near the page where the initial page, and/or a paired page of the neighboring page. In another embodiment, the system is configured to perform a time-limited search function to attempt to determine optimal reference voltage values through an iterative process that adjusts voltage values in a progression to determine a set of values that can retrieve the data.

Abstract: A data storage system configured to perform prioritized memory scanning for memory errors is disclosed. In one embodiment, the data storage system prioritizes scanning for memory errors based on a quality attribute of pages or zones of a non-volatile memory array. Pages or zones having quality attributes that reflect a lower level of reliability or endurance than other pages or zones are scanned more frequently for memory errors. When memory errors are discovered, the quality attribute of pages or zones can be adjusted to reflect a lower level of reliability or endurance. In addition, stored data can be recovered before it may become permanently lost and before a host system reads the stored data. Improved performance of the data storage system is thereby attained.

Abstract: Disclosed herein is a nonvolatile memory including: a nonvolatile memory cell device including at least a nonvolatile memory cell array accessible in units of a word and further accessible at least with a fixed latency in a first access mode and with a variable latency in a second access mode; a first access path used in the first access mode; a second access path used in the second access mode; a first ECC processing part configured to be connected to the first access path and to perform error detection and correction using an ECC on the data output from the nonvolatile memory cell array in the first access mode; and a second ECC processing part configured to be connected to the second access path and to perform error detection and correction using the ECC on the data output from the nonvolatile memory cell array in the second access mode.

Abstract: A method may be performed at a data storage device that includes a memory and a controller. The method includes providing user data to a variable-bit error correction coding (ECC) encoder. The ECC encoder generates a first set of parity bits. A first number of parity bits in the first set of parity bits is determined based on stored counts of read errors. The method also includes storing the user data and the first set of parity bits to a memory of the data storage device.

Abstract: A method of controlling a nonvolatile semiconductor memory includes checking a first group at a first interval period, the first group including a plurality of blocks, and when a first block in the first group satisfies a first condition, assigning the first block to a second group. The method includes checking, at a second interval period, an error count of data stored in the second group, and when a second block in the second group satisfies a second condition, moving data stored in the second block to an erased block in which stored data is erased among the plurality of blocks.

Abstract: According to one embodiment, a semiconductor storage device includes a semiconductor memory which includes two or more cell peripheral circuits and two or more storage cells at least one of reading and writing of which is controlled by the cell peripheral circuits in each of the cell peripheral circuits. Further, the semiconductor storage device includes a memory control unit configured to instruct to form 1 symbol as a unit for creating an error correction code by the data held by the storage cells controlled by the same cell peripheral circuit and creating an error correction code to the symbol created base of the instruction.

Abstract: A controller for a nonvolatile memory includes an encoder and a decoder. The memory includes memory cells that each store data using more than two levels. The encoder generates first data for storage in first memory cells. For first and second subsets of cells of the first memory cells, the first data is stored at first and second levels, respectively. Measurable values of the first subset of cells are characterized by a first probability density function having a first width. Measurable values of the second subset of cells are characterized by a second probability density function having a second width. The first width is greater than the second width. The encoder generates the first data such that a size of the first subset of cells is less than a size of the second subset of cells. The decoder decodes encoded data from the memory.

Abstract: Method for encoding information in a flash memory block which combines an independent encoding of each page with a block-level code across multiple pages. The method includes two independent error correction codes, one in horizontal direction and one in vertical direction, with horizontal direction error correction decoding; and vertical direction erasure correction decoding.

Abstract: A nonvolatile memory device comprises a memory controller having a memory cell status estimator that generates status estimation information indicating the status of a memory cell based on status register data, a coupling group index selector configured to generate a select signal for selecting a page and coupling group index from the status estimation information, and a memory cell status value generator configured to map the status estimation information to the data reliability decision bits and the coupling group index and generate a status value of the memory cell for error correction code decoding.

Abstract: Systems, circuits, devices and/or methods related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing.

Abstract: A memory controller including a buffer configured to perform decoding frame-unit data decoded by an LDPC decoder through partial parallel processing based on a check matrix made up of a block of a unit matrix and a plurality of blocks in which each row of the unit matrix is sequentially shifted and store threshold decision information of the data read from a memory section, an LLR conversion section configured to convert the threshold decision information to an LLR, an LMEM configured to store probability information ? calculated during iteration processing that repeatedly performs column processing and row processing based on the LLR in an iteration unit equal to or smaller than a size of the block, and a CPU core configured to transfer the probability information ? stored in the LMEM to the buffer every time the iteration processing in the iteration unit is completed.

Abstract: Methods of operating nonvolatile memory devices include reading a first plurality of multi-bit nonvolatile memory cells in the nonvolatile memory device using a first plurality of read voltages to thereby generate first read data, and then rereading the first plurality of multi-bit nonvolatile memory cells using a second plurality of read voltages that differ, at least in part, from the first plurality of read voltages, to thereby generate second read data. An operation is then undertaken to perform first and second ECC decoding operations on the first and second read data, respectively, to thereby identify whether the first read data or the second read data more accurately reflects data stored in the first plurality of multi-bit nonvolatile memory cells during the reading and rereading.

Abstract: A data input method of a NAND flash memory includes: determining whether a size of a writing-requested data is less than a reference value; calculating an error correction code (ECC) for the data using a software ECC method when the data size is less than the reference value; and writing the data and the ECC to a data region of the NAND flash memory. A data output method of the NAND flash memory includes: determining whether a size of a reading-requested data is less than a reference value; reading the data and an error correction code (ECC) from the NAND flash memory; calculating an ECC for the read data using a software ECC method when the data size is less than the reference value; and performing an error detection and correction by comparing the calculated ECC and the read ECC.

Abstract: A nonvolatile memory storage controller for delivering log likelihood ratios (LLRs) to a low-density parity check (LDPC) decoder for use in the decoding of an LDPC encoded codeword. The controller includes partitioning circuitry for identifying a set of soft-decision reference voltages having the smallest calculated introduced error value based upon the estimated BER of the nonvolatile memory. The controller further includes read circuitry for reading an LDPC encoded codeword stored in a nonvolatile memory storage module using the set of soft-decision reference voltages having the smallest calculated LLR introduced error value to provide a plurality of soft-decision bits representative of the codeword. The controller further includes an LLR look-up table accessible by the read circuitry to provide LLRs to the LDPC decoder for the subsequent decoding of the codeword.

Abstract: The present disclosure includes methods, devices, and systems for object oriented memory in solid state devices. One embodiment of a method for object oriented memory in solid state devices includes accessing a defined set of data as a single object in an atomic operation manner, where the accessing is from a source other than a host. The embodiment also includes storing the defined set of data as the single object in a number of solid state memory blocks as formatted by a control component of a solid state device that includes the number of solid state memory blocks.

Abstract: An apparatus, system, and method are disclosed for managing data reliability. A priority module is configured to receive a storage request for a non-volatile memory device. The storage request may include data associated with a priority. The non-volatile memory device includes a plurality of cells, and each cell encodes a plurality of bits. The bits for a cell provide distinct levels of quality of service. A select module is configured to select a bit for storing the data based on the priority of the data and the level of quality of service of the selected bit. A data management module is configured to manage the data to satisfy a write order for the plurality of bits.

Abstract: The present invention discloses an error correction method applied to a memory device, wherein the memory device has a plurality of pages. The error correction method includes: sequentially retrieving data of a plurality of first sectors of a first page of the pages in response to a first read command; performing a first error correction by an error correction module during retrieval the data of the first page; producing a second read command when the data of the first sectors of the first page are all retrieved; and starting to sequentially retrieve data of a plurality of second sectors of a second page of the pages in response to the second read command after the data of the first sectors of the first page are all retrieved.

Abstract: A system and method reading, accumulating and processing soft information for use in LDPC decoding. In accordance with the present invention, an LDPC decoder includes accumulation circuitry to receive soft reads of a cell of the nonvolatile memory storage module and to produce an accumulated soft read that can be used to identify an appropriate LLR for the cell. The accumulation circuitry of the present invention may include, an accumulation RAM, an arithmetic logic unit (ALU) and a soft accumulation control and sequencing module for accumulating and processing soft information for use in LDPC decoding.

Abstract: A system and method for computing MLC flash memory cell programming parameters to dynamically adjust verify voltage levels is provided. The method may use an iterative guess and check process that will result in a distribution of states, specifically a cell voltage distribution (CVD) that minimizes the cell error rate in cells encoded in interleaved error correction code (ECC) mode, and that balances the bit error rate between pages in cells encoded in non-interleaved ECC mode.

Abstract: A method and apparatus for generating soft decision error correction code information. The method includes generating or creating a lookup table (LUT), such as a log likelihood ratio (LLR) lookup table, characterizing a flash memory device. The method also includes loading the lookup table into the SSD controller. The method also includes accessing the lookup table to assign LLR or other characteristic values to the cells of a flash memory device. The method also includes decoding the data in a flash memory device using the soft decision information provided by the lookup table and assigned to the appropriate cells of the flash memory device.

Abstract: Mass storage uses additional error correction codes. The additional codes can be stored in a storage medium (e.g., volatile solid state memory) separate from the associated data. The additional codes may be written to a nonvolatile medium. The additional codes may be transient. The additional codes may be cached. As long as present, the additional codes may be used to correct user data in synch with or in addition to other error detection and correction codes.

Abstract: A data write method of a nonvolatile memory device is provided which includes receiving write data to be stored in selected memory cells; reading data stored in the selected memory cells; processing the write data according to a plurality of data modulation manners to generate a plurality of modulated data values; calculating the number of flip bits and the number of switching bits when the write data and the plurality of modulated data values are overwritten on the selected memory cells, each flip bit indicating that a logical value of a selected memory cell is reversed and each switching bit indicating that a logical value of a selected memory cell is switched from a first logical value to a second logical value; and selecting one of the write data and the plurality of modulated data values according to calculating the number of flip bits and the number of switching bits.

Abstract: A method of processing data using a memory controller includes determining at least one cell state to which each of a plurality of multi-level cells can be changed to based on a current cell state of each multi-level cell, where each multi-level cell includes a plurality of data pages; determining one of the data pages as having a stuck bit when a value of the data page has a single mapping value based on mapping values mapped to the at least one cell state and generating stuck bit data regarding the stuck bit; and encoding write data to be stored in the multi-level cells based on the stuck bit data.

Abstract: A memory system includes a flash subsystem for storing data identified by page numbers. The memory system further includes a central processing unit (CPU), and a flash controller coupled to the CPU, the CPU being operable to pair a lower with an upper page. Further included in the memory system is a buffer including a page of data to be programmed in a block of the flash subsystem, wherein split segments of pages are formed and concatenated with split error correcting code (ECC), the ECC having a code rate associated therewith.

Abstract: Semiconductor memory devices are provided that include a nonvolatile memory that has a plurality of memory cells and a memory controller that is configured to control at least some of the operations of the nonvolatile memory. The memory controller include an error correction unit. Moreover, the memory controller is configured to determine whether a read failure that occurs during a read operation of a first of the plurality of memory cells is due to charge leakage based at least in part on an output of the error correction unit. Related methods are also disclosed.

Abstract: An SSD controller maintains a zero count and a one count, and/or in some embodiments a zero/one disparity count, for each read unit read from an SLC NVM (or the lower pages of an MLC). In an event that the read unit is uncorrectable in part due to a shift in the threshold voltage distributions away from their nominal distributions, the maintained counts enable a determination of a direction and/or a magnitude to adjust a read threshold to track the threshold voltage shift and restore the read data zero/one balance. In various embodiments, the adjusted read threshold is determined in a variety of described ways (counts, percentages) that are based on a number of described factors (determined threshold voltage distributions, known stored values, past NVM operating events). Extensions of the forgoing techniques are described for MLC memories.

Abstract: A method for encoding a data word for writing an encoded data word in N cells of a solid state memory. Each of the N cells can be programmed in one of q nominal levels. The method includes encoding the data word as a codeword of a first codeword type having q symbol values or as a codeword of a second codeword type having (q-d) symbol values, d ? [1, . . . , q?1], depending on a state of the N cells.

Abstract: Storage of digital data in non-volatile media such as NAND FLASH needs to take account of the errors in data retrieved from the memory. The error rate tends to increase with the number of write/erase cycles of a cell of memory and with the time that the data has been stored. To achieve a very low uncorrected bit error rate (UBER) a substantial amount of redundancy data needs to be stored for error correction purposes. A method and apparatus is disclosed where a first redundancy data is represented by a second redundancy data computed from the first redundancy data. The first redundancy data may not be stored and is reconstructed from the stored data using a same generation procedure as previously used. The reconstructed estimate of the first redundancy data is corrected by the second redundancy data, and is used to correct the underlying data.

Abstract: A method for data storage includes, in a memory that includes multiple memory blocks, specifying at a first time a first over-provisioning overhead, and storing data in the memory while retaining in the memory blocks memory areas, which do not hold valid data and whose aggregated size is at least commensurate with the specified first over-provisioning overhead. Portions of the data from one or more previously-programmed memory blocks containing one or more of the retained memory areas are compacted. At a second time subsequent to the first time, a second over-provisioning overhead, different from the first over-provisioning overhead, is specified, and data storage and data portion compaction is continued while complying with the second over-provisioning overhead.

Abstract: A memory controller includes a memory access circuit and an LDPC decoding circuit. The memory access circuit reads the hard information of a first code word and a second code word from a memory device. The LDPC decoding circuit decodes the first code word according to the hard information of the first code word. When the LDPC decoding circuit does not decode the first code word successfully, the LDPC decoding circuit configures the memory access circuit to read the soft information of the first code word and the second code word, and decodes the first code word and the second code word according to the soft information of the first code word and the second code word.

Abstract: Techniques associated with a read and write window budget for a two level memory (2LM) system may include establishing a read and write window budget for the 2LM system that includes a first level memory and a second level memory. The established read and write window budget may include a combination of a first set of memory addresses and a second set of memory addresses of the second level of memory. The first set of memory addresses may be associated with non-volatile memory cells having wider cell threshold voltage distributions compared to cell threshold voltage distributions for non-volatile memory cells associated with the second set of memory addresses. According to some examples, the established read and write window budget may be part of a strategy to meet both a completion time threshold for a given amount of memory and an acceptable error rate threshold for the given amount of memory when fulfilling read or write requests to the second level memory.

Abstract: A DRAM memory device includes several banks of memory cells each of which are divided into first and second sets of memory cells. The memory cells in the first set can be refreshed at a relatively slow rate to reduce the power consumed by the DRAM device. Error checking and correcting circuitry in the DRAM device corrects any data retention errors in the first set of memory cells caused by the relatively slow refresh rate. The memory cells in the second set are refreshed at a normal rate, which is fast enough that data retention errors do not occur. A mode register in the DRAM device may be programmed to select the size of the second set of memory cells.

Abstract: The device for testing a memory of an electric tool has a control unit, a testing module, a buffer memory and an address translator. The control unit is coupled to the memory and configured to control the electric tool. The testing module is coupled to the memory and configured to test a specific memory cell from among a plurality of memory cells of the memory. The buffer memory is configured to provide temporary storage of the data that is stored in the specific memory cell during the testing of the specific memory cell. The address translator is configured to translate the address of the specific memory cell to the address of the buffer memory during the testing of the specific memory cell. A tool and method are also provided.

Abstract: The embodiments described herein provide a controller and method for interfacing between a host controller in a host and a flash memory device. In one embodiment, a controller comprises a first NAND interface, a second NAND interface, and one or more of the following modules: a data scrambling module, a column replacement module, and a module that manages at least one of had blocks and spare blocks. Other embodiments are disclosed, and each of the embodiments can be used alone or together in combination.

Abstract: Provided is a memory system and wear-leveling method. A memory system includes a flash memory device and a memory controller. The flash memory device includes a plurality of memory blocks, each including a plurality of memory cells. The memory controller is configured to control the flash memory device based on erase event information and error checking and correction (ECC) event information of each of the memory blocks such that use of the memory blocks is distributed more uniformly.

Abstract: A memory circuit is described comprising a plurality of memory elements, wherein each memory element is configured to store one data element of a plurality of data elements, an error correction information memory configured to store joint error correction information of the plurality of data elements, for each memory element, an error detection information memory storing error detection information for the data element stored in the memory element and a memory access circuit configured to, for an access to a memory element of the plurality of memory elements, check whether the error detection information for the data element stored in the memory element indicates an error of the data element stored in the memory element and, depending on whether the error detection information for the data element stored in the memory element indicates an error of the data element stored in the memory element, to process the error correction information for the access.

Abstract: A data storage device may generally be constructed and operated with at least a controller configured to identify a variance from a predetermined threshold in at least one variable resistance memory cell and upgrade a first error correction code (ECC) level to a second ECC level for the at least one variable resistance memory cell.

Abstract: A method for data storage includes accepting data for storage in a memory that includes multiple analog memory cells and supports a set of built-in programming commands. Each of the programming commands programs a respective page, selected from a group of N pages, in a subset of the memory cells. The subset of the memory cells is programmed to store M pages of the data, M>N, by performing a sequence of the programming commands drawn only from the set.

Abstract: A storage system that includes multiple nodes, each node comprises a SSD cache and a management module and hard disk drives that are coupled to the nodes. The management module of each node is arranged to manage a SSD cache map that comprises multiple entries for storing mappings from logical addresses to SSD cache physical addresses and to physical addresses in the hard disk drives. The mappings are related to data units stored in the SSD cache. Upon a rejoin of a certain node following a shut-down or a failure of the certain node, the certain node is arranged to: obtain from at least one other node, current mappings between logical addresses and physical addresses in the hard disk drives, and perform a validation process of the data units stored in the SSD cache in response to relationships between the current mappings and the entries of the SSD cache map.