Abstract: A method for operating an MS decoder and an associated memory system utilizing the MS decoder. The method determines an operation mode of the MS decoder. For each variable node, the method calculates a variable to check node V2C message. The method stores, in a check node unit CNU memory, check information associated with the calculated V2C message according to the operation mode. The check information includes full information when the operation mode is a high precision mode, and partial information when the operation mode is a low precision mode.

Abstract: An LDPC encoding method and a system for error code detection. In the method and system, partial syndromes using a user portion and a low density parity check matrix are calculated, a parity portion of a codeword is calculated using the partial syndromes and using a quasi-cyclic matrix, the parity portion is generated by segment processing of the quasi-cyclic matrix, and the user portion and the parity portion are concatenated to complete the codeword.

Abstract: A controller optimizes read threshold values for a memory device using domain transformation. The controller determines, for decoded data of each read operation, an asymmetric ratio (AR) and a number of unsatisfied checks (USCs), the AR indicating a ratio of a number of a first binary value to a number of a second binary value in the decoded data. The controller determines a Z-axis such that AR values of threshold sets are arranged in a set order along the Z-axis. The controller determines an optimum read threshold set using coordinate values on the Z-axis, which correspond to a set AR value and a set USC value.

Abstract: A system and method for regenerative satellite communications between a gateway of a terrestrial communication network and a user terminal via a communications satellite are described. The system includes a distributed regenerative modulator having a first portion of modulator components arranged at the gateway, and a second portion of modulator components arranged at the communications satellite. The first portion of the modulator components applies a first part of modulation functions to the information data carried by an uplink signal at the gateway, while the second portion of the modulator components applies a second part of modulation functions to the information data at the satellite to generate a down-link signal for transmitting it to the user terminal. The first portion of the components performs specific signal processing operations, which are only suitable for processing a waveform of a specific type.

Abstract: Apparatus, methods, and computer program products for decoding are provided. An example method may include receiving a communication from a second network entity via a channel, where the communication is encoded based on multi-level coding associated with at least a first coding level and a second coding level, and where the first coding level is associated with a first set of bits and the second coding level is associated with a second set of bits. The example method may further include means for generating a first estimate of a first LLR associated with the first coding level, a second estimate of a second LLR associated with the second coding level, and auxiliary information including a third estimate of a third LLR based on the first set of bits and the second set of bits.

Abstract: This application relates to the field of communication technologies, and discloses a polar coding/decoding method and apparatus, to improve sequence lookup efficiency. The method includes: obtaining a first sequence from a polar code construction sequence table based on a coding parameter, where the polar code construction sequence table includes at least one coding parameter and at least one sequence corresponding to the at least one coding parameter, the coding parameter is mapped to the sequence in a one-to-one manner, the first sequence is one of the at least one sequence; and selecting serial numbers of K polarized channels from the first sequence based on a rate matching scheme and/or a reliability order, placing to-be-coded bits based on the selected serial numbers of the K polarized channels, and performing polar coding, to obtain a coded bit sequence.

Abstract: Disclosed are a method and an apparatus for fast decoding a linear code based on soft decision. The method may comprise sorting received signals in a magnitude order to obtain sorted signals; obtaining hard decision signals by performing hard decision on the sorted signals; obtaining upper signals corresponding to MRBs from the hard decision signals; obtaining a permuted and corrected codeword candidate using the upper signals and an error vector according to a current order; calculating a cost for the current order using a cost function; determining the permuted and corrected codeword candidate as a permuted and corrected codeword according to a result of comparing the calculated cost with a minimum cost; and determining a predefined speeding condition.

Abstract: An apparatus for data storage includes an interface and a processor. The interface is configured to communicate with a memory device that includes (i) a plurality of memory cells and (ii) a data compression module. The processor is configured to determine a maximal number of errors that are required to be corrected by applying a soft decoding scheme to data retrieved from the memory cells, and based on the maximal number of errors, to determine an interval between multiple read thresholds for reading Code Words (CWs) stored in the memory cells for processing by the soft decoding scheme, so as to meet following conditions: (i) the soft decoding scheme achieves a specified decoding capability requirement, and (ii) a compression rate of the compression module when applied to confidence levels corresponding to readouts of the CWs, achieves a specified readout throughput requirement.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 10/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.

Abstract: Disclosed are methods, systems and devices for decoding data read from a memory device, including receiving noisy data from a first memory location included in a word line zone of the memory device, identifying the word line zone and a prior successful decoder parameter associated with the word line zone, decoding the noisy data using the prior successful decoder parameter used in a prior successful decoding with respect to a second memory location included in the same word line zone, determining whether the decoding based on the prior successful decoder parameter has succeeded, maintaining, upon a determination that the decoding has succeeded, the prior successful decoder parameter as a decoder parameter for the first memory location, and decoding, upon a determination that the decoding operation has failed, the noisy data read from the first memory location by using another decoder parameter selected from a set of predefined decoder parameters.

Abstract: Methods and apparatus for decoding LDPC code provide that an LDPC code may be represented as a Tanner graph comprising bit nodes and check nodes and connections between them. A configurable LDPC decoder supporting many different LDPC codes having any sub-matrix size includes several independently addressable memories which are used to store soft decision data for each bit node. The decoder further includes a number P of check node processing systems which generate updated soft decision data. The updated values are then passed back to the memories via a shuffling system. If the number of check nodes processed in parallel by the check node processing systems is PCNB (where P?PCNB) and the soft decision data for a bit node is of word size q bits, the total width of the independently addressable memories is larger than PCNB*q bits.

Abstract: Systems and methods related to encoding metadata or other status information into error correcting code (ECC) for a data block. In one embodiment, an encoder of a memory controller generates ECC check bits based on a data block and virtual bits representing metadata, then stores the ECC check bits and the data block as a code word. Subsequently, multiple decoders of the memory controller process candidate code words that include the code word and candidate virtual bit values to detect errors in the candidate code words. The decoders output signals identifying each candidate code word as having no error, a correctable error, or an uncorrectable error and outputs a calculated error location in the case of a correctable error. The system determines the actual value of the virtual bits based on the outputs of the decoders and corrects any identified correctable error in the recovered code word.

Abstract: Methods, systems, and devices for wireless communications are described. A first device may identify that a first set of transmission resources in a transmission time interval (TTI) has a higher priority at a second device than a second set of transmission resources in the TTI. The first device may identify that a message is to be transmitted from the first device to the second device via the TTI and process the message into a bit sequence based on the identification of the second set of transmission resources in the TTI, where the processing increases a likelihood that systematic bits of the message are received at the second device despite presence of the second set of transmission resources in the TTI. The first device may transmit the bit sequence to the second device via the TTI.

Abstract: A method of decoding a polar coded signal includes determining channel reliabilities for a plurality of polar coded bit channels in a data communication system including a plurality of frozen bit channels and non-frozen bit channels, selecting a frozen bit channel, calculating a likelihood value for a bit estimate associated with the frozen bit channel, generating a hard decision value for the bit estimate in response to the likelihood value, comparing the hard decision value for the bit estimate to a known value of a frozen bit transmitted on the frozen bit channel, in response to determining that the hard decision value for the bit estimate differs from the known value of the frozen bit transmitted on the frozen bit channel, updating an accumulated uncertainty, comparing the accumulated uncertainty to a threshold, and determining that a decoding error has occurred in response to the comparison.

Abstract: A saturation metric that represents a degree of saturation in a low-density parity-check (LDPC) decoding system that uses a fixed-point number representation is determined. The saturation metric is compared against a saturation threshold. In the event the saturation metric exceeds the saturation threshold, at the end of a decoding iteration, a message is more aggressively attenuated compared to when the saturation metric does not exceed the saturation threshold in order to produce an attenuated message. In the event the saturation metric does not exceed the saturation threshold, at the end of the decoding iteration, the message is less aggressively attenuated compared to when the saturation metric does exceed the saturation threshold in order to produce the attenuated message.

Abstract: An error check code (ECC) decoder includes a buffer, a data converter and a decoding circuit. The buffer stores a plurality of read pages read from a plurality of multi-level cells connected to a same wordline. The data converter adjusts reliability parameters of read bits of the plurality of read pages based on state-bit mapping information and the plurality of read pages to generate a plurality of ECC input data respectively corresponding to the plurality of read pages. The state-bit mapping information indicate mapping relationships between states and bits stored in the plurality of multi-level cells. The decoding circuit performs an ECC decoding operation with respect to the plurality of read pages based on the plurality of ECC input data. An error correction probability is increased by adjusting the reliability parameters of read bits based on the state-bit mapping information.

Abstract: Low-density parity-check (LDPC) encoded data with one or more errors and information associated with an early convergence checkpoint are received. The information associated with the early convergence checkpoint is used to perform LDPC decoding on the LDPC encoded data up to the early convergence checkpoint and generate a decoded codeword where the early convergence checkpoint is prior to a first complete iteration of the LDPC decoding. It is determined whether the LDPC decoding is successful and in the event it is determined that the LDPC decoding is successful, the decoded codeword is output.

Abstract: Systems, memory controllers, decoders and methods perform decoding by exploiting differences among word lines for which soft decoding fails (failed word lines). Such decoding generates extrinsic information for codewords of failed word lines based on the soft decoding. The soft information obtained during the soft decoding is updated based on the extrinsic information, and the updated soft information is propagated across failed word lines. Low-density parity-check (LDPC) decoding of codewords of failed word lines is performed with the updated soft information.

Abstract: A syndrome-based decoding method and apparatus for a block turbo code are disclosed. An embodiment of the present invention provides a syndrome-based decoding method for a block turbo code that includes an extended Hamming code as a component code, where the decoding method includes: (a) generating an input information value for a next half iteration by using channel passage information and the extrinsic information and reliability factor of a previous half iteration; (b) generating a hard decision word by way of a hard decision of the input information value; (c) calculating an n number of 1-bit syndromes, which corresponds to the number of columns or rows of the block turbo code, by using the hard decision word; and (d) determining whether or not to proceed with the next half iteration by using the calculated n number of 1-bit syndromes.

Abstract: The present invention provides an electronic device, wherein the electronic device includes a flash memory module and a flash memory controller. The flash memory module includes at least one flash memory chip, each flash memory chip includes a plurality of blocks, and each block includes a plurality of pages, and the flash memory controller is configured to access the flash memory module. In the operations of the electronic device, when the flash memory controller sends a read command to the flash memory module to ask for data on at least one page, the flash memory module uses a plurality of read voltages to read each memory cell of the at least one page to obtain multi-bit information of each memory cell, and the flash memory module transmits the multi-bit information of each memory cell of the at least one page to the flash memory controller.

Abstract: Techniques are provided for proof-of-work based on runtime compilation. Key generation code is partitioned into a set of code blocks. The key generation code generates an expected key value when compiled and executed. A shuffled set of code blocks is generated by reordering the set of code blocks. A client computing device is provided the shuffled set of code blocks and problem-solving code that, when executed at the client computing device, reconstructs the key generation code to generate a submission value by performing one or more compiling iterations. Each compiling iteration comprising reordering the shuffled set of code blocks to generate test code, and attempting to compile and execute the test code to generate the submission value. It is determined that the client computing device fully executed the problem-solving code based on the verifying the submission value.

Abstract: An error management system for a data storage device can generate soft-decision log-likelihood ratios (LLRs) using multiple reads of memory locations. 0-to-1 and 1-to-0 bit flip count data provided by multiple reads of reference memory locations can be used to generate probability data that is used to generate possible LLR values for decoding target pages. Possible LLR values are stored in one or more look-up tables.

Abstract: Systems, memory controllers, decoders and methods perform decoding by exploiting differences among word lines for which soft decoding fails (failed word lines). Such decoding generates extrinsic information for codewords of failed word lines based on the soft decoding. The soft information obtained during the soft decoding is updated based on the extrinsic information, and the updated soft information is propagated across failed word lines. Low-density parity-check (LDDC) decoding of codewords of failed word lines is performed with the updated soft information.

Abstract: Techniques are described for joint encoding and decoding of information symbols. In one embodiment, a method for joint encoding includes, in part, obtaining a sequence of information symbols, generating a plurality of cyclic codewords each corresponding to a portion of the sequence of information symbols, jointly encoding the plurality of cyclic codewords to generate at least one combined codeword, and providing the combined codeword to a device. The at least one combined codeword may be generated through Galois Fourier Transform (GFT).

Abstract: According to certain embodiments, a method is provided for generating soft information for code bits of polar codes. The method includes receiving, by a decoder of a receiver, soft information associated with coded bits from a first module of the receiver and using a tree structure of the polar code to generate updated soft information. The updated soft information is output by the decoder for use by a second module of the receiver.

Abstract: An encoding method for a memory storage apparatus adopting an ECC algorithm is provided. The memory storage apparatus comprises an ECC encoder. The encoding method includes: receiving a write command comprising a write address and a write data; reading an existing codeword; attaching a flip bit to the write data; encoding the write data and the flip bit to generate parity bits based on the ECC algorithm by the ECC encoder and attaching the write data and the flip bit to the plurality of parity bits to generate a new codeword; flipping the new codeword based on a number of bits among selected bits required to be changed from the existing codeword to the new codeword; and writing one of the new codeword and the flipped new codeword to the write address. In addition, a memory storage apparatus using the encoding method is provided.

Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

Abstract: A method for punctured bit estimation includes receiving a punctured codeword. The method further includes generating a reconstructed codeword using the punctured codeword and at least one punctured bit having a default logic value. The method further includes generating a syndrome vector for the reconstructed codeword. The method further includes determining, using the syndrome vector, a number of unsatisfied parity-checks for the at least one punctured bit. The method further includes determining, for the at least one punctured bit, a bit value using, at least, the number of unsatisfied parity-checks associated with the at least one punctured bit.

Abstract: Methods and apparatus for decoding LDPC code provide that an LDPC code may be represented as a Tanner graph comprising bit nodes and check nodes and connections between them. A configurable LDPC decoder supporting many different LDPC codes having any sub-matrix size includes several independently addressable memories which are used to store soft decision data for each bit node. The decoder further includes a number P of check node processing systems which generate updated soft decision data. The updated values are then passed back to the memories via a shuffling system. If the number of check nodes processed in parallel by the check node processing systems is PCNB (where P?PCNB) and the soft decision data for a bit node is of word size q bits, the total width of the independently addressable memories is larger than PCNB*q bits.

Abstract: Techniques and mechanisms for determining information which is to be used for performing bit error correction. In an embodiment, bit reliability information is calculated based on a first likelihood function, and also on data signals which each indicate a respective bit of a codeword. Values of the bit reliability information each indicate, for a respective bit of the codeword, a confidence that the bit is at a particular logic state. A syndrome vector is calculated based on the bit reliability information, and one of the first likelihood function or a second likelihood function is selected based on one or more bit errors which are indicated by the syndrome vector. The selected one of the first likelihood function or the second likelihood function is used to correct bit errors of the codeword. In another embodiment, the first likelihood function is a default likelihood function to be used for initial syndrome vector calculations.

Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

Abstract: A method and an apparatus for carrying identification information are disclosed, to extend a quantity of bit positions that can represent identification information. The method includes determining, by a base station, bit locations that can be used to carry identification information in to-be-coded bits, where the bit locations that can be used to carry the identification information include locations of fixed bits, the identification information is used to identify a terminal, and the fixed bits are used by the terminal to perform error correction in a decoding process, adding, by the base station, the identification information to the bit locations, and encoding, by the base station in a polar code encoding mode, the to-be-coded bits that carry the identification information, and sending an encoded polar code to the terminal.

Abstract: Techniques are described for wireless communication. One method includes identifying a set of punctured bit locations in a received codeword. The received codeword is encoded using a polar code. The method also includes identifying a set of information bit locations of the polar code, with the set of information bit locations being determined based at least in part on polarization weights per polarized bit-channel of a polar code decoder that are a function of nulled repetition operations per polarization stage of the polar code identified based at least in part on the set of punctured bit locations. The method further includes processing the received codeword using the polar code decoder to obtain an information bit vector at the set of information bit locations.

Abstract: Methods and systems are provided for decoding LDPC codewords or blocks of codewords using a second set of parameters if decoding the codewords or blocks of codewords fails using a first set of parameters. An LDPC codeword may be decoded using a first decoding technique to produce a first decoding output using a first parameter. The first parameter may be altered to generate a second parameter to be used in a second decoding technique. The LDPC codeword may be decoded using the second decoding technique to produce a second decoding output. A syndrome weight of the first decoding output may be compared to a syndrome weight of the second decoding output and one of the first decoding output or the second decoding output may be selected based on which of the first decoding output or the second decoding output has a lower error.

Abstract: Various aspects described herein relate to techniques for rate matching and interleaving in wireless communications (e.g., 5G NR). In an example, a method described herein includes encoding one or more information bits to generate a first codeblock, rate matching the first codeblock to generate a second codeblock, segmenting, using bit distribution, the second codeblock into one or more sub-blocks each having a plurality of bits. The method further includes interleaving the plurality of bits on each of the one or more sub-blocks, concatenating, using bit collection, the one or more sub-blocks to generate a third codeblock in response to the interleaving, and transmitting a signal using the third codeblock.

Abstract: Certain aspects of the present disclosure generally relate to methods and apparatus for decoding low density parity check (LDPC) codes, and more particularly to a deeply-pipelined layered LDPC decoder architecture for high decoding throughputs. Accordingly, aspects of the present disclosure provide techniques for reducing delays in a processing pipeline by, in some cases, relaxing a dependency between updating bit log likelihood ratios (LLRs) and computing a posteriori LLRs.

Abstract: A method and apparatus for encoding low-density parity check codes uses parity check matrices composed of circulant blocks. The apparatus operates on a parity check matrix of a judiciously designed block structure, which permits low cost hardware implementation, and high encoding throughput.

Abstract: A method of correcting one or more bit errors in a memory device includes retrieving a codeword from a memory device. The codeword includes a data and an error correcting code. The method further includes determining whether the one or more bit errors are present in the retrieved codeword and correcting the retrieved codeword for the one bit error in response to determining one bit error is present in the retrieved codeword. The method also includes flipping a bit of the retrieved codeword in response to determining a plurality of bit errors is present in the retrieved codeword and correcting the retrieved codeword for the plurality of bit errors based on the bit-flipped codeword.

Abstract: A multi-iteration method for compressing a deep neural network into a sparse neural network without degrading the accuracy is disclosed herein. In an example, the method includes determining a respective initial compression ratio for each of a plurality of matrices characterizing the weights between the neurons of the neural network, compressing each of the plurality of matrices based on the respective initial compression ratio, so as to obtain a compressed neural network, and fine-tuning the compressed neural network.

Abstract: A method for decoding a (n, k, d) cyclic code is disclosed. The method includes: receiving a word corresponding to the cyclic code; constructing a look-up table, wherein the look-up table includes k syndrome vectors and k error patterns; computing a syndrome vector of the received word by a hardware processor; comparing the weight of the syndrome vector of the received word with an error-correcting capacity; decoding the received word by adding the received word and the syndrome vector if the weight of the syndrome vector of the received word is not more than the error-correcting capacity; decoding the received word by inverting bits in the message section in sequence and re-compute a syndrome vector of the inverted received word if the weight of the syndrome vector of the received word is more than the error-correcting capacity.

Abstract: A transmitter of a communications system includes a first encoder configured to apply a shaping operation to a data signal to generate a shaped data signal, a second encoder configured to encode the shaped data signal according to a forward error correction (FEC) scheme to generate an encoded signal, and a constellation mapper configured to modulate the encoded signal to symbol values according to a modulation scheme to generate a corresponding symbol stream for transmission through the communications system. The shaping operation reduces average constellation energy for constellations of the modulation scheme.

Abstract: A semiconductor device includes a controller and a memory device. The controller includes a processor configured to process a request from an external apparatus, an interface configured to receive the request and data from the external apparatus and an ECC encoder configured to generate, in response to the request, a data block matrix including a plurality of data block groups and a plurality of parity blocks that are generated based on the received data, and to generate encoded data by adding parity information to the data block matrix, the encoded data being transmitted to the memory device.

Abstract: A memory system, a controller including a bit-flipping (BF) decoder and a min-sum (MS) decoder that may be included in the memory system and operating methods thereof in which the controller determines a quality metric as a function of initial syndrome weight and information of the BF decoder after a set number of decoding iterations by the BF decoder in a test period. After the test period, the controller applies the quality metric to each codeword to determine whether to send that codeword first to the BF decoder for decoding or directly to the MS decoder for decoding.

Abstract: Devices and methods for decoding a signal encoded using an error correcting code are provided. For example, a check node processing unit is provided for a decoder to receive at least two input messages and to generate at least one output message, each message comprising a plurality of components. The check node processing unit comprises a data structure configured to store the input messages, the components of the input messages being associated with an integer index. The check node processing unit also comprises a data processing unit configured to apply one or more iterations of a transformation operation to at least a part of the data structure depending on at least some of the components of the input messages associated with a given value of the integer index, which provides a transformed data structure. The check node processing unit further comprises a calculation unit configured to determine at least one output message from the transformed data structure.

Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

Abstract: The present invention concerns a method and device for demodulating received symbols using a turbo-demodulation scheme comprising an iterative channel equalization and wherein an iterative channel decoder is used in the turbo-demodulation scheme, characterized in that the iterative channel decoder performs a first iterative process named iterative decoding process, the turbo-demodulation performing a second iterative process named iterative demodulation and decoding process, at each iteration of the second iterative process, the iterative channel decoder executing plural iterations in order to decode bits from which symbols are derived from. The iterative channel decoder: —memorizes at the end of the iterations of the first iterative process, the variables used internally by the iterative channel decoder, —reads the memorized variables at the following iteration of the second iterative process.

Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

Abstract: A transmitter apparatus in a wireless communication system that includes a processor. In one embodiment, the processor is configured to receive at least one modulated data message and spread the at least one modulated data message into a transmission signal using a low density signature matrix. The low density signature matrix is a cycle-free signature matrix. A receiver apparatus is configured to receive the transmission signal and detect within the received transmission signal at least one modulated data message. The processor is configured to detect the at least one modulated data message in one iteration using the cycle-free signature matrix.

Abstract: Performing soft error correction includes receiving a word at a soft correction engine capable of operating in more than one correction mode, identifying soft bit positions within the word, and automatically generating a number of possible results for the received word using combinations of the soft bit positions and more than one correction mode. The soft correction engine may include a Golay engine.