Using Symbol Reliability Information (e.g., Soft Decision) Patents (Class 714/780)
  • Patent number: 10637510
    Abstract: Devices and methods for decoding a signal encoded using an error correcting code are provided. For example, a check node processing unit is provided for a decoder to receive at least two input messages and to generate at least one output message, each message comprising a plurality of components. The check node processing unit comprises a data structure configured to store the input messages, the components of the input messages being associated with an integer index. The check node processing unit also comprises a data processing unit configured to apply one or more iterations of a transformation operation to at least a part of the data structure depending on at least some of the components of the input messages associated with a given value of the integer index, which provides a transformed data structure. The check node processing unit further comprises a calculation unit configured to determine at least one output message from the transformed data structure.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: April 28, 2020
    Assignee: UNIVERSITE DE BRETAGNE SUD
    Inventors: Cédric Marchand, Emmanuel Boutillon
  • Patent number: 10630318
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: April 21, 2020
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Heung-Mook Kim, Sun-Hyoung Kwon, Nam-Ho Hur
  • Patent number: 10511410
    Abstract: The present invention concerns a method and device for demodulating received symbols using a turbo-demodulation scheme comprising an iterative channel equalization and wherein an iterative channel decoder is used in the turbo-demodulation scheme, characterized in that the iterative channel decoder performs a first iterative process named iterative decoding process, the turbo-demodulation performing a second iterative process named iterative demodulation and decoding process, at each iteration of the second iterative process, the iterative channel decoder executing plural iterations in order to decode bits from which symbols are derived from. The iterative channel decoder: —memorizes at the end of the iterations of the first iterative process, the variables used internally by the iterative channel decoder, —reads the memorized variables at the following iteration of the second iterative process.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: December 17, 2019
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Damien Castelain
  • Patent number: 10432226
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: October 1, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Heung-Mook Kim, Sun-Hyoung Kwon, Nam-Ho Hur
  • Patent number: 10425105
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: September 24, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Heung-Mook Kim, Sun-Hyoung Kwon, Nam-Ho Hur
  • Patent number: 10411754
    Abstract: A transmitter apparatus in a wireless communication system that includes a processor. In one embodiment, the processor is configured to receive at least one modulated data message and spread the at least one modulated data message into a transmission signal using a low density signature matrix. The low density signature matrix is a cycle-free signature matrix. A receiver apparatus is configured to receive the transmission signal and detect within the received transmission signal at least one modulated data message. The processor is configured to detect the at least one modulated data message in one iteration using the cycle-free signature matrix.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: September 10, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Anahid Robert Safavi, Alberto Giuseppe Perotti, Branislav M. Popovic
  • Patent number: 10355718
    Abstract: Performing soft error correction includes receiving a word at a soft correction engine capable of operating in more than one correction mode, identifying soft bit positions within the word, and automatically generating a number of possible results for the received word using combinations of the soft bit positions and more than one correction mode. The soft correction engine may include a Golay engine.
    Type: Grant
    Filed: July 1, 2008
    Date of Patent: July 16, 2019
    Assignee: Adaptive Networks, Inc.
    Inventors: Michael B. Propp, John Jakson
  • Patent number: 10291356
    Abstract: The disclosure relates to a method for decoding a transport block encoded with multiple codeblock segments. User equipment determines whether to decode one of a transport block cyclic redundancy check (CRC) and a codeblock segment CRC based on a speed of user equipment. In response to the speed of the user equipment being greater than a threshold, the user equipment decodes the transport block CRC and generates an acknowledgement (ACK)/non-acknowledgement (NAK). In response to the speed of the UE being less than or equal to the threshold, during a first data transmission, the user equipment decodes the codeblock segment CRC for each of the multiple codeblock segments and generates the ACK/NAK. During a second and latter data transmissions, the user equipment decodes the codeblock segment CRC for each of the multiple codeblock segments that failed in the first data transmission and generates the ACK/NAK.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: May 14, 2019
    Assignee: Futurewei Technologies, Inc.
    Inventors: SaiRamesh Nammi, Xiao-Feng Qi
  • Patent number: 10270474
    Abstract: A partial concatenated coding system using an algebraic code and LDPC code is disclosed. The partial concatenated coding system includes an ECC encoder, a received codeword monitoring module and an ECC decoder. The ECC encoder has a LDPC code encoding module and an algebraic code encoding module. The ECC decoder has a LDPC code decoding module and an algebraic code decoding module. Comparing with conventional concatenating coding systems, the present invention has advantages of less spare spaces, better error-correcting performance, lower hardware complexity, better decoding throughput and fixable code length.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: April 23, 2019
    Assignee: STORART TECHNOLOGY(SHENZHEN) CO., LTD.
    Inventors: Pei-Yu Shih, Tsung-Yu Wu
  • Patent number: 10263640
    Abstract: Method and apparatus for decoding data. In some embodiments, an LDPC decoder has a variable node circuit (VNC) with a plurality of variable nodes configured to store bit reliability values of m-bit code bits. A check node circuit (CNC) has a plurality of check nodes configured to perform parity check operations upon n-bit messages from the VNC. Each n-bit message is formed from a combination of the bit reliability values and stored messages from the check nodes. A pre-saturation compensation circuit is configured to maintain a magnitude of each n-bit message received by the CNC below a saturation limit comprising the maximum value that can be expressed using p bits, with p less than n and each of the n-bit messages received by the CNC having a different magnitude. The pre-saturation compensation circuit may apply different scaling and/or bias factors to the n-bit messages over different decoding iterations.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: April 16, 2019
    Assignee: Seagate Technology LLC
    Inventors: Ivana Djurdjevic, Ara Patapoutian, Zheng Wang, AbdelHakim Alhussien, Sundararajan Sankaranarayanan, Ludovic Danjean, Erich F. Haratsch
  • Patent number: 10256839
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: April 9, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Heung-Mook Kim, Sun-Hyoung Kwon, Nam-Ho Hur
  • Patent number: 10177788
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: January 8, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Heung-Mook Kim, Sun-Hyoung Kwon, Nam-Ho Hur
  • Patent number: 10153786
    Abstract: A decoding method decodes data iteratively according to a first rule, measures at a selected iteration at least one performance criterion of the decoding of data according to the first rule, performs at the selected iteration a comparison of the at least one performance criterion to a threshold, when the comparison yields a first result relative to the threshold, continues decoding according to the first rule, and when the comparison yields a second result relative to the threshold, continues decoding according to a further rule. Decoding apparatus operates according to the method. The decoding according to the first rule, the measuring at least one performance criterion at the selected iteration, the performing the comparison at the selected iteration, and the continuing decoding according to the first or further rule, may be repeated until the comparison yields a predetermined result. Repeating may be stopped after a predetermined maximum number of iterations.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: December 11, 2018
    Assignee: Marvell International Ltd.
    Inventors: Phong Sy Nguyen, Shashi Kiran Chilappagari
  • Patent number: 10153781
    Abstract: Methods and apparatus for decoding LDPC codes provide that an LDPC code may be represented as a Tanner graph comprising bit nodes and check nodes and connections between them. In an embodiment, a configurable LDPC decoder, which supports many different LDPC codes having any sub-matrix size, comprises several independently addressable memories which are used to store soft decision data for each bit node. The decoder further comprises a number, P, of check node processing systems which generate updated soft decision data. The updated values are then passed back to the memories via a shuffling system. If the number of check nodes processed in parallel by the check node processing systems is PCNB (where P?PCNB) and the soft decision data for a bit node is of word size q bits, the total width of the independently addressable memories is larger than PCNB*q bits.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: December 11, 2018
    Assignee: Imagination Technologies Limited
    Inventors: Christopher Owen, Adrian John Anderson
  • Patent number: 10148289
    Abstract: A method includes: dividing a first polar code into an odd number part and an even number part, where the odd number part of the first polar code includes bits in odd number locations in the first polar code, and the even number part of the first polar code includes bits in even number locations in the first polar code; and interleaving the odd number part of the first polar code to obtain a first bit sequence, and interleaving the even number part of the first polar code to obtain a second bit sequence, where the first bit sequence and the second bit sequence form an output sequence of rate matching.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: December 4, 2018
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Hui Shen, Bin Li, Jun Chen
  • Patent number: 10148287
    Abstract: Memory systems may include a memory storage, and an error correcting code (ECC) unit suitable for determining a number of unsatisfied check nodes of a channel output in a decoding iteration of a decoding process, updating a flipping indicator of a variable node, comparing the flipping indicator of the variable node with a flipping threshold associated with the decoding process, flipping a bit of the variable node when the flipping indicator is greater than the flipping threshold, and ending the decoding process when decoding is determined to be successful or a maximal iteration number is reached.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: December 4, 2018
    Assignee: SK Hynix Inc.
    Inventors: Chenrong Xiong, Fan Zhang, Aman Bhatia, Abhiram Prabhakar, HongChich Chou, Naveen Kumar
  • Patent number: 10108489
    Abstract: Embodiments are related to systems and methods for data storage, and more particularly to systems and methods for storing and accessing data from a flash memory.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: October 23, 2018
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Zhijun Zhao, Shaohua Yang, Victor Krachkovsky
  • Patent number: 10084486
    Abstract: A method for decoding a received code using a device that includes: an antenna for receiving a signal over a wireless channel, and instances of a Maximum-A-Posteriori (MAP) turbo decoder for decoding a segment of the received code, are disclosed. For example, the method, by forward and backward gamma engines, for each window, concurrently computes gamma branch metrics in forward and backward directions, respectively, by forward and backward state metric engines comprising respective lambda engines and coupled to the respective gamma engines, for each window, sequentially computes forward and backward state metrics, respectively, based on respective gamma branch metrics and respective initial values, by the lambda engines, determines Log Likelihood Ratios (LLRs) and soft decisions, and by a post-processor, computes extrinsic data based on the forward and backward state metrics for any subsequent iteration as at least a portion of the a-priori information and otherwise provides a decoded segment.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: September 25, 2018
    Assignee: Intel Corporation
    Inventors: Jianbin Zhu, Yi Zhou, Yuzhou Zhang, Yuan Li, Chuong Vu
  • Patent number: 10075315
    Abstract: A method for transmitting data includes modulating data bits with a constellation to produce modulated data symbols, precoding the modulated data symbols to obtain ns groups of precoded samples, where ns is equal to a number of non-zero terms in a sparse code associated with the transmitting device, mapping the ns groups of precoded samples to groups of subcarriers in accordance with the sparse code associated with the transmitting device, to obtain a plurality of subcarrier-mapped samples, transforming the plurality of subcarrier-mapped samples into encoded data symbols, and transmitting the encoded data symbols.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: September 11, 2018
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Mikhail Germanovich Bakulin, Gennady Vladimirovich Ovechkin, Vitaly Borisovich Kreyndelin, Javad Abdoli
  • Patent number: 10038587
    Abstract: There is provided a device and method for demodulating a pulse amplitude modulated, hereinafter referred to as PAM, signal. The device comprises memory storing a set of boundaries of regions in which the log likelihood ratio, hereinafter referred to as LLR, for each bit to be determined is represented by a linear function of the received signal, along with the properties of the linear function for each bit for each region; and a controller. The controller is configured to: receive a PAM signal to be demodulated; determine which region the signal falls within; for each bit to be determined, retrieve the properties of the linear function for the LLR for the bit within the determined region and determine, from this linear function, the LLR value for the bit; and demodulate the signal based on the determined LLR values.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: July 31, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Magnus Stig Torsten Sandell, Filippo Tosato, Amr Ismail
  • Patent number: 9941902
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: April 10, 2018
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Heung-Mook Kim, Sun-Hyoung Kwon, Nam-Ho Hur
  • Patent number: 9838100
    Abstract: Various exemplary embodiments relate to a method for improving reception of transmissions with first adjacent interference signals, the method including selecting one or more time samples from each of two or more antennas; generating a lower first adjacent interference (LFAI) signal, a desired signal, and an upper first adjacent interference (UFAI) signal for each of the time samples; calculating a lower weighting co-efficient based on the LFAI signal; calculating a middle weighting co-efficient based on the desired signal; calculating a upper weighting co-efficient based on the UFAI signal; combining the lower weighting co-efficient with a filtered LFAI signal into a weighted lower signal; combining the middle weighting co-efficient with a filtered desired signal into a weighted middle signal; combining the upper weighting co-efficient with a filtered UFAI signal into a weighted upper signal; and combining the weighted lower signal, the weighted middle signal, and the weighted upper signal.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: December 5, 2017
    Assignee: NXP B.V.
    Inventor: Wim van Houtum
  • Patent number: 9813193
    Abstract: An error resilience method comprising: using a computer, creating and storing, in computer memory, one or more FEC filter tables for use by the FEC filter for selectively forwarding a FEC packet; selectively forwarding a request for the FEC packet through a FEC filter based on the FEC table and a dynamic packet loss level at a receiver; limiting a re-transmission request for a particular packet through the FEC filter based on a number of re-transmission requests for the particular packet; and selectively skipping a key frame request based on a number of key frame requests received from a plurality receiver devices, wherein the method is performed by one or more special-purpose computing devices.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: November 7, 2017
    Inventors: Qiyong Liu, Zhaofeng Jia, Kai Jin, Jing Wu, Huipin Zhang
  • Patent number: 9793928
    Abstract: A method for measuring a signal-to-noise ratio when decoding Low Density Parity Check (LDPC) codes is provided. The method includes receiving from an input of a demodulator an input code word with “strong” or “weak” solutions, decoding the input code word in a LDPC decoder using a predetermined dependence of a mean number of iterations on the signal-to-noise ratio, recording a number of iterations performed during the decoding of the input code word, averaging derived values of the number of iterations for a specified time interval, estimating a signal-to-noise ratio based on averaged derived values of the number of iterations and based on the predetermined dependence of the mean number of iterations on the signal-to-noise ratio, and generating an output decoded code word.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: October 17, 2017
    Assignee: Topcon Positioning Systems, Inc.
    Inventors: Nikolay Vazhenin, Andrey Veitsel, Ivan Kirianov
  • Patent number: 9735808
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: August 15, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Heung-Mook Kim, Sun-Hyoung Kwon, Nam-Ho Hur
  • Patent number: 9735807
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: August 15, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Heung-Mook Kim, Sun-Hyoung Kwon, Nam-Ho Hur
  • Patent number: 9729173
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: August 8, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Heung-Mook Kim, Sun-Hyoung Kwon, Nam-Ho Hur
  • Patent number: 9729171
    Abstract: Examples are given for techniques associated with error correction for encoded data. In some examples, error correction code (ECC) information for the ECC encoded data may be received that indicates the ECC encoded data has bit errors that are not able to be corrected by the ECC used to encode the ECC encoded data. A soft decision decoding may be implemented that includes flipping a given number of bits of a selected portion of the ECC encoded data based on a combinatorial operation or method. One or more successful decodes may result from this selective flipping to enable the ECC to successfully decode the ECC encoded data.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: August 8, 2017
    Assignee: Intel Corporation
    Inventor: Ravi H. Motwani
  • Patent number: 9680504
    Abstract: An operating method of a controller includes iterating a first ECC decoding on a codeword read from a semiconductor memory device according to a first read voltage a predetermined iteration number until the first ECC decoding succeeds, wherein a value of the first read voltage is updated on basis of a number of an unsatisfied syndrome check (USC); and when the first ECC decoding fails until the predetermined iteration number, performing a second ECC decoding on the codeword by generating soft decision data according to the first read voltage, a value of which corresponds to the minimum number of the USC among the updated values during the iterating of the first ECC decoding.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: June 13, 2017
    Assignee: SK Hynix Inc.
    Inventor: Jae-Bum Kim
  • Patent number: 9647795
    Abstract: According to one embodiment, a transmitter for transmitting at least one broadcast signal having PLP (Physical Layer Pipe) data includes: a BCH (Bose-Chadhuri-Hocquenghem) encoder configured to BCH encode the PLP data; an LDPC (Low Density Parity Check) encoder configured to LDPC encode the BCH encoded PLP data and output FECFrames (Forward Error Correction Frames); a mapper configured to map data in the FECFrames onto constellations by QAM (Quadrature Amplitude Modulation) schemes; a time-interleaver configured to time-interleave the mapped data; a frame builder configured to build a signal frame including preamble symbols and data symbols; and an OFDM (Orthogonal Frequency Division Multiplexing) modulator configured to modulate data in the signal frame by an OFDM scheme. The PLP data are processed by an LDPC scheme for a long or a short LDPC FECframe. The preamble symbols include signaling information for the time-interleaved PLP data. The data symbols include the time-interleaved PLP data.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: May 9, 2017
    Assignee: LG ELECTRONICS INC.
    Inventors: Woo Suk Ko, Sang Chul Moon
  • Patent number: 9612903
    Abstract: The present disclosure includes apparatuses and methods related to updating reliability data. A number of methods can include receiving, at a variable node, either a first reliability data value with a first hard data value or a second reliability data value with a second hard data value, sending the first hard data value or the second hard data value to each check node coupled to the variable node according to a parity check code, and updating the reliability data based on input from less than all of the check nodes.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: April 4, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Saeed Sharifi Tehrani, Nicholas J. Richardson
  • Patent number: 9577673
    Abstract: Apparatuses and methods for error correcting data are provided. A first error correction code (ECC) decoder is configured to decode a first codeword to provide a first result and to decode a second codeword to provide a second result. The decoder is configured to run up to a particular number of iterations to provide each of the results. A second ECC decoder is configured to decode a third codeword to provide decoded data, wherein the third codeword includes the first result and the second result. An evaluation module is configured to initiate a recovery scheme responsive to the decoded data including an error.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: February 21, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Sivagnanam Parthasarathy, Mustafa Nazmi Kaynak, Patrick Robert Khayat
  • Patent number: 9565581
    Abstract: A nonbinary iterative detector-decoder (IDD) system. The IDD system comprises a detector, a decoder; and a nonbinary interface electrically connected between the detector and decoder. The interface is operative to convert a soft symbol and variance that is output by the detector into a corresponding nonbinary log likelihood ratio (LLR) vector that comprises one or more nonbinary LLRs, and to provide the LLR vector to the decoder. The interface is further configured to convert a nonbinary LLR vector comprised of one or more nonbinary LLRs that is output by the decoder into a corresponding soft symbol and variance, and to provide the soft symbol and variance to the detector.
    Type: Grant
    Filed: February 20, 2016
    Date of Patent: February 7, 2017
    Assignee: The Regents of the University of Michigan
    Inventors: Zhengya Zhang, Chia-Hsiang Chen
  • Patent number: 9531406
    Abstract: It is provided a method for decoding a sequence of bits encoded by a LPDC code. The method comprises providing a set of bit states, including a first state and a second state, and a set of conditions to change a bit state including a first condition 5 and a second condition. The first condition and the second condition are different. The method comprises reading the value of each bit of the sequence, associating each bit to a respective state of the set according to the values as read, determining that an evaluated condition is met and changing the state of the target bit as a result of the condition being met. The method may then set the value of the target bit of the 10 sequence according to the state thereof. Such a method provides a solution for decoding a sequence of bits encoded by a LDPC code with better performance than the classic bit-flipping algorithm with only a slight increase in complexity.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: December 27, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Evangelos S. Eleftheriou, Robert Haas, Xiao-Yu Hu, Dung Nguyen
  • Patent number: 9496896
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: November 15, 2016
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Heung-Mook Kim, Sun-Hyoung Kwon, Nam-Ho Hur
  • Patent number: 9490843
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: November 8, 2016
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Heung-Mook Kim, Sun-Hyoung Kwon, Nam-Ho Hur
  • Patent number: 9483347
    Abstract: In an SSD controller reading from flash memory, subsequent to failure of an initial soft-decision decoding attempt based on a nominal LLR, soft-decision re-decoding attempts are made using compensated LLR soft-decision information sets, pre-calculated at respective read-equilibrium points corresponding to mean shifts and variance change in the actual charge-state distributions of the flash memory channel. According to embodiment, soft-decision re-decoding attempts are performed without a retry read, or overlapped with one or more retry reads. By overlapping re-decoding with one or more retry reads, the probability of successful decoding increases, the need for further retry reads diminishes, and throughput is improved. The LLR compensation becomes very effective over a large number of retry reads, improving decoding reliability and achieving close to optimal bit error rates, even in the presence of large channel variation.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: November 1, 2016
    Assignee: Seagate Technology LLC
    Inventors: Yunxiang Wu, Earl T. Cohen
  • Patent number: 9479289
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: October 25, 2016
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Heung-Mook Kim, Sun-Hyoung Kwon, Nam-Ho Hur
  • Patent number: 9391644
    Abstract: An improved decoding method is provided making it possible to solve the problem of the error floor of a turbo-code or of an LDPC code, or more generally of a correcting code from the family of “turbo-like codes”, while preserving the same spectral efficiency, without any decrease in the useful throughput of the encoded stream. This result is obtained by an identification, on input to the decoder, of the bits on which an error has a strong impact, and a modification of the likelihoods corresponding to these bits so as to improve the convergence of the decoder.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: July 12, 2016
    Assignee: Thales
    Inventors: Benjamin Gadat, Nicolas Van Wambeke, Lionel Ries
  • Patent number: 9385758
    Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for modifying symbols in a data set prior to re-processing.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: July 5, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Yu Chin Fabian Lim, Shaohua Yang, Kaitlyn T. Nguyen, Zuo Qi, Ku Hong Jeong
  • Patent number: 9369152
    Abstract: Systems and methods are provided for decoding data. A variable node value for a variable node is received at a first time, and reliability data for the variable node is received at a second time. The variable node is decoded using a first decoding scheme after the first time and before the second time, and the variable node is decoded using a second decoding scheme different from the first decoding scheme after the second time.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: June 14, 2016
    Assignee: Marvell World Trade Ltd.
    Inventors: Dung Viet Nguyen, Shashi Kiran Chilappagari, Phong Sy Nguyen
  • Patent number: 9337911
    Abstract: An approach for Soft-output K-Best MIMO detection comprises computing an estimated symbol vector and Log-Likelihood Ratio (LLR) values for transmitted bits. The approach includes a relevant discarded paths selection process, a last-stage on-demand expansion process, and a relaxed LLR computation process. The relevant discarded paths selection process includes analyzing the K-Best paths and discarded paths at each intermediate tree level and selecting only those discarded paths for further processing that will help in LLR computation for at least one of the transmitted bits. The last-stage on-demand expansion process includes expanding K paths at the tree level 2NT?1 (NT=number of transmit antennas) on-demand to only 2K?1 lowest Partial Euclidean Distance (PED) paths at last tree level 2NT. The relaxed LLR computation scheme includes approximating LLR computations by assuming that discarded path PED is greater than or equal K-Best path PED.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: May 10, 2016
    Assignee: MaxLinear, Inc.
    Inventors: Dimpesh Patel, Mahdi Shabany, Glenn Gulak
  • Patent number: 9323611
    Abstract: Systems and methods are provided for decoding data. A first decoder attempts to decode the data based on a hard decision input for a symbol. When the attempt to decode the data based on the hard decision input fails, a request is transmitted reliability information for the symbol. Receiving circuitry receives the reliability information for the symbol, and a second decoder decodes the data based on the reliability information.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: April 26, 2016
    Assignee: Marvell World Trade Ltd.
    Inventors: Shashi Kiran Chilappagari, Gregory Burd
  • Patent number: 9325347
    Abstract: A Forward Error Correction (FEC) decoder is provided, for example including a Layered Low Density Parity Check (LDPC) component. In an implementation, power consumption of the LDPC decoder is minimized with minimal to no impact on the error correction performance. This is achieved, in an implementation, by partially or fully eliminating redundant operations in the iterative process.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: April 26, 2016
    Assignee: Microsemi Storage Solutions (U.S.), Inc.
    Inventors: Peter Graumann, Sean Gibb
  • Patent number: 9317365
    Abstract: An apparatus having a circuit and an interface to a nonvolatile memory is disclosed. The circuit is configured to (i) read a plurality of bits in a read channel of the nonvolatile memory. The bits are encoded with a polar code. The circuit is also configured to (ii) generate a plurality of probabilities based on a plurality of log likelihood ratio values of the read channel and (iii) decode the bits based on the probabilities.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: April 19, 2016
    Assignee: Seagate Technology LLC
    Inventors: AbdelHakim S. Alhussien, Erich F. Haratsch, Yue Li
  • Patent number: 9294234
    Abstract: A receiving node makes an early estimate of the outcome of a decoding attempt and sends a corresponding early feedback (EHF) to the sending node. This has an effect of enabling a fast retransmission of the data by the sending node in case the decoding by the receiving node is likely to fail. An advantage of this is that any delays due to data retransmission may be minimized, resulting in a higher average throughput of the data transmission between the nodes.
    Type: Grant
    Filed: May 4, 2010
    Date of Patent: March 22, 2016
    Assignee: Telefonaktiebolaget L M Ericsson (publ)
    Inventors: Niclas Wiberg, Erik Eriksson, Pål Frenger, Jonas Fröberg Olsson, Bo Göransson
  • Patent number: 9281841
    Abstract: A method for determining update candidates in a low-density parity-check decoding process includes dividing the quasi-cyclic columns into groups and identifying an update candidate in each group. One or more of the identified update candidates are then updated. In the first half of iterative process, the higher quality candidate is updated. In the second half of the iterative process, the lower quality candidate is updated.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: March 8, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Lei Chen, Fan Zhang
  • Patent number: 9274891
    Abstract: A decoding method, a memory storage device and a memory controlling circuit unit are provided. The decoding method includes: reading at least one memory cell according to a first read voltage to obtain at least one first verification bit; executing a hard bit mode decoding procedure according to the first verification bit, and determining whether a first valid codeword is generated by the hard bit mode decoding procedure; if the first valid codeword is not generated by the hard bit mode decoding procedure, obtaining storage information of the memory cell; deciding a voltage number according to the storage information; reading the memory cell according to second read voltages matching the voltage number to obtain second verification bits; and executing a soft bit mode decoding procedure according to the second verification bits. Accordingly, the speed of decoding is increased.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: March 1, 2016
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Shao-Wei Yen, Yu-Hsiang Lin, Kuo-Hsin Lai
  • Patent number: 9270297
    Abstract: An example method is provided that includes receiving a representation of a codeword that includes a plurality of bits, and associating the bits with a respective plurality of one-bit hard-bit values representing the bits and multiple-bit soft-bit values representing measures of reliability of respective hard-bit values. The method includes for each of a plurality of iterations, updating a hard-bit/soft-bit value of one or more bits of a respective subset of the bits as a function of current hard-bit values of the subset's bits, and the current hard-bit and soft-bit values of the respective bit. For two iterations in which the current hard-bit and soft-bit values for each bit of a subset for both iterations is the same, the hard-bit/soft-bit value updated for any bit of the subset during one of the two iterations is the same as that computed for the respective bit during the other of the two iterations.
    Type: Grant
    Filed: July 31, 2011
    Date of Patent: February 23, 2016
    Assignee: Sandisk Technologies, INC.
    Inventors: Eran Sharon, Idan Alrod, Omer Fainzilber, Simon Litsyn
  • Patent number: 9252813
    Abstract: A method includes accepting modulated symbols, which carry bits of a code word of a Low Density Parity Check (LDPC) code, and computing respective soft input metrics for the bits. The code word is decoded using an iterative LDPC decoding process that includes selecting, based on a predefined criterion, a number of internal iterations to be performed by an LDPC decoder (84) in the process, performing the selected number of the internal iterations using the LDPC decoder so as to estimate decoded bits and soft output metrics indicative of the input bits based on the soft input metrics, performing an external iteration that updates one or more of the soft input metrics based on one or more of the soft output metrics produced by the LDPC decoder, and repeating at least one of the internal iterations using the updated soft input metrics.
    Type: Grant
    Filed: May 16, 2010
    Date of Patent: February 2, 2016
    Assignee: NOVELSAT LTD.
    Inventors: Daniel Wajcer, Mor Miller