Using Symbol Reliability Information (e.g., Soft Decision) Patents (Class 714/780)
  • Patent number: 11074125
    Abstract: An error management system for a data storage device can generate soft-decision log-likelihood ratios (LLRs) using multiple reads of memory locations. 0-to-1 and 1-to-0 bit flip count data provided by multiple reads of reference memory locations can be used to generate probability data that is used to generate possible LLR values for decoding target pages. Possible LLR values are stored in one or more look-up tables.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: July 27, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventor: Guangming Lu
  • Patent number: 11062758
    Abstract: Systems, memory controllers, decoders and methods perform decoding by exploiting differences among word lines for which soft decoding fails (failed word lines). Such decoding generates extrinsic information for codewords of failed word lines based on the soft decoding. The soft information obtained during the soft decoding is updated based on the extrinsic information, and the updated soft information is propagated across failed word lines. Low-density parity-check (LDDC) decoding of codewords of failed word lines is performed with the updated soft information.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: July 13, 2021
    Assignee: SK hynix Inc.
    Inventors: Naveen Kumar, Yu Cai, Fan Zhang
  • Patent number: 11038530
    Abstract: Techniques are described for joint encoding and decoding of information symbols. In one embodiment, a method for joint encoding includes, in part, obtaining a sequence of information symbols, generating a plurality of cyclic codewords each corresponding to a portion of the sequence of information symbols, jointly encoding the plurality of cyclic codewords to generate at least one combined codeword, and providing the combined codeword to a device. The at least one combined codeword may be generated through Galois Fourier Transform (GFT).
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: June 15, 2021
    Assignee: WESTHOLD CORPORATION
    Inventors: Shu Lin, Khaled Ahmed Sabry Abdel-Ghaffar, Juane Li, Keke Liu
  • Patent number: 11018696
    Abstract: According to certain embodiments, a method is provided for generating soft information for code bits of polar codes. The method includes receiving, by a decoder of a receiver, soft information associated with coded bits from a first module of the receiver and using a tree structure of the polar code to generate updated soft information. The updated soft information is output by the decoder for use by a second module of the receiver.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: May 25, 2021
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Dennis Hui, Yufei Blankenship
  • Patent number: 11003529
    Abstract: An encoding method for a memory storage apparatus adopting an ECC algorithm is provided. The memory storage apparatus comprises an ECC encoder. The encoding method includes: receiving a write command comprising a write address and a write data; reading an existing codeword; attaching a flip bit to the write data; encoding the write data and the flip bit to generate parity bits based on the ECC algorithm by the ECC encoder and attaching the write data and the flip bit to the plurality of parity bits to generate a new codeword; flipping the new codeword based on a number of bits among selected bits required to be changed from the existing codeword to the new codeword; and writing one of the new codeword and the flipped new codeword to the write address. In addition, a memory storage apparatus using the encoding method is provided.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: May 11, 2021
    Assignee: Winbond Electronics Corp.
    Inventors: Chuen-Der Lien, Ming-Huei Shieh, Chi-Shun Lin, Ngatik Cheung
  • Patent number: 10992317
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: April 27, 2021
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Heung-Mook Kim, Sun-Hyoung Kwon, Nam-Ho Hur
  • Patent number: 10979072
    Abstract: A method for punctured bit estimation includes receiving a punctured codeword. The method further includes generating a reconstructed codeword using the punctured codeword and at least one punctured bit having a default logic value. The method further includes generating a syndrome vector for the reconstructed codeword. The method further includes determining, using the syndrome vector, a number of unsatisfied parity-checks for the at least one punctured bit. The method further includes determining, for the at least one punctured bit, a bit value using, at least, the number of unsatisfied parity-checks associated with the at least one punctured bit.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: April 13, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ran Zamir, Eran Sharon, Idan Goldenberg, Dudy David Avraham
  • Patent number: 10958288
    Abstract: Methods and apparatus for decoding LDPC code provide that an LDPC code may be represented as a Tanner graph comprising bit nodes and check nodes and connections between them. A configurable LDPC decoder supporting many different LDPC codes having any sub-matrix size includes several independently addressable memories which are used to store soft decision data for each bit node. The decoder further includes a number P of check node processing systems which generate updated soft decision data. The updated values are then passed back to the memories via a shuffling system. If the number of check nodes processed in parallel by the check node processing systems is PCNB (where P?PCNB) and the soft decision data for a bit node is of word size q bits, the total width of the independently addressable memories is larger than PCNB*q bits.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: March 23, 2021
    Assignee: Imagination Technologies Limited
    Inventors: Christopher Owen, Adrian John Anderson
  • Patent number: 10944428
    Abstract: Techniques and mechanisms for determining information which is to be used for performing bit error correction. In an embodiment, bit reliability information is calculated based on a first likelihood function, and also on data signals which each indicate a respective bit of a codeword. Values of the bit reliability information each indicate, for a respective bit of the codeword, a confidence that the bit is at a particular logic state. A syndrome vector is calculated based on the bit reliability information, and one of the first likelihood function or a second likelihood function is selected based on one or more bit errors which are indicated by the syndrome vector. The selected one of the first likelihood function or the second likelihood function is used to correct bit errors of the codeword. In another embodiment, the first likelihood function is a default likelihood function to be used for initial syndrome vector calculations.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: March 9, 2021
    Assignee: Intel Corporation
    Inventors: Ravi Motwani, Poovaiah Palangappa, Santhosh Vanaparthy
  • Patent number: 10903856
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: January 26, 2021
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Heung-Mook Kim, Sun-Hyoung Kwon, Nam-Ho Hur
  • Patent number: 10892850
    Abstract: A method and an apparatus for carrying identification information are disclosed, to extend a quantity of bit positions that can represent identification information. The method includes determining, by a base station, bit locations that can be used to carry identification information in to-be-coded bits, where the bit locations that can be used to carry the identification information include locations of fixed bits, the identification information is used to identify a terminal, and the fixed bits are used by the terminal to perform error correction in a decoding process, adding, by the base station, the identification information to the bit locations, and encoding, by the base station in a polar code encoding mode, the to-be-coded bits that carry the identification information, and sending an encoded polar code to the terminal.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: January 12, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Hejia Luo, Yue Zhou, Rong Li, Ying Chen
  • Patent number: 10862625
    Abstract: Techniques are described for wireless communication. One method includes identifying a set of punctured bit locations in a received codeword. The received codeword is encoded using a polar code. The method also includes identifying a set of information bit locations of the polar code, with the set of information bit locations being determined based at least in part on polarization weights per polarized bit-channel of a polar code decoder that are a function of nulled repetition operations per polarization stage of the polar code identified based at least in part on the set of punctured bit locations. The method further includes processing the received codeword using the polar code decoder to obtain an information bit vector at the set of information bit locations.
    Type: Grant
    Filed: February 17, 2018
    Date of Patent: December 8, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Yang Yang, Jing Jiang, Changlong Xu, Gabi Sarkis, Chao Wei, Hari Sankar, Jian Li, Joseph Binamira Soriaga
  • Patent number: 10797728
    Abstract: Methods and systems are provided for decoding LDPC codewords or blocks of codewords using a second set of parameters if decoding the codewords or blocks of codewords fails using a first set of parameters. An LDPC codeword may be decoded using a first decoding technique to produce a first decoding output using a first parameter. The first parameter may be altered to generate a second parameter to be used in a second decoding technique. The LDPC codeword may be decoded using the second decoding technique to produce a second decoding output. A syndrome weight of the first decoding output may be compared to a syndrome weight of the second decoding output and one of the first decoding output or the second decoding output may be selected based on which of the first decoding output or the second decoding output has a lower error.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: October 6, 2020
    Assignee: Marvell Asia Pte, Ltd.
    Inventor: Nedeljko Varnica
  • Patent number: 10778371
    Abstract: Certain aspects of the present disclosure generally relate to methods and apparatus for decoding low density parity check (LDPC) codes, and more particularly to a deeply-pipelined layered LDPC decoder architecture for high decoding throughputs. Accordingly, aspects of the present disclosure provide techniques for reducing delays in a processing pipeline by, in some cases, relaxing a dependency between updating bit log likelihood ratios (LLRs) and computing a posteriori LLRs.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: September 15, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Vincent Loncke, Girish Varatkar, Thomas Joseph Richardson, Yi Cao
  • Patent number: 10778251
    Abstract: A method and apparatus for encoding low-density parity check codes uses parity check matrices composed of circulant blocks. The apparatus operates on a parity check matrix of a judiciously designed block structure, which permits low cost hardware implementation, and high encoding throughput.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: September 15, 2020
    Assignee: Codelucida, Inc.
    Inventors: David Declercq, Bane Vasic, Benedict J. Reynwar
  • Patent number: 10778366
    Abstract: Various aspects described herein relate to techniques for rate matching and interleaving in wireless communications (e.g., 5G NR). In an example, a method described herein includes encoding one or more information bits to generate a first codeblock, rate matching the first codeblock to generate a second codeblock, segmenting, using bit distribution, the second codeblock into one or more sub-blocks each having a plurality of bits. The method further includes interleaving the plurality of bits on each of the one or more sub-blocks, concatenating, using bit collection, the one or more sub-blocks to generate a third codeblock in response to the interleaving, and transmitting a signal using the third codeblock.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: September 15, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Vincent Loncke, Raghunath Kalavai, Yi Cao, Thomas Richardson, Joseph Binamira Soriaga, Shrinivas Kudekar
  • Patent number: 10762426
    Abstract: A multi-iteration method for compressing a deep neural network into a sparse neural network without degrading the accuracy is disclosed herein. In an example, the method includes determining a respective initial compression ratio for each of a plurality of matrices characterizing the weights between the neurons of the neural network, compressing each of the plurality of matrices based on the respective initial compression ratio, so as to obtain a compressed neural network, and fine-tuning the compressed neural network.
    Type: Grant
    Filed: December 26, 2016
    Date of Patent: September 1, 2020
    Assignee: BEIJING DEEPHI INTELLIGENT TECHNOLOGY CO., LTD.
    Inventors: Xin Li, Song Han, Shijie Sun, Yi Shan
  • Patent number: 10761927
    Abstract: A method of correcting one or more bit errors in a memory device includes retrieving a codeword from a memory device. The codeword includes a data and an error correcting code. The method further includes determining whether the one or more bit errors are present in the retrieved codeword and correcting the retrieved codeword for the one bit error in response to determining one bit error is present in the retrieved codeword. The method also includes flipping a bit of the retrieved codeword in response to determining a plurality of bit errors is present in the retrieved codeword and correcting the retrieved codeword for the plurality of bit errors based on the bit-flipped codeword.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Shih-Lien Linus Lu
  • Patent number: 10742236
    Abstract: A method for decoding a (n, k, d) cyclic code is disclosed. The method includes: receiving a word corresponding to the cyclic code; constructing a look-up table, wherein the look-up table includes k syndrome vectors and k error patterns; computing a syndrome vector of the received word by a hardware processor; comparing the weight of the syndrome vector of the received word with an error-correcting capacity; decoding the received word by adding the received word and the syndrome vector if the weight of the syndrome vector of the received word is not more than the error-correcting capacity; decoding the received word by inverting bits in the message section in sequence and re-compute a syndrome vector of the inverted received word if the weight of the syndrome vector of the received word is more than the error-correcting capacity.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: August 11, 2020
    Assignee: CHONGQING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS
    Inventors: Yong Li, Hsin-Chiu Chang, Hongqing Liu, Trieu-Kien Truong
  • Patent number: 10735135
    Abstract: A transmitter of a communications system includes a first encoder configured to apply a shaping operation to a data signal to generate a shaped data signal, a second encoder configured to encode the shaped data signal according to a forward error correction (FEC) scheme to generate an encoded signal, and a constellation mapper configured to modulate the encoded signal to symbol values according to a modulation scheme to generate a corresponding symbol stream for transmission through the communications system. The shaping operation reduces average constellation energy for constellations of the modulation scheme.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: August 4, 2020
    Assignee: Ciena Corporation
    Inventors: Shahab Oveis Gharan, Kim B. Roberts, Akbar Ghasemi, Mahmoud Taherzadehboroujeni
  • Patent number: 10700712
    Abstract: A semiconductor device includes a controller and a memory device. The controller includes a processor configured to process a request from an external apparatus, an interface configured to receive the request and data from the external apparatus and an ECC encoder configured to generate, in response to the request, a data block matrix including a plurality of data block groups and a plurality of parity blocks that are generated based on the received data, and to generate encoded data by adding parity information to the data block matrix, the encoded data being transmitted to the memory device.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: June 30, 2020
    Assignee: SK hynix Inc.
    Inventors: Dae Sung Kim, Chol Su Chae
  • Patent number: 10700706
    Abstract: A memory system, a controller including a bit-flipping (BF) decoder and a min-sum (MS) decoder that may be included in the memory system and operating methods thereof in which the controller determines a quality metric as a function of initial syndrome weight and information of the BF decoder after a set number of decoding iterations by the BF decoder in a test period. After the test period, the controller applies the quality metric to each codeword to determine whether to send that codeword first to the BF decoder for decoding or directly to the MS decoder for decoding.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: June 30, 2020
    Assignee: SK hynix Inc.
    Inventors: Fan Zhang, Aman Bhatia, Chenrong Xiong, Naveen Kumar, Yu Cai
  • Patent number: 10637510
    Abstract: Devices and methods for decoding a signal encoded using an error correcting code are provided. For example, a check node processing unit is provided for a decoder to receive at least two input messages and to generate at least one output message, each message comprising a plurality of components. The check node processing unit comprises a data structure configured to store the input messages, the components of the input messages being associated with an integer index. The check node processing unit also comprises a data processing unit configured to apply one or more iterations of a transformation operation to at least a part of the data structure depending on at least some of the components of the input messages associated with a given value of the integer index, which provides a transformed data structure. The check node processing unit further comprises a calculation unit configured to determine at least one output message from the transformed data structure.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: April 28, 2020
    Assignee: UNIVERSITE DE BRETAGNE SUD
    Inventors: Cédric Marchand, Emmanuel Boutillon
  • Patent number: 10630318
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: April 21, 2020
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Heung-Mook Kim, Sun-Hyoung Kwon, Nam-Ho Hur
  • Patent number: 10511410
    Abstract: The present invention concerns a method and device for demodulating received symbols using a turbo-demodulation scheme comprising an iterative channel equalization and wherein an iterative channel decoder is used in the turbo-demodulation scheme, characterized in that the iterative channel decoder performs a first iterative process named iterative decoding process, the turbo-demodulation performing a second iterative process named iterative demodulation and decoding process, at each iteration of the second iterative process, the iterative channel decoder executing plural iterations in order to decode bits from which symbols are derived from. The iterative channel decoder: —memorizes at the end of the iterations of the first iterative process, the variables used internally by the iterative channel decoder, —reads the memorized variables at the following iteration of the second iterative process.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: December 17, 2019
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Damien Castelain
  • Patent number: 10432226
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: October 1, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Heung-Mook Kim, Sun-Hyoung Kwon, Nam-Ho Hur
  • Patent number: 10425105
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: September 24, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Heung-Mook Kim, Sun-Hyoung Kwon, Nam-Ho Hur
  • Patent number: 10411754
    Abstract: A transmitter apparatus in a wireless communication system that includes a processor. In one embodiment, the processor is configured to receive at least one modulated data message and spread the at least one modulated data message into a transmission signal using a low density signature matrix. The low density signature matrix is a cycle-free signature matrix. A receiver apparatus is configured to receive the transmission signal and detect within the received transmission signal at least one modulated data message. The processor is configured to detect the at least one modulated data message in one iteration using the cycle-free signature matrix.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: September 10, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Anahid Robert Safavi, Alberto Giuseppe Perotti, Branislav M. Popovic
  • Patent number: 10355718
    Abstract: Performing soft error correction includes receiving a word at a soft correction engine capable of operating in more than one correction mode, identifying soft bit positions within the word, and automatically generating a number of possible results for the received word using combinations of the soft bit positions and more than one correction mode. The soft correction engine may include a Golay engine.
    Type: Grant
    Filed: July 1, 2008
    Date of Patent: July 16, 2019
    Assignee: Adaptive Networks, Inc.
    Inventors: Michael B. Propp, John Jakson
  • Patent number: 10291356
    Abstract: The disclosure relates to a method for decoding a transport block encoded with multiple codeblock segments. User equipment determines whether to decode one of a transport block cyclic redundancy check (CRC) and a codeblock segment CRC based on a speed of user equipment. In response to the speed of the user equipment being greater than a threshold, the user equipment decodes the transport block CRC and generates an acknowledgement (ACK)/non-acknowledgement (NAK). In response to the speed of the UE being less than or equal to the threshold, during a first data transmission, the user equipment decodes the codeblock segment CRC for each of the multiple codeblock segments and generates the ACK/NAK. During a second and latter data transmissions, the user equipment decodes the codeblock segment CRC for each of the multiple codeblock segments that failed in the first data transmission and generates the ACK/NAK.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: May 14, 2019
    Assignee: Futurewei Technologies, Inc.
    Inventors: SaiRamesh Nammi, Xiao-Feng Qi
  • Patent number: 10270474
    Abstract: A partial concatenated coding system using an algebraic code and LDPC code is disclosed. The partial concatenated coding system includes an ECC encoder, a received codeword monitoring module and an ECC decoder. The ECC encoder has a LDPC code encoding module and an algebraic code encoding module. The ECC decoder has a LDPC code decoding module and an algebraic code decoding module. Comparing with conventional concatenating coding systems, the present invention has advantages of less spare spaces, better error-correcting performance, lower hardware complexity, better decoding throughput and fixable code length.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: April 23, 2019
    Assignee: STORART TECHNOLOGY(SHENZHEN) CO., LTD.
    Inventors: Pei-Yu Shih, Tsung-Yu Wu
  • Patent number: 10263640
    Abstract: Method and apparatus for decoding data. In some embodiments, an LDPC decoder has a variable node circuit (VNC) with a plurality of variable nodes configured to store bit reliability values of m-bit code bits. A check node circuit (CNC) has a plurality of check nodes configured to perform parity check operations upon n-bit messages from the VNC. Each n-bit message is formed from a combination of the bit reliability values and stored messages from the check nodes. A pre-saturation compensation circuit is configured to maintain a magnitude of each n-bit message received by the CNC below a saturation limit comprising the maximum value that can be expressed using p bits, with p less than n and each of the n-bit messages received by the CNC having a different magnitude. The pre-saturation compensation circuit may apply different scaling and/or bias factors to the n-bit messages over different decoding iterations.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: April 16, 2019
    Assignee: Seagate Technology LLC
    Inventors: Ivana Djurdjevic, Ara Patapoutian, Zheng Wang, AbdelHakim Alhussien, Sundararajan Sankaranarayanan, Ludovic Danjean, Erich F. Haratsch
  • Patent number: 10256839
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: April 9, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Heung-Mook Kim, Sun-Hyoung Kwon, Nam-Ho Hur
  • Patent number: 10177788
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: January 8, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Heung-Mook Kim, Sun-Hyoung Kwon, Nam-Ho Hur
  • Patent number: 10153786
    Abstract: A decoding method decodes data iteratively according to a first rule, measures at a selected iteration at least one performance criterion of the decoding of data according to the first rule, performs at the selected iteration a comparison of the at least one performance criterion to a threshold, when the comparison yields a first result relative to the threshold, continues decoding according to the first rule, and when the comparison yields a second result relative to the threshold, continues decoding according to a further rule. Decoding apparatus operates according to the method. The decoding according to the first rule, the measuring at least one performance criterion at the selected iteration, the performing the comparison at the selected iteration, and the continuing decoding according to the first or further rule, may be repeated until the comparison yields a predetermined result. Repeating may be stopped after a predetermined maximum number of iterations.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: December 11, 2018
    Assignee: Marvell International Ltd.
    Inventors: Phong Sy Nguyen, Shashi Kiran Chilappagari
  • Patent number: 10153781
    Abstract: Methods and apparatus for decoding LDPC codes provide that an LDPC code may be represented as a Tanner graph comprising bit nodes and check nodes and connections between them. In an embodiment, a configurable LDPC decoder, which supports many different LDPC codes having any sub-matrix size, comprises several independently addressable memories which are used to store soft decision data for each bit node. The decoder further comprises a number, P, of check node processing systems which generate updated soft decision data. The updated values are then passed back to the memories via a shuffling system. If the number of check nodes processed in parallel by the check node processing systems is PCNB (where P?PCNB) and the soft decision data for a bit node is of word size q bits, the total width of the independently addressable memories is larger than PCNB*q bits.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: December 11, 2018
    Assignee: Imagination Technologies Limited
    Inventors: Christopher Owen, Adrian John Anderson
  • Patent number: 10148287
    Abstract: Memory systems may include a memory storage, and an error correcting code (ECC) unit suitable for determining a number of unsatisfied check nodes of a channel output in a decoding iteration of a decoding process, updating a flipping indicator of a variable node, comparing the flipping indicator of the variable node with a flipping threshold associated with the decoding process, flipping a bit of the variable node when the flipping indicator is greater than the flipping threshold, and ending the decoding process when decoding is determined to be successful or a maximal iteration number is reached.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: December 4, 2018
    Assignee: SK Hynix Inc.
    Inventors: Chenrong Xiong, Fan Zhang, Aman Bhatia, Abhiram Prabhakar, HongChich Chou, Naveen Kumar
  • Patent number: 10148289
    Abstract: A method includes: dividing a first polar code into an odd number part and an even number part, where the odd number part of the first polar code includes bits in odd number locations in the first polar code, and the even number part of the first polar code includes bits in even number locations in the first polar code; and interleaving the odd number part of the first polar code to obtain a first bit sequence, and interleaving the even number part of the first polar code to obtain a second bit sequence, where the first bit sequence and the second bit sequence form an output sequence of rate matching.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: December 4, 2018
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Hui Shen, Bin Li, Jun Chen
  • Patent number: 10108489
    Abstract: Embodiments are related to systems and methods for data storage, and more particularly to systems and methods for storing and accessing data from a flash memory.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: October 23, 2018
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Zhijun Zhao, Shaohua Yang, Victor Krachkovsky
  • Patent number: 10084486
    Abstract: A method for decoding a received code using a device that includes: an antenna for receiving a signal over a wireless channel, and instances of a Maximum-A-Posteriori (MAP) turbo decoder for decoding a segment of the received code, are disclosed. For example, the method, by forward and backward gamma engines, for each window, concurrently computes gamma branch metrics in forward and backward directions, respectively, by forward and backward state metric engines comprising respective lambda engines and coupled to the respective gamma engines, for each window, sequentially computes forward and backward state metrics, respectively, based on respective gamma branch metrics and respective initial values, by the lambda engines, determines Log Likelihood Ratios (LLRs) and soft decisions, and by a post-processor, computes extrinsic data based on the forward and backward state metrics for any subsequent iteration as at least a portion of the a-priori information and otherwise provides a decoded segment.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: September 25, 2018
    Assignee: Intel Corporation
    Inventors: Jianbin Zhu, Yi Zhou, Yuzhou Zhang, Yuan Li, Chuong Vu
  • Patent number: 10075315
    Abstract: A method for transmitting data includes modulating data bits with a constellation to produce modulated data symbols, precoding the modulated data symbols to obtain ns groups of precoded samples, where ns is equal to a number of non-zero terms in a sparse code associated with the transmitting device, mapping the ns groups of precoded samples to groups of subcarriers in accordance with the sparse code associated with the transmitting device, to obtain a plurality of subcarrier-mapped samples, transforming the plurality of subcarrier-mapped samples into encoded data symbols, and transmitting the encoded data symbols.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: September 11, 2018
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Mikhail Germanovich Bakulin, Gennady Vladimirovich Ovechkin, Vitaly Borisovich Kreyndelin, Javad Abdoli
  • Patent number: 10038587
    Abstract: There is provided a device and method for demodulating a pulse amplitude modulated, hereinafter referred to as PAM, signal. The device comprises memory storing a set of boundaries of regions in which the log likelihood ratio, hereinafter referred to as LLR, for each bit to be determined is represented by a linear function of the received signal, along with the properties of the linear function for each bit for each region; and a controller. The controller is configured to: receive a PAM signal to be demodulated; determine which region the signal falls within; for each bit to be determined, retrieve the properties of the linear function for the LLR for the bit within the determined region and determine, from this linear function, the LLR value for the bit; and demodulate the signal based on the determined LLR values.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: July 31, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Magnus Stig Torsten Sandell, Filippo Tosato, Amr Ismail
  • Patent number: 9941902
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: April 10, 2018
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Heung-Mook Kim, Sun-Hyoung Kwon, Nam-Ho Hur
  • Patent number: 9838100
    Abstract: Various exemplary embodiments relate to a method for improving reception of transmissions with first adjacent interference signals, the method including selecting one or more time samples from each of two or more antennas; generating a lower first adjacent interference (LFAI) signal, a desired signal, and an upper first adjacent interference (UFAI) signal for each of the time samples; calculating a lower weighting co-efficient based on the LFAI signal; calculating a middle weighting co-efficient based on the desired signal; calculating a upper weighting co-efficient based on the UFAI signal; combining the lower weighting co-efficient with a filtered LFAI signal into a weighted lower signal; combining the middle weighting co-efficient with a filtered desired signal into a weighted middle signal; combining the upper weighting co-efficient with a filtered UFAI signal into a weighted upper signal; and combining the weighted lower signal, the weighted middle signal, and the weighted upper signal.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: December 5, 2017
    Assignee: NXP B.V.
    Inventor: Wim van Houtum
  • Patent number: 9813193
    Abstract: An error resilience method comprising: using a computer, creating and storing, in computer memory, one or more FEC filter tables for use by the FEC filter for selectively forwarding a FEC packet; selectively forwarding a request for the FEC packet through a FEC filter based on the FEC table and a dynamic packet loss level at a receiver; limiting a re-transmission request for a particular packet through the FEC filter based on a number of re-transmission requests for the particular packet; and selectively skipping a key frame request based on a number of key frame requests received from a plurality receiver devices, wherein the method is performed by one or more special-purpose computing devices.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: November 7, 2017
    Inventors: Qiyong Liu, Zhaofeng Jia, Kai Jin, Jing Wu, Huipin Zhang
  • Patent number: 9793928
    Abstract: A method for measuring a signal-to-noise ratio when decoding Low Density Parity Check (LDPC) codes is provided. The method includes receiving from an input of a demodulator an input code word with “strong” or “weak” solutions, decoding the input code word in a LDPC decoder using a predetermined dependence of a mean number of iterations on the signal-to-noise ratio, recording a number of iterations performed during the decoding of the input code word, averaging derived values of the number of iterations for a specified time interval, estimating a signal-to-noise ratio based on averaged derived values of the number of iterations and based on the predetermined dependence of the mean number of iterations on the signal-to-noise ratio, and generating an output decoded code word.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: October 17, 2017
    Assignee: Topcon Positioning Systems, Inc.
    Inventors: Nikolay Vazhenin, Andrey Veitsel, Ivan Kirianov
  • Patent number: 9735807
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: August 15, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Heung-Mook Kim, Sun-Hyoung Kwon, Nam-Ho Hur
  • Patent number: 9735808
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: August 15, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Heung-Mook Kim, Sun-Hyoung Kwon, Nam-Ho Hur
  • Patent number: 9729171
    Abstract: Examples are given for techniques associated with error correction for encoded data. In some examples, error correction code (ECC) information for the ECC encoded data may be received that indicates the ECC encoded data has bit errors that are not able to be corrected by the ECC used to encode the ECC encoded data. A soft decision decoding may be implemented that includes flipping a given number of bits of a selected portion of the ECC encoded data based on a combinatorial operation or method. One or more successful decodes may result from this selective flipping to enable the ECC to successfully decode the ECC encoded data.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: August 8, 2017
    Assignee: Intel Corporation
    Inventor: Ravi H. Motwani
  • Patent number: 9729173
    Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: August 8, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Heung-Mook Kim, Sun-Hyoung Kwon, Nam-Ho Hur