Abstract: Turbo equalization is performing by using a soft output detector to perform decoding. At least a portion of a local iteration of decoding is performed using a soft output decoder. A metric associated with decoding progress is generated and it is determined whether to perform another local iteration of decoding based at least in part on the metric.

Abstract: A decoder for decoding received vectors r encoded in accordance with a forward error correction code having a parity check matrix H with multiple regions at least two of which have patterns of ones with different pattern characteristics. The decoder can include a permuted decode module configured to decode in accordance with a permuted version of the parity check matrix H in which the ones in one of the regions are permuted into a permuted pattern that has a pattern characteristic of the other region. The decoder can also include a reorder module that permutes probabilities of a received vector r to be decoded to correspond with the permuted parity check matrix H.

Abstract: Methods of reading data from storage devices may include reading data stored in the storage device using normal read voltages; performing a first low density parity check (LDPC) decoding based on the read data; generating reliability bits of each of read bits according to the decoding result, the read bits being bits of the read data; and performing a second low density parity check (LDPC) decoding based on the read data and the reliability bits to perform a first error correction on the read data.

Abstract: In one embodiment, a method includes passing a signal through an adaptive noise whitening filter, wherein one or more noise whitening coefficients used in the noise whitening filter are updated using a noise whitening filter coefficient updater, wherein the noise whitening filter is configured to process the signal according to a transfer polynomial: W(D)=1?(p1D+ . . . +p??D??), where p1 . . . p?? are noise whitening coefficients, where a tape channel is characterized by a transfer polynomial F(D)=1+f1D+ . . . +fLDL where D is delay corresponding to bit duration, with 2L being a number of states of the tape channel, wherein a soft detector has a total of 2L+? states, the noise whitening filter comprises 2?? states, ?? is greater than ?, L represents a memory length of the tape channel, and ? represents a memory length of the noise whitening filter.

Abstract: A device for demultiplexing a packet-based transport stream of transport stream packets each provided with a systematic forward error detection code is described. The transport stream packets are each allocated to one of a plurality of data sinks, so that in a payload data section of the transport stream packets allocated to the same data sink a data stream of forward error protection code-protected data packets which are addressed to the respective data sink is embedded. The device determines, for a transport stream packet which is erroneous according to the systematic forward error detection code, a probability value for each of the plurality of data sinks which indicates how probable it is that the predetermined transport stream packet is allocated to the respective data sink, and allocates the predetermined transport stream packet to a selected one of the plurality of data sinks.

Abstract: The present invention includes generating a tie-breaking metric via a comparative tie-breaking metric training process, monitoring an output of a channel detector in order to identify a tie condition between a first log-likelihood ratio (LLR) value and a second LLR value of a symbol, and upon identifying a tie condition between the first LLR value and the second LLR value of the symbol, applying the generated tie-breaking metric to the symbol in order to assign a hard decision to the symbol.

Abstract: The present disclosure includes systems and methods for acquiring a first set of information for a plurality of low density parity check (LDPC)-encoded data symbols, acquiring a second set of information for the plurality of LDPC-encoded data symbols, and selecting a window including a subset of the plurality of LDPC-encoded data symbols. The present disclosure includes acquiring a decoder schedule having information for controlling the decoder, wherein the information in the decoder schedule includes decoding instructions based on a configuration of at least one of the first set of information and the second set of information. The present disclosure further includes determining a likelihood of an error in the window using the decoding instructions in the decoder schedule, and updating the second set of information for selected data symbols of the subset based on the likelihood of an error in the window.

Abstract: An apparatus having a circuit and one or more processor is disclosed. The circuit is configured to receive a codeword from a memory. The memory is nonvolatile. The codeword generally has one or more errors. The processors are configured to generate read data by decoding the codeword repeatedly. The decoding includes a soft-decision decoding that uses a plurality of parameters calculated by (i) a first procedure, (ii) a second procedure in response to a plurality of failures of the decoding to converge using the first procedure and (iii) a third procedure in response to another failure of the decoding to converge using the second procedure.

Abstract: In an error detection correction method of an embodiment, in decoding processing using a sum-product algorithm, which repeats processing of propagating reliability ? from a check node set to correspond to a Tanner graph of a check matrix of a low density parity check code to a plurality of bit nodes connected to the check node, and processing of propagating reliability ? from a bit node to a plurality of check nodes connected to the bit node, the check node includes a parity of two bits or more.

Abstract: Systems, methods and/or devices that enhance the reliability with which data can be stored in and read from a memory utilize an error indicator to adaptively determine the soft information values used for decoding. For example, in some implementations, the method includes selecting a first set of one or more soft information values and receiving a read data command. The method further includes responding to the read data command by initiating performance of a data access operation to access data in a storage medium, the data access operation producing a syndrome weight; determining a first indicator based at least in part on the syndrome weight; based on the first indicator, selecting a second set of one or more soft information values; and decoding data obtained from the data access operation using the second set of one or more soft information values to produce a result.

Abstract: A method includes receiving a representation of a set of single error detection (SED) parity bits and a representation of data. The data includes an error correction coding (ECC) codeword including information bits and ECC parity bits. Each SED parity bit of the set of SED parity bits indicates a parity value for a corresponding portion of the data. The method includes, in response to determining that a particular portion of the representation of the data includes a single erasure bit, selectively modifying a bit value of the single erasure bit based on the representation of the SED parity bit that corresponds to the particular portion and generating an updated representation of the ECC codeword when the bit value of the single erasure bit corresponds to the ECC codeword and has been modified. The method may include initiating an ECC decode operation of the updated representation of the ECC codeword.

Abstract: The error correcting decoding device of the present invention performs Low-Density Parity-Check (LDPC) decoding which accommodates a plurality of code rates while sharing circuits to suppress increase in circuit scale. If the set code rate is a second code rate which is a higher code rate than a first code rate, a column processing and row processing calculating unit (120A) uses a distributed submatrix in which a number of columns are selected and combined, wherein the number of columns is equal in number to the number of columns with which a first submatrix is constructed from a distributed check matrix corresponding to a second check matrix which accommodates the second code rate. At this time, the column processing and row processing calculating unit (120A) uses a distributed submatrix such that the row degree is less than or equal to the row degree of the first submatrix.

Abstract: A storage device comprises a nonvolatile memory device comprising a plurality of memory cells, and an error correction circuit configured to receive primary data and secondary data from the nonvolatile memory device and to perform a hard decision decoding operation on the primary data and further configured to perform a soft decision decoding operation on the primary data based on the secondary data. The primary data is read from the plurality of memory cells in a hard decision read operation and the secondary data is read from memory cells programmed to a specific state from among the primary data.

Abstract: Embodiments of decoding data stored in solid-state memory arrays are disclosed. In one embodiment, multiple read operations are performed while taking inter-cell interference (ICI) into account. Soft-decision information, such as log-likelihood ratios (LLRs), is determined by using known data and its corresponding multi-read output. Soft-decision information is provided to a detector. Reliability is improved and performance is increased.

Abstract: Systems and methods for power efficient iterative equalization on a channel are provided. An iterative decoder decodes received data from a channel detector using a decoding process. The decoder computes a decision metric based on the decoded data and adjusts the number of iterations of the decoding process based on the decision metric. The adjustment occurs prior to a reliability criterion for the decoded data being satisfied. The decoder may pass control back to the channel detector if the adjusted number of iterations has occurred or if the reliability criterion is satisfied. Adjusting the number of iterations of the decoding process may include increasing the number of iterations from a predetermined number of iterations. The decision metric may be based on syndrome weight or hard decisions. The decision metric may be chosen to reduce average power consumption of the detector, the decoder, or circuitry including the detector and the decoder.

Abstract: A flash memory controller, a computer readable medium and a method. The method may include performing, by a flash memory controller, multiple read attempts of a group of flash memory cells, using multiple read thresholds, to provide multiple read results; determining, by the flash memory controller and based upon the multiple read results, a reliability metric of each of the multiple read results; and error correction decoding the multiple read results based upon reliability metrics associated with the multiple read results.

Abstract: Data that are stored in cells of a multi-bit-per cell memory, according to a systematic or non-systematic ECC, are read and corrected (systematic ECC) or recovered (non-systematic ECC) in accordance with estimated probabilities that one or more of the read bits are erroneous. In one method of the present invention, the estimates are a priori. In another method of the present invention, the estimates are based only on aspects of the read bits that include significances or bit pages of the read bits. In a third method of the present invention, the estimates are based only on values of the read bits. Not all the estimates are equal.

Abstract: A method for decoding comprises the following steps: receiving a first codeword comprising a plurality of elements of a first finite commutative group and associated to a plurality of symbols in accordance with a first code defining codeword elements by respective summations in said first commutative group; determining, by applying a projection onto elements of the first codeword, a second codeword comprising a plurality of elements of a second finite commutative group having a cardinal strictly smaller than the cardinal of the first finite commutative group, wherein the projection is a morphism from the first finite commutative group to the second finite commutative group; decoding the second codeword in accordance with a second code defining codeword elements by respective summations in said second commutative group.

Abstract: A system providing early termination for channel decoding by re-encoding including a decoding unit, an encoding unit connected to the decoding unit, and a checking unit connected to the decoding unit and to the encoding unit. Via the system, decoded message words produced from the decoding unit are sent back to the encoding unit for re-encoding. Re-encoded words are compared to the decoded codewords by the checking unit and, if they are completely the same, the decoding action of the decoding unit is terminated. The system reduces power consumption and offers a simplified structure, improved decoding throughput, and reduced hardware complexity.

Abstract: A processor includes a first memory module for storing a first set of storage values each representing a respective input, and a second memory module for storing a second set of storage values in analog form. An analog module is coupled to the first and the second memory modules. The analog module is configured to, in each operation cycle of at least one iteration, update at least some of the second set of storage values based on the first and the second sets of storage values. An output module is for generating a set of outputs from at least some of the second set of storage values.

Abstract: Computer-implemented methods and systems may perform one or more operations including, but not limited to: receiving input data from a source; applying an interleaving protocol to the input data to generate at least one component codeword; decoding the at least one component codeword; determining a first convergence value of at least one decoded component codeword; computing extrinsic data associated with the at least one component codeword according to the bit error count and the first convergence of at least one component codeword; determining a second convergence value associated with the at least one component codeword according to the extrinsic data associated with the at least one component codeword.

Abstract: An apparatus for comparing pairs of binary words includes an intermediate value determiner and an error detector. The intermediate value determiner determines an intermediate binary word so that the intermediate binary word is equal to a reference binary word for a first pair of equal or inverted binary words, so that the intermediate binary word is equal to the inverted reference binary word for a second pair of equal or inverted binary words and so that the intermediate binary word is unequal to the reference binary word and the inverted reference binary word for a pair of unequal and uninverted binary words, if the intermediate value determiner works faultlessly. Further, the error detector provides an error signal based on the intermediate binary word so that the error signal indicates whether or not the binary words of a pair of binary words are equal or inverted.

Abstract: Data that are stored in cells of a multi-bit-per cell memory, according to a systematic or non-systematic ECC, are read and corrected (systematic ECC) or recovered (non-systematic ECC) in accordance with estimated probabilities that one or more of the read bits are erroneous. In one method of the present invention, the estimates are a priori. In another method of the present invention, the estimates are based only on aspects of the read bits that include significances or bit pages of the read bits. In a third method of the present invention, the estimates are based only on values of the read bits. Not all the estimates are equal.

Abstract: A set of reliability metrics is provided for use by an iterative probabilistic decoding process for non-volatile storage. A plurality of sense operations are performed on at least one set of non-volatile storage elements which are programmed to a plurality of programming states. A set of reliability metrics such as logarithmic likelihood ratios is provided based on the sense operations. The set of reliability metrics is can be used by an iterative probabilistic decoding process in determining a programming state of at least one non-volatile storage element based on at least one subsequent sense operation involving the at least one non-volatile storage element. The plurality of sense operations can be performed at different ages (e.g., number of program/erase cycles) of the at least one set of non-volatile storage elements and the set of reliability metrics can be based on an average over the different ages.

Abstract: A soft output detector is programmed with a first set of parameters. Soft information is generated according to the first set of parameters, including likelihood information that spans a maximum likelihood range. Error correction decoding is performed on the soft information generated according to the first set of parameters. In the event decoding is unsuccessful, the soft output detector is programmed with a second set of parameters, soft information according is generated to the second set of parameters (including likelihood information that is scaled down from the maximum likelihood range), and error correction decoding is performed on the soft information generated according to the second set of parameters.

Abstract: A communication method using random linear coding is disclosed. The communication method using a random linear code comprises receiving first code blocks randomly linear-coded from a transmitter; demodulating the first code blocks using a decision distance determined in accordance with a channel status; determining whether an error has occurred in the first code blocks, using the decision distance, and transmitting a NACK signal to the transmitter, the NACK signal including information of the number of the code blocks where an error has occurred. Since a block error rate can be controlled in accordance with channel status, throughput can be improved.

Abstract: A custom decoding algorithm is introduced, in connection with a corresponding decoding structure, to resolve many complexity and large memory requirements of known decoders. A system. A variable node forms a confidence vector of four components, one component for each state of a memory cell, and passes the current primary component (e.g., the largest) to one or more check nodes. The check nodes calculate a temporary component and corresponding index based on all components received from the variable nodes, which they pass back to the respective variable nodes. The variable node updates the confidence vector based on the temporary nodes received from respective check nodes, and determines the correct state for corresponding memory cell based on which component in the confidence vector is currently the primary component.

Abstract: An error control encoding system produces a codeword from a data word, where the resulting codeword includes the data word and three or more parity segments produced using the data word. The system includes a first encoder to encode the data word in two or more first data segments in order to produce two or more first parity segments, where each of the two or more first data segments includes a respective sequential portion of the data word. The system includes a second encoder to encode the data word in one or more second data segments in order to produce a corresponding one or more second parity segments, where each of the one or more second data segments includes a respective sequential portion of the data word, and each of the one or more second data segments also includes a sequential portion of the data included in a plurality of the two or more first data segments.

Abstract: An error control system uses an error control code that corresponds to an error density location profile of a storage medium. The system includes an encoder configured to produce one or more codewords from data using an error control code generator matrix corresponding to the error density location profile of the storage medium. The system also includes a decoder configured to produce decoded data from one or more codewords using an error control code parity-check matrix corresponding to the error density location profile of the storage medium, where columns of the parity-check matrix are associated with corresponding data bits of the storage medium, rows of the parity-check matrix are associated with check bits, and each matrix element of the parity-check matrix having a predefined value indicates a connection between a particular data bit and a particular check bit.

Abstract: Embodiments of the inventions are related to systems and methods for data processing, and more particularly to systems and methods for mitigating trapping sets in a data processing system.

Abstract: A method and system are provided for a symbol-oriented approach that addresses information recovery from manufacturing variations (MVs) readings in a high noise environment. The multi-bits-per-symbol approach, which is in accordance with the various aspects of the present invention, is in contrast with how manufacturing-variation-derived bits are normally treated in the context of PUF Key Generation's error correction process. The multi-bit-per-symbol approach also offers a natural distance metric (distance to the most-likely symbol, distance to the next-most-likely symbol, etc.) which can aid soft-decision decoding or list-decoding, and can be used to improve the provisioning of a more reliably encoded secret and its associated helper data value.

Abstract: A processor includes a first memory module for storing a first set of storage values each representing a respective input, and a second memory module for storing a second set of storage values in analog form. An analog module is coupled to the first and the second memory modules. The analog module is configured to, in each operation cycle of at least one iteration, update at least some of the second set of storage values based on the first and the second sets of storage values. An output module is for generating a set of outputs from at least some of the second set of storage values.

Abstract: A circuit having a first circuit and a memory is disclosed. The first circuit may be configured to (i) receive a control signal that identifies a current one of a plurality of wireless communication standards and a code word size and (ii) generate a plurality of tables corresponding to both the current wireless communication standard and the code word size. Each of the tables generally has a plurality of indices. Up to two of the indices may be generated by the first circuit per clock cycle. Each of the tables generally comprises a permutation table of a turbo code interleaver. The memory may be configured to store the tables.

Abstract: A representation of a codeword is decoded by applying a first decoder of the codeword to the representation of the codeword. If applying the first decoder fails to decode the representation of the codeword then a second decoder of the codeword is applied to the representation of the codeword. Preferably, applying the first decoder consumes less power and is faster than applying the second decoder. Data are ported by encoding the data as a codeword, exporting the codeword to a corrupting medium, importing a representation of the codeword, and applying a first decoder to the representation of the codeword. If applying the first decoder fails to decode the representation of the codeword then a second decoder of the codeword is applied to the representation of the codeword.

Abstract: A modem architecture that supports the application of joint source channel decoding (JSCD). The modem architecture includes two channel decoders, one of which is modified to provide improved signal quality. The modem architecture further includes transparent network layers that enable the passage of data from one layer to another layer. For example, the modem architecture enables the passage soft bits, when available, from a physical layer to an application layer. The soft bits may be utilized for JSCD, packet loss concealment, or other applications. The modem architecture enables encryption and decryption of data to incorporate extrinsic information in operating JSCD.

Abstract: A low-density parity check (LDPC) decoder is provided for decoding low-density parity check (LDPC) encoded data wherein an adaptive check node approximation is performed at the check node processor utilizing the smallest magnitude log-likelihood ratio (LLR) and the second smallest magnitude log-likelihood ratio (LLR) to adapt to the current conditions at the check node.

Abstract: A Solid-State Disk (SSD) controller uses LDPC decoding to enable flash memory accesses with improved latency and/or error correction capabilities. With SLC flash memory having a BER less than a predetermined value, the SSD controller uses a 1-bit read (single read) hard-decision LDPC decoder to access the flash memory. If the hard-decision LDPC decoder detects an uncorrectable error, then the SSD controller uses a 1.5-bit read (two reads) erasure-decision LDPC decoder to access the flash memory. With flash memory having a raw BER between two other predetermined values, the SSD controller omits the use of the hard-decision LDPC decoder and uses only the erasure-decision LDPC decoder to access the flash memory. Variations of the SSD controller similarly access MLC flash memory. Some SSD controllers dynamically switch between hard-decision and erasure-based decoders based on dynamic decoder selection criteria.

Abstract: A high throughput and scalable MIMO detector can use a K-Best detection algorithm to find K combinations of transmit symbols that are likely to be the symbols that were actually transmitted. The K-best MIMO detector can include a plurality of stages, where each stage may correspond to a transmit antenna, and each stage can find K best symbol combinations based on information from a previous stage. To find the new K best symbol combinations, at each stage, a plurality of metrics for potential combinations are computed and sorted by magnitude. The MIMO detector preferably uses a high throughput, merge sorting algorithm to sort the metrics.

Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for utilizing multiple data streams for data recovery from a storage device. In some cases the systems include a low density parity check data decoder circuit including at least a first data decoder engine and a second data decoder engine each electrically coupled to a common circuit. The common circuit is operable to: shift a combination of both a first sub-message from the first data decoder engine and the second sub-message from the second data decoder engine to yield an shifted output, and disaggregate the shifted output to yield a third sub-message to the first data decoder engine and a fourth sub-message to the second decoder engine.

Abstract: Methods and apparatus are provided for improved iterative error-erasure decoding. A signal is decoded by obtaining a plurality of symbols associated with the signal and one or more corresponding reliability values; generating at least one erasure list comprised of L symbols and at least one shortened erasure list comprised of L? symbols, where L? is less than L; and constructing an erasure set by taking erasures from at least one of the erasure list and the shortened erasure list. A signal is also processed by generating one or more reliability values using a soft-output detector; generating an erasure list of symbols by comparing the reliability values to at least one reliability threshold value (or by sorting); and performing error erasure decoding using the erasure list. The size of the erasure list can optionally be adjusted using feedback information.

Abstract: An error management system for a data storage device can generate soft-decision log-likelihood ratios (LLRs) using multiple reads of memory locations. 0-to-1 and 1-to-0 bit flip count data provided by multiple reads of reference memory locations can be used to generate probability data that is used to generate possible LLR values for decoding target pages. Possible LLR values are stored in one or more look-up tables.

Abstract: An apparatus for providing improved color intensity mapping may include a processor. The processor may be configured to divide color intensity value byte data into high priority portions and low priority portions distributed as constellation points in a constellation matrix and to provide separation between each of the constellation points by assigning a unique mapping code to a plurality of the constellation points.

Abstract: One or more locations in a plurality of data bit sequences that do not satisfy parity and are associated with data bit sequences that are unable to be successfully error correction decoded are determined. Soft information associated with the determined locations is modified and error correction decoding using the modified soft information is performed.

Abstract: A soft decision value generation circuit capable of reducing amount of calculation and hardware scale for generating a soft decision value. The soft decision value generation circuit includes: a phase rotation unit rotating phases of received symbols after coherent detection; addition units calculating, by using the phase-rotated received symbols, absolute values of soft decision values for soft decision value candidates restricted in advance; minimum value selection units selecting minimum values out of the absolute values of the soft decision values; sign reflection units reflecting, based on the phases of the received symbols after the phase rotation, sign information to the minimum values; and soft decision value correction units multiplying outputs of the sign reflection units by a coefficient depending on a noise variance value and an amplitude value of a modulation symbol.

Abstract: A low-density parity check (LDPC) code decoding method may be provided. The LDPC code decoding method may linearize or perform step-approximation on a natural logarithm hyperbolic cosine function included in a check node updating equation of a sum-product algorithm used for decoding an LDPC code, and may convert the linearized function to correspond to a check node updating equation of a min-sum algorithm.

Abstract: Systems, methods, and apparatus are provided for iteratively decoding a codeword. Once a codeword is received, the codeword is processed to generate an incremental hard decision value and a log likelihood ratio amplitude value. These values are generated by processing the codeword using a soft output Viterbi algorithm. A faulty symbol in the codeword is identified. A complete hard decision value is generated using the incremental hard decision value. The LLR amplitude value and complete hard decision value corresponding to the identified faulty symbol are selectively provided to a decoder and the decoder uses these values to decode the codeword.

Abstract: A first set of one or more soft detector outputs is generated. It is determined if error correction decoding is successful using the first set of soft detector outputs. In the event it is determined error correction decoding is not successful, a second set of one or more soft detector outputs is generated where a largest likelihood associated with the first set is greater than a largest likelihood associated with the second set.

Abstract: A set of decisions is determined based at last in part on a set of samples. For a given sample in the set of samples, a low frequency noise estimate is estimated based at least in part on (1) at least some samples from the set of samples and (2) at least some decisions from the set of decisions. A reduced noise sample is generated by removing the low frequency noise estimate from the given sample.

Abstract: A communication system includes: a decoding-probability module for calculating a decoding likelihood with a control unit for characterizing an alternative hypothesis regarding an arriving communication; a null-probability module, coupled to the decoding-probability module, for calculating a null likelihood for characterizing a null hypothesis regarding the arriving communication; a weight-calculation module, coupled to the decoding-probability module, for generating a decision weight corresponding to the decoding likelihood, the null likelihood, or a combination thereof; a reliability calculation module, coupled to the decoding-probability module, for calculating a decoding reliability with the decision weight, the decoding likelihood, and the null likelihood, the decoding reliability corresponding to a decoded-result; and a decoding module, coupled to the reliability calculation module, for decoding the arriving communication with a decoding parameter based on the decoding reliability for communicating with

Abstract: A signal detector/decoder is implemented in multiple stages. The beginning stage is configured to input channel data bits and to output hard data bits based on the channel bits and a maximum likelihood (ML) path. The next stage includes a postcoder coupled to receive channel domain information from the first stage and to convert the channel domain information to user domain information. The final stage includes a reliability unit coupled to receive the user domain information from the postcoder and to output user domain soft information for the hard data bits based on the ML path estimation and the user domain information.