Abstract: A system for reading data from a data storage device includes a channel detector configured to detect bits of digital data corresponding to the data read from the storage device, and, for each of the bits of digital data, determine a probability that each of the bits is a 0 or a 1. A decoder module is configured to generate confidence indicators associated with a first subset of the digital data. The confidence indicators include the probability, received from the channel detector, that each of the bits in the first subset of the digital data is a 0 or a 1, and/or bit flip data indicating a number of times each of the bits in the first subset of the digital data was flipped during decoding. A digital defect detection module is configured to selectively identify the first subset of the digital data as defective based on the confidence indicators.

Abstract: Systems and methods are provided for GF(q) iterative decoding. A decoder computes a plurality of R messages corresponding to a variable node of the decoder and forms decoder extrinsic information for the variable node by combining the plurality of R messages. The decoder stores the decoder extrinsic information in a memory during a first time period and retrieves the decoder extrinsic information from the memory during a second time period, the second time period occurring after the first time period. The decoder extrinsic information is provided to a soft detector.

Abstract: Communication device employing binary product coding with selective additional cyclic redundancy check (CRC) therein. Product code encoding (e.g., employing row and column encoding of matrix formatted bits, selectively with interleaving and/or permutation of the bits therein) may be combined with additional error correction code (ECC) or forward error correction (FEC) coding thereby generating coded bits for use in generating a signal to be launched into a communication channel Various ECCs/FECs may be employed including a BCH (Bose and Ray-Chaudhuri, and Hocquenghem) code, a Reed-Solomon (RS) code, an LDPC (Low Density Parity Check) code, etc. The redundancy of such coded signals as generated using the principles herein is in the range of approximately 7%, and hard decision decoding may be performed on such coded signals generated herein. In accordance with decoding such (e.g.

Abstract: Embodiments of the present invention provide multi-level signal memory with LDPC and interleaving. Thus, various embodiments of the present invention provide a memory apparatus that includes a memory block comprising a plurality of memory cells, each memory cell adapted to operate with multi-level signals. Such a memory apparatus also includes a low density parity check (LDPC) coder to LDPC code data values to be written into the memory cells and an interleaver adapted to apply bit interleaved code modulation (BICM) to the LDPC coded data values to generate BICM coded data values. Other embodiments may be described and claimed.

Abstract: A method of generating a reliability indicator for decoding an encoded signal transmitted from a transmitter to a receiver via a wireless channel subject to fading. The method comprises: receiving symbols of the encoded signal; generating a reliability indicator for decoding at least some of the symbols selectively based on one or both of a statistical model representing additive white Gaussian noise (AWGN) in the encoded signal and a statistical model representing fading of the encoded signal; and selecting the statistical model based on signal characteristics of the wireless channel.

Abstract: Decoding data received includes decoding the received data using a first error correcting circuitry that decodes data in accordance with a first decoding process, terminating execution of the first decoding process used to correct the data before the first error correcting circuitry completes executing the first, decoding process and outputting partially decoded data, determining whether partially decoded data requires further decoding, and in response to determining whether partially decoded data requires further decoding, decoding the partially decoded data using a second error correcting circuitry that decodes data in accordance with a second decoding process. A system decodes data in accordance with the method.

Abstract: A computer implemented method for a cyclic (forward-backward) decoding for a forward error-correction FEC scheme includes decoding a given k?1th codeword in in a block code of length N in an optical communication system, forwarding M symbols' enhanced log likelihood ratios LLRs produced by decoding the k?1th codeword, decoding the kth codeword together with forwarded M symbols' enhanced LLRS, and feeding backward, to the initial step i) decoding, corresponding overlapped M symbols' enhanced LLRs for decoding of the k?1 th codeword again.

Abstract: A system is configured to receive a block of symbols, associated with a phase-modulated signal that includes data symbols that correspond to a payload associated with the signal, and control symbols; process the control symbols to identify an amount of phase noise associated with the control symbols; reset a phase, associated with each of the data symbols, based on the amount of phase noise and a reference phase; interleave the respective data samples, of each of the data symbols with other data samples, where the interleaved respective data samples cause errors, associated with the respective data samples, to be spread out among the other data samples and reduces an error rate relative to a prior data rate that existed before the interleaving; and perform forward error correction on the interleaved respective data samples.

Abstract: Provided is a receiver for processing VSB signal. The receiver includes a first equalizer/decoder unit and a second equalizer/decoder unit. The first equalizer/decoder unit performs a first equalizing operation, first TCM decoding and first RS decoding on a received symbol to output a first dibit. The second equalizer/decoder unit performs a second equalizing operation, second TCM decoding and second RS decoding on the received symbol to output a transport stream. The first dibit is provided as a priori information for a soft-decision operation of the second TCM decoding.

Abstract: In one embodiment, a tape drive system includes a soft detector for executing a first forward loop of a detection algorithm on a first block of signal samples during a first time interval; and logic for executing forward and reverse loops during several time intervals; and logic adapted for outputting a first decoded block of signal samples based on the executing the decoding algorithm on the first block during a sixth time interval, wherein a sum of second, third, fourth, fifth, and sixth time intervals are about equal in duration to the first time interval.

Abstract: A decoding apparatus and method for estimating a reliability value by detecting uncorrected packet errors. The decoding apparatus includes a hard-decision unit and a reliability determination unit. The hard-decision unit performs hard-decision on a soft-input of a code. The reliability determination unit generates a reliability estimation value of the hard-decision result according to whether a packet error exists in the hard-decision result. The hard-decision unit performs hard-decision in response to the reliability estimation value.

Abstract: Various embodiments of the present invention provide systems and methods for a symbol flipping data processor. For example, a symbol flipping data processor is disclosed that includes a data decoder in the symbol flipping data processor operable to perform error checking calculations, and a data detector in the symbol flipping data processor operable to perform symbol flipping in the data detector based at least in part on the error checking calculations, wherein the output of the data processor is generated at least in part based on the symbol flipping in the data detector.

Abstract: Various embodiments of the present invention provide systems and methods for media defect detection. For example, a data transfer system is disclosed that includes a data detector, a defect detector and a gating circuit. The data detector provides a soft output, and the defect detector is operable to receive the soft output and the data signal, and to assert a defect indication based at least in part on the soft output and the data signal. The gating circuit is operable to modify the soft output of the detector whenever the defect indication is asserted.

Abstract: The present disclosure describes methods and apparatuses for improved transport block decoding in devices capable of wireless communication, which may include user equipment and network entities. For example, the present disclosure presents methods and apparatuses for decoding a code block from a plurality of code blocks corresponding to a transport block, obtaining a reliability indicator that identifies a reliability of the decoding of the code block, comparing the reliability indicator to a reliability threshold, and determining whether to decode a subsequent code block from the plurality of code blocks based on the comparing. Furthermore, these methods and apparatuses may include determining not to decode at least one subsequent code block of the transport block where the comparing indicates that the reliability indicator is less than the reliability threshold. As such, device power is not unnecessarily consumed by decoding likely superfluous code blocks.

Abstract: Methods of operating nonvolatile memory devices include testing strings of nonvolatile memory cells in the memory device to identify at least one weak string therein having a higher probability of yielding erroneous read data error relative to other strings. An identity of the at least one weak string may be stored as weak column information, which may be used to facilitate error detection and correction operations. In particular, an error correction operation may be performed on bits of data read from the strings using an algorithm that modifies a weighting of the reliability of one or more data bits in the bits of data based on the weak column information. More specifically, an algorithm may be used that interprets a bit of data read from the at least one weak string as having a relatively reduced reliability relative to other ones of the data bits.

Abstract: Disclosed herein is a method and apparatus for transferring extrinsic information of a turbo decoder. In the method of transferring the extrinsic information of the turbo decoder according to the present invention, Log-Likelihood Ratio (LLR) values for input bits of the turbo decoder are calculated. The LLR values are transferred as extrinsic information values.

Abstract: Systems, devices, and methods are disclosed for a novel LDPC decoder. An architecture is described to implement a novel sequence of bit node processing (BNP) and check node processing (CNP) operations. More specifically, the BNP may be split into two parts: a BNP accumulator and a BNP extrinsic information calculator. This separation of processing modules may provide for fewer read and write operations to and from edge memory.

Abstract: A data receiving circuit includes: a first de-interleave circuit configured to de-interleave first data which is demodulated and is soft-decision-processed; a second de-interleave circuit configured to de-interleave second data which is demodulated and is soft-decision-processed; a memory configured to be shared by the first de-interleave circuit and the second de-interleave circuit and store respective hard decision information and respective soft decision information of the first data and the second data; and a memory control circuit configured to vary a first through fourth number of bits stored in the memory, the first number corresponding to the hard decision information of the first data, the second number corresponding to the soft decision information of the first data, the third number corresponding to the hard decision information of the second data, the fourth number corresponding to the soft decision information of the second data.

Abstract: Provided is a soft demapping apparatus that may detect a log likelihood ratio (LLR) value of a quadrature amplitude modulation (QAM) signal, using a shifted table scheme, may designate a sub-region of the QAM signal corresponding to bit information that is obtained by decoding the LLR value, and may calculate an LLR value of other bit information included in the designated sub-region.

Abstract: Provided are a method of decoding an LDPC code for producing several different decoders using a parity-check matrix of the LDPC code, and an LDPC code system including the same. The system includes: an LDPC encoder outputting an LDPC codeword through a channel; a first LDPC decoder decoding the LDPC codeword received through the channel, and when the decoding has failed in a second LDPC decoder, decoding the LDPC codeword according to original parity check matrix of the LDPC codeword, using soft information newly generated after the decoding is ended in the second LDPC decoder; and the second LDPC decoder, when the decoding has failed in the first LDPC decoder, receiving the soft information on each bit from the first LDPC, and decoding the LDPC codeword according to a new parity-check matrix produced from the parity-check matrix of the LDPC codeword using the received soft information on each bit.

Abstract: The present inventions are related to systems and methods for irregular decoding of regular codes in an LDPC decoder, and in particular to allocating decoding resources based in part on data quality.

Abstract: The present disclosure describes techniques for pre-scaling decoder input values. In some aspects a soft-decoding input indicating a reliability of an encoded bit is received, the soft-decoding input is scaled based on a value of the soft-decoding input, and a hardware-based soft-decoder is enabled to use the scaled soft-decoding input to decode the encoded bit. By so doing, resolution of the soft-decoding input can be preserved during subsequent decoding operations improving performance of the hardware-based soft-decoder.

Abstract: A method includes generating first and second data units corresponding to first and second PHY modes, respectively. Generating the first data unit includes FEC encoding first information bits, mapping the FEC-encoded bits to first constellation symbols, and generating first OFDM symbols to include the first constellation symbols. The first OFDM symbols utilize a first tone spacing, and include a first number of non-zero tones collectively spanning a first bandwidth. Generating the second data unit includes FEC encoding second information bits, block encoding the FEC-encoded bits, mapping the block-encoded bits to second constellation symbols, and generating second OFDM symbols to include the second constellation symbols. The second OFDM symbols utilize the first tone spacing, and include a second number of non-zero tones collectively spanning a second bandwidth less than the first bandwidth. The second number of non-zero tones is less than the first number of non-zero tones.

Abstract: A modified soft output Viterbi algorithm (SOVA) detector receives a sequence of soft information values and determines a best path and an alternate path for each soft information value and further determines, when the best and alternate paths lead to the same value for a given soft information value, whether there is a third path departing from the alternate path that leads to an opposite decision with respect to the best path for a given soft information value. The SOVA detector then considers this third path when updating the reliability of the best path. The modified SOVA detector achieves max-log-map equivalence effectively through the Fossorier approach and includes modified reliability metric units for the first N stages of the SOVA detector, where N is the memory depth of a given path, and includes conventional reliability metric units for the remaining stages of the detector.

Abstract: In a digital broadband broadcast transmitter, digital data is time interleaved for transmission, and the time interleaved digital data is transmitted in a digital broadband broadcast transmission towards a plurality of receivers. A cellular transmitter is operated in an apparatus. In the same apparatus, the digital broadband broadcast transmission transmitted by the digital broadband broadcast transmitter is received, and the received digital broadband broadcast transmission is time deinterleaved.

Abstract: Error concealment guided robustness may include identifying a current portion of a current video stream. Identifying the current portion may include identifying a feature, or a vector of features, for the current portion. An estimated vulnerability metric may be identified based on the feature and an associated learned feature weight. An error correction code for the current portion may be generated based on the estimated vulnerability metric. Error concealment guided robustness may include generating learned feature weights based on one or more training videos by generating vulnerability metrics for the training videos and identifying relationships between features of the training videos and the vulnerability metrics generated for the training videos.

Abstract: Various embodiments of the present invention provide data processing circuits that include: a data detector circuit, a data decoder circuit, and a modification circuit. The data detector circuit is operable to apply a data detection algorithm to a data input to yield a detected output. The data decoder circuit is operable to apply a data decode algorithm to a decode input to yield a decoded output. The decode input is selected between at least the detected output, and a modified version of the detected output. The modification circuit is operable to receive the detected output and to provide the modified version of the detected output.

Abstract: A computer implemented method for generating soft bit metric information of telecommunications systems employing differential encoding of data.

Abstract: A method for controlling a message-passing algorithm (MPA) based decoding operation includes: gathering statistics data of syndromes obtained from executed iterations; and selectively adjusting a decoding operation in a next iteration to be executed according to the statistics data. A control apparatus for controlling an MPA based decoder includes an adjusting circuit and a detecting circuit. The detecting circuit is coupled to the adjusting circuit, and used for gathering statistics data of syndromes obtained from executed iterations, and selectively controlling the adjusting circuit to adjust a decoding operation in a next iteration to be executed according to the statistics data.

Abstract: While decoding a representation, imported from a channel, of a codeword that encodes K information bits as N>K codeword bits, by updating estimates of the codeword bits in a plurality of iterations, the iterations are interrupted upon satisfaction of an interruption criterion that is either an order-dependent interruption criterion or an interruption criterion that includes an estimate of mutual information of the codeword and a vector that is used in the decoding iterations. Either the iterations are terminated or the iterations are resumed after one or more elements of one or more vectors used in the iterations is/are modified.

Abstract: According to some embodiments, a turbo decoder configured for High-Speed Packet Access (HSPA) and Long Term Evolution (LTE) is provided, comprising: a plurality of maximum a posteriori (MAP) engines; a plurality of extrinsic memory banks accessible by a MAP engine of the plurality of MAP engines; and wherein when the turbo decoder is operating in HSDPA mode the plurality of extrinsic memory banks is configured such that during a first half of a decoding iteration, the MAP engine is able to read a first dataset from and write second dataset to the plurality of extrinsic memory banks in natural row and column order, and during a second half of the decoding iteration, the MAP engine is able to read a third dataset from and write a fourth dataset to the plurality of extrinsic memory banks in a predetermined row and column order in accordance with an interleaver table using a read column buffer and a write column buffer.

Abstract: A QC-LDPC decoding system employing a trapping set look-up table is provided. The entries of the trapping set look-up table may be sorted according to failure frequencies of the trapping sets. The decoder may determine short-cycles associated with dominant trapping sets in order to decode the received codeword. If the iterative decoder of the QC-LDPC decoding system fails to produce a valid codeword, the decoder may compute the syndrome pattern of the processed codeword and search the look-up table for a trapping set class that is responsible for the iterative decoder's failure. If no responsible trapping set is found in the look-up table, the decoder may attempt to decode the received codeword using alternate decoding methods and subsequently determine a trapping set associated with the decoded codeword. If a trapping set is determined, then that trapping set may be added to the look-up table.

Abstract: Systems, methods, and other embodiments associated with data decoding are described. According to one embodiment, a method includes receiving an output value from one of a first block and a second block that form a pair of concatenated decoding blocks. The method includes determining a value of a modification criteria and modifying the output value based, at least in part, on the value of the modification criteria to form a modified output value. The modified output value is input to one of the first and second decoding blocks.

Abstract: One aspect provides a method. The method comprises receiving a signal comprising a sequence of encoded symbols, each corresponding to one of a plurality of possible states. For each symbol in the sequence, the method further comprises determining a set of state metrics, each representing a probability that the respective symbol corresponds to the plurality of states. The method further comprises decoding the signal by processing runs of recursions using runs of forward recursions, whereby a later state metric in the sequence is updated based on a preceding state metric, and runs of recursions using runs of reverse recursions, whereby a preceding state metric in the sequence is updated based on a later state metric. The method further comprises outputting the decoded signal to a device. The decoding comprises performing a plurality of repeated iterations over the sequence.

Abstract: Techniques for efficiently and accurately computing log-likelihood ratio (LLRs) for code bits are described. A set of code bits may be mapped to a modulation symbol in a signal constellation. Different code bits in the set may be associated with different LLR functions. A receiver obtains received symbols for a transmission sent via a communication channel. The receiver derives LLRs for code bits based on the received symbols and piecewise linear approximation of at least one LLR function. The piecewise linear approximation of each LLR function may comprise one or more linear functions for one or more ranges of input values. The receiver may select one of the linear functions for each code bit based on a corresponding received symbol component value. The receiver may then derive an LLR for each code bit based on the linear function selected for that first code bit.

Abstract: Apparatuses and methods for determining soft data using a classification code are provided. One example apparatus can include a classification code (CC) decoder and an outer code decoder coupled to the CC decoder. The CC decoder is configured to receive a CC codeword. The CC codeword includes a piece of an outer code codeword and corresponding CC parity digits. The CC decoder is configured to determine soft data associated with the piece of the outer code codeword, at least partially, using the corresponding CC digits.

Abstract: Data that are stored in cells of a multi-bit-per cell memory, according to a systematic or non-systematic ECC, are read and corrected (systematic ECC) or recovered (non-systematic ECC) in accordance with estimated probabilities that one or more of the read bits are erroneous. In one method of the present invention, the estimates are a priori. In another method of the present invention, the estimates are based only on aspects of the read bits that include significances or bit pages of the read bits. In a third method of the present invention, the estimates are based only on values of the read bits. Not all the estimates are equal.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, data processing systems are disclosed that include: a data decoder circuit, a decoder log, a mis-correction detection circuit, and a controller circuit.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, data processing systems are disclosed that include a data decoding circuit having a data decoder circuit, an element modification circuit, an element modification log, and a mis-correction detection circuit.

Abstract: By utilizing Reed-Solomon erasure decoding algorithms and techniques, the system is able to perform error detection for the case where the number of bytes received in error exceeds a correcting capability of a decoder. The error detection can be used, for example, to determine whether a codeword is decodable, and whether the retransmission of data is necessary. The retransmission can be accomplished by assembling a message that is sent to another modem requesting retransmission of one or more portions of data, such as one or more codewords.

Abstract: A memory controller including a buffer configured to perform decoding frame-unit data decoded by an LDPC decoder through partial parallel processing based on a check matrix made up of a block of a unit matrix and a plurality of blocks in which each row of the unit matrix is sequentially shifted and store threshold decision information of the data read from a memory section, an LLR conversion section configured to convert the threshold decision information to an LLR, an LMEM configured to store probability information ? calculated during iteration processing that repeatedly performs column processing and row processing based on the LLR in an iteration unit equal to or smaller than a size of the block, and a CPU core configured to transfer the probability information ? stored in the LMEM to the buffer every time the iteration processing in the iteration unit is completed.

Abstract: Various embodiments of the present invention provide systems and methods for a data processing system with failure recovery. For example, a data processing system is disclosed that includes a data processing circuit operable to process a block of data from an input and to yield a plurality of possible results based on the block of data, and an error detection circuit operable to test the plurality of possible results for errors and to report to the data processing circuit whether the plurality of possible results contain errors. The data processing system is operable to output any of the possible results in which the error detection circuit found no errors.

Abstract: A data processing system is disclosed including a low density parity check decoder with a variable node processor, a check node processor and a scaler circuit. The low density parity check decoder is operable to scale soft information with a scaling factor in the scaler circuit while iteratively generating and processing check node to variable node messages in the variable node processor and variable node to check node messages in the check node processor between a plurality of check nodes and variable nodes. The scaling factor is derived from a distribution of possible values in an input to the low density parity check decoder.

Abstract: Systems, methods, and other embodiments associated with LDPC decoder architectures are described. According to one embodiment, an apparatus includes a super-parity-check matrix that corresponds to at least a portion of a low density parity check (LDPC) code matrix. The super-parity-check matrix is coupled to a high throughput LDPC decoder and a low throughput LDPC decoder. The super-parity-check matrix includes n parity check matrices, each including x rows corresponding to x check node processing elements and y columns corresponding to y bit node processing elements. Thus, the super-parity-check matrix comprises nx rows and ny columns. The numbers n, x, and y are selected so that ny codeword can be processed in single time unit by the high throughput decoder and y codeword bits can be processed in a single time unit by the low throughput decoder.

Abstract: Determining a parameter associated with whether a portion of a storage device is defective is disclosed. Determining comprises: obtaining known data associated with the portion; reading back from the portion to produce a read-back waveform; decoding the read-back waveform, including producing statistical information; and determining a parameter associated with whether the portion is defective based at least in part on the statistical information.

Abstract: Various embodiments of the present invention are related to methods and apparatuses for decoding data, and more particularly to methods and apparatuses for multi-level layered LDPC decoding. For example, in one embodiment an apparatus includes a variable node processor and a check node processor. The variable node processor is operable to generate variable node to check node messages and to calculate perceived values based on check node to variable node messages. The check node processor is operable to generate the check node to variable node messages and to calculate checksums based on variable node to check node messages. The check node processor includes a min finder circuit operable to identify a minimum, a next minimum and an index of minimum value in the variable node to check node messages. The variable node processor and check node processor are operable to perform layered multi-level decoding.

Abstract: Various embodiments of the present inventions provide a symbol flipping LDPC decoding system. For example, a symbol flipping data processing system is disclosed that includes a low density parity check decoder operable to decode codewords and to identify unsatisfied parity checks, a symbol flipping controller operable to change values of at least one symbol in the codewords based on the unsatisfied parity checks to assist the low density parity check decoder to decode the codewords, a scheduler operable to control a decoding and symbol flipping mode in the low density parity check decoder and the symbol flipping controller, and a hard decision queue operable to store hard decisions for converged codewords from the low density parity check decoder.

Abstract: Systems and methodologies are described herein that facilitate Hybrid Automatic Repeat Request (H-ARQ) scheduling and coordination in a wireless communication system. As described herein, a network node capable of cooperation with other nodes for communication to respective users can coordinate a cooperation strategy across nodes based on a H-ARQ protocol to be utilized for a given user. In the case of a synchronous H-ARQ protocol, communication can be scheduled as described herein such that initial transmissions to a user are conducted cooperatively and re-transmissions are conducted without inter-node cooperation. In the case of a H-ARQ protocol utilizing persistent assignments, transmission intervals can be calculated and utilized based on application latency requirements, backhaul link latency, or other factors.

Abstract: A data processing method and a data re-transmission method in a broadband wireless access system are disclosed. A transmitting side generates a coded block set including coded blocks of a predetermined number and the coded blocks are transmitted to first and second base stations. The transmitting side sets a timer after transmitting a last coded block of the coded blocks. The coded blocks received by the second base station are transmitted to the first base station, and the transmitting side receives a control signal indicating whether there is a transmission error from the first base station.

Abstract: A method of decoding a received signal encoded with an LDPC code is provided. The method comprises initializing bits with an initial value of the received signal, obtaining posterior values of the bits by iteratively decoding the bits in a row direction and a column direction, determining on the basis of the posterior values whether an iterative decoding operation should be performed and comparing the posterior values with predetermined values and updating the initial value of the bits, when it is determined that the iterative decoding operation is be performed.