Abstract: A forward error correcting method in a multi protocol encapsulation-forward error correction (MPE-FEC) system, in which FEC modes are selected. The forward error correcting method includes comparing a number of received ERASUREs with a number of reference ERASUREs, selecting an ERASURE ONLY mode in which FEC is performed based on information about locations and sizes of errors, when the number of received ERASUREs is less than or equal to the number of reference ERASUREs, wherein the ERASURE ONLY mode is an FEC mode, selecting a NORMAL RS mode in which FEC is performed with respect to errors whose locations and sizes are not known, when the number of received ERASUREs is greater than the number of reference ERASURES, wherein the NORMAL RS mode is an FEC mode, and performing FEC in the selected FEC mode.

Abstract: A system and method for soft decision forward error correction (FEC) decoding may be used to determine a possible error in a differential detection signal, for example, in a DPSK system. The system and method uses the constructive and destructive signals from a demodulator to provide an error locating signal. Using the error locating signal, the system and method converts the differential detection signal into a soft decision signal including multi-level soft values.

Abstract: A method which makes use of the syndrome information at each iteration, combined with the bit reliability information available at a FEC decoder, to extract the minimum estimated bit error configuration, i.e. the block which is closest to the transmitted codeword during the decoding process, and to select such block if the result at the final decoding iteration has a higher number of estimated bit errors.

Abstract: Various embodiments of the present invention provide systems and methods for media defect detection. Data pre-processing is operable to pre-process a symbol based detected output to yield a suspect symbol indicator, and data detection is operable to provide a defect indicator corresponding to a probable defect identified based on the suspect symbol indicator.

Abstract: A probabilistic approach of symbol error estimation is disclosed. The probabilistic approach of symbol error estimation reflects the number of symbol errors more precisely than the number of unsatisfied checks. The more precise quality metric calculated in accordance with the present disclosure allows a codec system to achieve a better overall performance. In addition, many other features that previously depend on the number of unsatisfied checks as the sector quality metric may also benefit by adopting the more precise quality metric.

Abstract: A plurality of interpolated samples is generated. Using a plurality of soft-decision detectors, error correction decoding is performed on the plurality of interpolated samples in order to obtain a plurality of decisions. From the plurality of decisions, one is selected by determining which of the plurality of soft-decision detectors are able to come to a decision during error correction decoding. It is determined whether a majority of the detectors that are able to come to a decision come to a same decision. If not, a decision associated with a greatest reliability is selected from the decision detectors that are able to come to a decision.

Abstract: In one or more aspects, the present invention improves the efficiency of soft information transfer within a soft-value processing apparatus, by reducing in some sense the “amount” of soft information transferred between constituent processor circuits within the apparatus, without forfeiting or otherwise compromising the transfer of “valuable” soft information. In one example, the soft values produced by a constituent processor circuit are identified as being reliable or unreliable according to a reliability threshold. Some or all of the unreliable values are omitted from a soft value information transfer to another constituent processor circuit, or they are quantized for such transfer. The reduction in memory requirements for soft information transfer advantageously allows the use of lower power, less complex, and less expensive circuitry than would otherwise be required in the apparatus, which may be, as a non-limiting example, a Turbo receiver in a wireless communication device.

Abstract: Systems and methods are provided for decoding received codewords using an LDPC code. An LDPC post-processor is disclosed for performing post-processing when standard LDPC decoding fails due to a trapping set. The LDPC post-processor may direct the LDPC decoder to decode the received codeword again, but may change some of the inputs to the LDPC decoder so that the LDPC decoder does not fail in the same way. In one embodiment, the LDPC post-processor may modify the symbol positions in the received codeword that correspond to a particular unsatisfied check. In another embodiment, the LDPC post-processor may modify the messages in the decoder's iterative message algorithm that correspond to the symbol positions.

Abstract: A system and method for decoding data. Multi-dimensional encoded data may be received that potentially has errors. The multi-dimensional encoded data may encode each input bit in a set of input bits multiple times in multiple different dimensions to generate encoded bits. The encoded bits may be decoded in at least one of the multiple dimensions. If one or more errors are detected in a plurality of encoded bits in the at least one of the multiple dimensions, an intersection sub-set of the encoded data may be decoded that includes data encoding the same input bits encoded by the plurality of encoded bits in at least a second dimension of the multiple dimensions. The values of the input bits by decoding the intersection sub-set may be changed.

Abstract: An error correcting code decoding device includes a first decoding circuit, a word-length reduction circuit configured to reduce bit lengths of a first external values corresponding to a plurality of bits obtained after decoding process performed by the first decoding circuit a first predetermined number of times and to reduce bit lengths of words included in word string, and a second decoding circuit configured to decode the bit string by executing a decoding process a second predetermined number of times for calculating second external values and posterior values of the bits included in the bit string in accordance with the word string including the words having the reduced bit lengths using the first external values having the reduced bit lengths as second prior probabilities that corresponding bits among the plurality of bits are the predetermined value.

Abstract: A iterative decoding method for iteratively carrying out a decoding process for an encoded segmented and signal transmitted in a plurality of (Ncb) sub blocks for each predetermined block unit includes storing a number of (ncb) sub blocks smaller than the number (Ncb) of the sub blocks; and successively and iteratively carrying out a decoding process for each of the stored (ncb) sub blocks within a specified time period determined based on the number (ncb).

Abstract: Techniques for decoding repeated messages sent from a transmitter are improved with information obtained from the decoding of the first transmission and by augmenting Chase combining techniques with a voting-based combining method. In an example method, first encoded bits corresponding to a first instance of the repeated message and demodulated to obtain first soft bits, which are decoded to obtain first decoded bits. Second encoded bits corresponding to a second instance of the repeated message are demodulated to obtain second soft bits. The first decoded bits are re-encoded to obtain re-encoded bits. Sign values for modified soft bits are determined from sign values for the first soft bits, the sign values for the second soft bits, and the sign values for the re-encoded bits. The modified soft bits are combined with the first soft bits and decoded.

Abstract: Methods and systems for executing a code stream of non-native binary code on a computing system are disclosed. One method includes parsing the code stream to detect a plurality of elements including one or more branch destinations, and traversing the code stream to detect a plurality of non-native operators. The method also includes executing a pattern matching algorithm against the plurality of non-native operators to find combinations of two or more non-native operators that do not span across a detected branch destination and that correspond to one or more target operators executable by the computing system. The method further includes generating a second code stream executable on the computing system including the one or more target operators.

Abstract: A method for data storage includes storing data in analog memory cells by programming the memory cells with respective analog input values. After storing the data, respective analog output values are read from the memory cells using multiple read thresholds, which define multiple ranges of the analog output values. Respective numbers of read errors in the data, corresponding to the analog output values falling in the ranges, are assessed. The stored data is recovered based on respective numbers of the read errors assessed in the ranges.

Abstract: A DTV transmitting system includes an encoder, a randomizer, a block processor, a group formatter, a deinterleaver, and a packet formatter. The encoder codes enhanced data for error correction, permutes the coded data, and further codes the permuted data for error detection. The randomizer randomizes the coded enhanced data, and the block processor codes the randomized data at an effective coding rate of 1/H. The group formatter forms a group of enhanced data having data regions, and inserts the coded enhanced data into at least one of the data regions. The deinterleaver deinterleaves the group of enhanced data, and the packet formatter formats the deinterleaved data into corresponding data bytes.

Abstract: The present invention includes generating a tie-breaking metric via a comparative tie-breaking metric training process, monitoring an output of a channel detector in order to identify a tie condition between a first log-likelihood ratio (LLR) value and a second LLR value of a symbol, and upon identifying a tie condition between the first LLR value and the second LLR value of the symbol, applying the generated tie-breaking metric to the symbol in order to assign a hard decision to the symbol.

Abstract: Iterative demapper. Demodulation and/or demapping of a signal (e.g., based on a constellation whose points have a corresponding mapping with associated labels) is performed such that each dimension is processed separately without accounting for influences from the other dimension. For example, the demapping process operates on each respective dimension separately and independently. In some instances, the processing operates iteratively, in that, information identified from processing one of the dimensions is employed in directing the processing in another of the dimensions. Such operation may be performed iteratively by updating/modified information associated with one or more of the dimensions as well. Moreover, decoding may operate in accordance with iterative demapping (e.g., error correction code (ECC) and/or forward error correction (FEC) code by which information bits are encoded) to make estimates of bits within a signal sequence, and those estimates may be used in a subsequent iteration of demapping.

Abstract: Operational parameter adaptable LDPC (Low Density Parity Check) decoder. A novel means is presented by which LDPC coded signal can be decoded, and any one or more operational parameters can be adjusted during the decoding processing. For example, the original information extracted from a received LDPC coded signal (e.g., log likelihood ratios (LLRs)), can be modified during (or before) the iterative decoding processing performed in accordance with decoding an LDPC coded signal. Such modification of an operational parameter can include any one or combination of scaling, compression (and expansion/decompression), adding an offset to or subtracting an offset from, scaling, rounding, and/or some other modification of an operational parameter. The bit (or variable) edge messages and/or the check edge messages can also undergo modification during decoding processing.

Abstract: An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to generate (i) a plurality of symbols and (ii) a plurality of decision values both in response to detecting an encoded codeword. The second circuit may be configured to (i) generate a plurality of probabilities to flip one or more of the symbols based on the decision values, (ii) generate a modified probability by merging two or more of the probabilities of an unreliable position in the symbols and (iii) generate a decoded codeword by decoding the symbols using a list decode technique in response to the modified probability.

Abstract: The embodiments of the invention disclose a method and a device for decoding an RS code, the method comprising: receiving bit reliability information of the RS code output by a channel, performing a hard decision on the bit reliability information to obtain a hard-decision result value sequence; determining a type of an error of the hard-decision result value sequence according to an initial check array corresponding to an encoding mode of the RS code; according to preset corresponding relationships between types of errors of the hard-decision result value sequence and error-correcting modes capable of correcting the errors, determining an error-correcting mode corresponding to the type of the error of the hard-decision result value sequence, and performing a bit error correction on the hard-decision result value sequence according to the determined error-correcting mode; outputting the hard-decision result value sequence after the bit error correction as a decoding result.

Abstract: Computer-implemented methods and systems may perform one or more operations including, but not limited to: receiving input data from a source; applying an interleaving protocol to the input data to generate at least one component code word; decoding the at least one component codeword; determining a first convergence value of at least one decoded component codeword; computing extrinsic data associated with the at least one component codeword according to the first convergence of at least one component codeword; determining a second convergence value associated with the at least one component codeword according to the extrinsic data associated with the at least one component codeword.

Abstract: In one embodiment, a method for data communication may include receiving a first set of soft bit values in a Hybrid Automatic Repeat-Request (HARQ) buffer using a first bit width. The method may also include soft combining the first set of soft bit values with a second set of soft bit values to obtain a set of combined soft bit values. The method may also include transforming the set of combined soft bit values from the first bit width to a decoder input bit width to obtain a set of transformed soft bit values.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detector circuit, a biasing circuit, and a data decoder circuit. The data detector circuit is operable to apply a data detection algorithm to a series of symbols to yield a detected output, and the detected output includes a series of soft decision data corresponding to non-binary symbols. The biasing circuit is operable apply a bias to each of the series of soft decision data to yield a series of biased soft decision data. The data decoder circuit is operable to apply a data decoding algorithm to the series of biased soft decision data corresponding to the non-binary symbols.

Abstract: A log-likelihood ratio (LLR) for a bit bi in a message is determined by generating a first term, including by summing LLRs corresponding to bits in a first codeword having a specified value. The first codeword has a corresponding first message and bit bi of the first message corresponds to a 0. A second term is generated, including by summing LLRs corresponding to bits in a second codeword having the specified value. The second codeword has a corresponding second message and bit bi of the second message corresponds to a 1. The LLR for bit bi in the message is generated based at least in part on the first term and the second term.

Abstract: Systems and methods for acquiring a first set of information for a plurality of low density parity check (LDPC)-encoded data symbols, acquiring a second set of information for the plurality of LDPC-encoded data symbols, and selecting a window including a subset of the plurality of LDPC-encoded data symbols. The systems and methods include acquiring a decoder schedule having information for controlling the decoder, wherein the information in the decoder schedule includes decoding instructions based on a configuration of at least one of the first set of information and the second set of information. The systems and methods further include determining a likelihood of an error in the window using the decoding instructions in the decoder schedule, and updating the second set of information for selected data symbols of the subset based on the likelihood of an error in the window.

Abstract: Various embodiments of the present invention provide systems and methods for stochastic stream decoding of binary LDPC codes. For example, a data decoder circuit is discussed that includes a number of variable nodes and check nodes, with serial connections between the variable nodes and the check nodes. The variable nodes are each operable to perform a real-valued computation of a variable node to check node message for each neighboring check node. The check nodes are operable to perform a real-valued computation of a check node to variable node message for each neighboring variable node. The messages are passed iteratively between the variable nodes and the check nodes.

Abstract: A cost function is obtained. For each of a plurality of groups of nodes, the cost function is evaluated by obtaining, for a given group of nodes, one or more reliability values associated with the given group of nodes; the one or more reliability values include sign and magnitude. For a given group of nodes, a reliability value with a smallest magnitude is selected where the evaluated cost function for the given group of nodes is set to the smallest magnitude. One of the plurality of groups of nodes is selected based at least in part on the evaluated cost functions. Error correction decoding related processing is performed on the selected group of nodes.

Abstract: Data that are stored in cells of a multi-bit-per cell memory, according to a systematic or non-systematic ECC, are read and corrected (systematic ECC) or recovered (non-systematic ECC) in accordance with estimated probabilities that one or more of the read bits are erroneous. In one method of the present invention, the estimates are a priori. In another method of the present invention, the estimates are based only on aspects of the read bits that include significances or bit pages of the read bits. In a third method of the present invention, the estimates are based only on values of the read bits. Not all the estimates are equal.

Abstract: An optical receiving apparatus includes: an A/D converting circuit; a received-signal demodulating circuit that demodulates a received digital signal from the A/D converting circuit into an m-bit received signal; a soft-decision-data generating circuit that generates n-bit (n?m) soft-decision data based on the m-bit received signal; and an error correcting circuit that performs error correction based on the n-bit soft-decision data and outputs an error-corrected received signal. The soft-decision-data generating circuit generates soft-decision data of n bits (n=p+1) that corresponds to a determination result according to 2n?1 soft-decision thresholds, by using an MSB of the m-bit received signal as hard-decision data, and by using, as reliability information, a result of comparison between a plurality of bits (k bits, where k?m) on an MSB side of the m-bit received signal and a fixed threshold, or p bits (p?m?k) selected from (m?k) bits on an LSB side of the m-bit received signal.

Abstract: A termination indication is computed during an iteration of an iterative decoding of a representation of a codeword according to a schedule. The termination indication is tested to see if the decoding has converged or is not likely to converge. The testing of the termination indication shows convergence or lack of likelihood thereof even if a codeword bit estimate was flipped during an immediately preceding traversal of the schedule. Preferably, the termination indication includes an error correction syndrome weight, a zero value whereof indicates convergence, and the computing of the termination indication includes, in response to the flipping of a codeword bit estimate, flipping the error correction syndrome bits that are influenced by that codeword bit estimate.

Abstract: A wireless telecommunication system receiver is described comprising a demodulator adapted to demodulate a signal received from a source via a transmission channel to provide an error correction code word in the form of flexible or hard values, a decoder adapted to decode the code word, characterized in that it further comprises decision means adapted to receive an estimation of the fading coefficients of the channel during the transmission of the code word as well as an estimation of the noise variance or the signal to noise ratio, to deduce therefrom an estimation of the relative instantaneous mutual information to the channel, and to decide whether or not to inhibit the decoding of the code word by the decoder, according to whether the binary rate of transmission of the source is respectively greater than or less than a characteristic threshold of the instantaneous mutual information.

Abstract: According to at least one embodiment, a decoding apparatus includes an error correcting module and a change module. The error correcting module decodes for correcting error of encoded data using a low-density party check code and likelihood information. The change module changes a value of the likelihood information if the value of the likelihood information is continuously smaller than a predetermined value.

Abstract: Soft bit metric generation computational complexity can be reduced by identifying and utilizing only the dominant terms in a reliability calculation such as a logarithmic likelihood ratio (LLR). The dominant terms are those terms for which the signs of the x and y components match those of channel outputs of the channel outputs. One technique for identifying the dominant terms is by determining the most likely transitions from two consecutive channel output samples Values for the dominant terms can be estimated by either the joint reliability of two consecutive samples of the in-phase component (x1,x2) or by the joint reliability of two consecutive samples of the quadrature components (y1,y2).

Abstract: Disclosed herein is a decoding apparatus that performs soft-decision decoding on a linear block code, the apparatus including a hard-decision decoder configured to perform hard-decision decoding on a received word using a hard-decision decoding algorithm; and a soft-decision decoder configured to perform, using a soft-decision algorithm, soft-decision decoding merely on a received word for which the hard-decision decoder has failed in the hard-decision decoding.

Abstract: Apparatuses and methods for resolving trapping sets are provided. One example method can include attempting to decode a codeword using initial values for confidence levels associated with digits of the codeword. For a trapping set, the confidence levels associated with the digits corresponding to a failed parity check are adjusted. The method further includes attempting to decode a codeword using the adjusted value for the confidence levels of the digits corresponding to the failed parity check.

Abstract: Systems and methods are provided for implementing list decoding in a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. The soft-information can be organized into an order of combinations of error events for list decoding. An RS decoder can employ a list decoder that uses a pipelined list decoder architecture. The list decoder can include one or more syndrome modification circuits that can compute syndromes in parallel. A long division circuit can include multiple units that operate to compute multiple quotient polynomial coefficients in parallel. The list decoder can employ iterative decoding and a validity test to generate error indicators. The iterative decoding and validity test can use the lower syndromes.

Abstract: In an aspect, in general, a forward error correction algorithm (FEC) utilizes an FEC block structure in a manner that extends the effective error correction such that it can approach an “infinite” length to obtain benefits typical of very large FEC block size without the commensurate computation cost.

Abstract: A memory system comprises a non-volatile memory device that stores user data and state information regarding the user data. In a read operation of the non-volatile memory device, a memory controller calculates a priori probabilities for the user data based on the state information, calculates a posteriori probabilities based on the a priori probabilities, and performs a soft-decision operation to determine values of the user data based on the a posteriori probabilities.

Abstract: An iterative decoding device includes a decoder, a dual mode determination unit and a dual mode scaling unit. The decoder is utilized for receiving a set of soft information (SI) and iteratively decoding the set of SI and updating the set of SI accordingly to generate a set of updated SI. The dual mode determination unit is coupled to the decoder for generating a determination result according to the set of updated SI. The dual mode scaling unit is coupled to the dual mode determination unit and the decoder for scaling the set of updated SI according to the determination result to generate a set of scaled SI acting as an input of the decoder for next iteration.

Abstract: A multistage difference cyclic permutation unit (106) for performing multistage cyclic permutation, an address administration unit (104) for administering addresses of the cumulative LLR memory (101), a received value arrangement unit (103) for generating records during writing of received values to the cumulative LLR memory (101), and a control unit (110) for generating parameters to control each unit from information of a parity check matrix and the current cyclic permutation size are prepared. The address administration unit (104) controls reading/writing addresses of the cumulative LLR memory (101) based on a reading start address from the cumulative LLR memory (101) corresponding to the column block. After the start of reading of a column block, the control unit (110) generates a reading start address in the next decoding of the column block and stores it into the address administration unit (104).

Abstract: An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to generate (i) a plurality of symbols and (ii) a plurality of decision values both in response to detecting an encoded codeword. The second circuit may be configured to (i) generate a plurality of probabilities to flip one or more of the symbols based on the decision values, (ii) generate a modified probability by merging two or more of the probabilities of an unreliable position in the symbols and (iii) generate a decoded codeword by decoding the symbols using an algebraic soft-decision technique in response to the modified probability.

Abstract: A system and method for using a cyclic redundancy check (CRC) to evaluate error corrections. A set of data and initial CRC values associated therewith may be received. The set of data by changing a sub-set of the data may be corrected. Intermediate CRC values may be computed for the entire uncorrected set of data in parallel with said correcting. Supplemental CRC values may be computed for only the sub-set of changed data after said correcting. The intermediate and supplemental CRC values may be combined to generate CRC values for the entire corrected set of data. The validity of the corrected set of data may be evaluated by comparing the combined CRC values with the initial CRC values.

Abstract: A method and apparatus of selecting N metrics among M metrics is provided. The apparatus determines M metrics P(i), where i=1, . . . , M. Each P(i) is represented by B bits. The apparatus determines N metrics among M metrics. The complexity for configuring the circuit is decreased, and the length of the critical path is reduced.

Abstract: A wireless device for implementing Incremental Redundancy (IR) operations includes system processing circuitry operable to perform Physical (PHY) layer operations, Media Access Control (MAC) layer operations and Radio Link Control (RLC) operations of the wireless device. The system processing circuitry further includes an IR control module for processing IR transactions related to a received RLC data block and for tracking an Automatic Repeat Request (ARQ) receiving state and received block bit map and a Layer 1 (L1) module for intercepting and diverting the IR transactions to the IR control module and for passing a correctly decoded RLC data block to the RLC layer operations via the MAC layer operations thereby automatically synchronizing the RLC layer operations. An IR processing module is coupled to the system processing circuitry to perform IR operations on the received RLC data block based upon a direction from the IR control module.

Abstract: A memory controller analyzes read data received from a memory device and first error correction code (ECC) data of the read data. A control unit generates a plurality of sub-data from write data to be written in the memory device where the number of error bits in the read data is greater than a number of error bits that can be corrected using the first ECC data. An ECC block generates the first ECC data and second ECC data by using substantially the same algorithm to correct errors in each of the sub-data. The control unit transmits each of the sub-data, the first ECC data and the second ECC data to the memory device.

Abstract: A method of data classification for use in a wireless communication system includes obtaining decoder metrics from a decoder. The decoder metrics correspond to data generated by the decoder. The decoder metrics include a symbol error rate (SER) and an energy metric (EM). The method also includes classifying the data into a first category if the data fails a cyclic redundancy check (CRC) check, into a second category if the data passes the CRC check and is determined to be unreliable, or into a third category if the data passes the CRC check and is determined to be reliable. A reliability of the data is determined based on the decoder metrics and an EM threshold.

Abstract: Systems and methods for processing and decoding TCM/BCM-coded signal vectors. A multi-dimensional signal vector is received by, for example, a TCM or BCM decoder. The TCM/BCM decoder identifies the closest signal points in the signal constellation set, or “nearest neighbors,” for each dimension of the received signal vector. The TCM/BCM decoder then forms a test set that includes a plurality of multi-dimensional test vectors, where each dimension of each test vector is based on an identified nearest neighbor. In particular, each test point in the test set is based on a different combination of the nearest neighbors. The TCM/BCM decoder can compute branch metrics based on only the test points in the test set, and can make detection decisions using the computed branch metrics.

Abstract: A method uses a set of reference symbols. The method includes receiving a first symbol, comparing the first symbol to the set of reference symbols, and selecting a reference symbol from the set of possible reference symbols. The set of reference symbols are adjusted by a set of respective error factors for each of the reference symbols. The reference symbol is selected when it matches the first symbol. The method also includes adjusting the respective error factor for the reference symbol in accordance with a difference between the first symbol and a remodulated reference symbol in one embodiment.

Abstract: A low power Chien searching method employing Chien search circuitry comprising at least two hardware components that compute at least two corresponding bits comprising a Chien search output, the method comprising activating only a subset of the hardware components thereby to compute only a subset of the bits of the Chien search output; and activating hardware components other than those in the subset of hardware components, to compute additional bits of the Chien search output other than the bits in the subset of bits, only if a criterion on the subset of the bits of the Chien search output is satisfied.

Abstract: A storage device comprises a nonvolatile memory device comprising a plurality of memory cells, and an error correction circuit configured to receive primary data and secondary data from the nonvolatile memory device and to perform a hard decision decoding operation on the primary data and further configured to perform a soft decision decoding operation on the primary data based on the secondary data. The primary data is read from the plurality of memory cells in a hard decision read operation and the secondary data is read from memory cells programmed to a specific state from among the primary data.