Abstract: Power-saving and area-efficient BCH coding systems are provided that employ hybrid decoder architectures. The BCH decoder architectures comprise both special-purpose hardware and firmware, thereby taking advantage of both the speed of special-purpose hardware and the energy-efficiency of firmware. In particular, the error correction capabilities of the BCH decoders provided herein are split between a hardware component designed to correct a single error and a firmware component designed to correct the remaining errors. In this manner, firmware operation is bypassed in situations where only one error is present and the complexity of the necessary hardware is significantly reduced.

Abstract: Error correction is selectively applied to data, such as repair data to be stored in a fusebay for BIST/BISR on an ASIC or other semiconductor device. Duplicate bit correction and error correction code state machines may be included, and selectors, such as multiplexers, may be used to enable one or both types of correction. Each state machine may include an indicator, such as a “sticky bit,” that may be activated when its type of correction is encountered. The indicator(s) may be used to develop quality and yield control criteria during manufacturing test of parts including embodiments of the invention.

Abstract: Methods and means of error correction code (ECC) debugging may comprise detecting whether a bit error has occurred; determining which bit or bits were in error; and using the bit error information for debug. The method may further comprise comparing ECC syndromes against one or more ECC syndrome patterns. The method may allow for accumulating bit error information, comparing error bit failures against a pattern, trapping data, counting errors, determining pick/drop information, or stopping the machine for debug.

Abstract: The invention provides a method for decoding an error correction code. First, an error syndrome of the error correction code is calculated. A plurality of coefficients of an error locator polynomial of the error correction code is then sequentially determined according to the error syndrome. When a new coefficient of the error locator polynomial is determined, it is also determined whether the new determined coefficient is equal to zero. When the new determined coefficient is equal to zero, a speculated error locator polynomial is built according to a plurality of low-order-term coefficients of the error locator polynomial, wherein the orders of the low-order-term coefficients are lower than that of the new determined coefficient. A Chien search is then performed to determine a plurality of roots of the speculated error locator polynomial. The error correction code is then corrected according to the roots of the speculated error locator polynomial.

Abstract: A termination indication is computed during an iteration of an iterative decoding of a representation of a codeword according to a schedule. The termination indication is tested to see if the decoding has converged or is not likely to converge. The testing of the termination indication shows convergence or lack of likelihood thereof even if a codeword bit estimate was flipped during an immediately preceding traversal of the schedule. Preferably, the termination indication includes an error correction syndrome weight, a zero value whereof indicates convergence, and the computing of the termination indication includes, in response to the flipping of a codeword bit estimate, flipping the error correction syndrome bits that are influenced by that codeword bit estimate.

Abstract: Defining a set of correctable error and uncorrectable error syndrome code points, generating an error correction code (ECC) syndrome decode, regarding the uncorrectable error syndrome code points as “don't cares” and logically minimizing the ECC syndrome decode for the determination of the correctable error syndrome code points based on the regarding of the uncorrectable error syndrome code points as the “don't cares” whereby output data can be ignored for the uncorrectable error syndrome code points.

Abstract: The present invention discloses a method and apparatus for performing forward error correction with a multi-dimensional Bose Ray-Chaudhuri Hocquenghem (BCH) product code, and a method for detecting false decoding errors in frame-based data transmission systems.

Abstract: The invention is intended to curtail the circuit scale of the error correction circuit of a flash memory.

Abstract: An encoder structure for an error correcting code with arbitrary parity positions is presented. The invention is effective for all error correcting codes whose parity check matrix is of the Vandermonde type. In contrast to conventional encoder circuits, the parity symbols produced by this encoder are not restricted to form a block of consecutive parity symbols at the beginning or at the end of a codeword, but may be spread arbitrarily within the codeword. A general structure of the parity check matrix for such a code is found by exploiting the special Vandermonde structure of matrices. From this general parity check matrix, an expression for the evaluation of the parity symbols in terms of a polynomial with limited degree is derived. An efficient hardware implementation of the proposed encoder is suggested.

Abstract: A decoder includes multiple decoder stages and a controller. The decoder stages perform decoding operations with respect to a received signal using corresponding different decoding algorithms. The controller determines whether the decoding operation performed by one of the decoder stages with respect to the received signal is successful, and controls the decoding operation of each of the other decoder stages in response to a result of the determination.

Abstract: Systems and methods are provided for enhancing the performance and throughput of a low-density parity check (LDPC) decoder. In some embodiments, the enhanced performance and throughput may be achieved by detecting and correcting near-codewords before the decoder iterates up to a predetermined number of iterations. In some embodiments, a corrector runs concurrently with the decoder to correct a near-codeword when the near-codeword is detected. In alternate embodiments, the corrector is active while the decoder is not active. Both embodiments allow for on-the-fly codeword error corrections that improve the performance (e.g., reducing the number of errors) without decreasing the throughput of the decoder.

Abstract: A flash memory device using an error correction code (ECC) algorithm and a method of operating the same. The device includes a memory cell array including a error correction code (ECC) block including data memory cells configured to store data and a parity cell configured to store a first parity code, a parity controller configured to generate a second parity code based on a the current operating mode of the flash memory device, and an error correction unit configured to receive one of the first and second parity codes and to perform an ECC algorithm on the data stored in the data memory cells using the received parity code. A control logic restarts an erase operation on an erroneously unerased data memory cell or prevents the erase operation from being restarted based on the number of erroneous bits per ECC block.

Abstract: A memory system accesses a block of data, each block including bits logically divided into rows and columns, each column including a row-checkbit column, an inner-checkbit column, and data-bit columns. Each column is stored in a different memory component, and checkbits are generated from databits to provide block-level correction for a failed memory component, and double-error correction for errors in different memory components. The system calculates a row syndrome and an inner syndrome for the block of data, the inner syndrome resulting from any two-bit error in the same row being unique. The system can use the row and inner syndromes to determine whether errors are associated with a failed memory component. If not, the system can use the row and inner syndromes, and inner syndromes for all possible combinations of one-bit errors occurring in two rows with a row syndrome of one to correct two bits.

Abstract: A Euclid processing module for obtaining an error locator polynomial of a binary BCH code in an error correction decoding circuit, in which error corrections of words are performed, includes registers, a shifter, a zero insertion unit, selectors and a sequencer. Coefficients of polynomials Ri (z) and Bi (z) stored in the registers are subjected to Galois field calculations by the processing module. Results of the calculations and the data of the registers are shifted by the shifter. Some of the coefficients are erased by the zero insertion unit and stored in registers by controlling the selectors with the sequencer. A necessary polynomial ? (z) is calculated by repeated processing of the processing module. The Euclid processing module decreases a logic scale and simplifies controlling logic in a state of small latency and high operating frequency.

Abstract: An ECC circuit can operate in a plurality of error correction modes with different correcting capabilities for data stored in a memory. The ECC circuit calculates a syndrome with respect to information data in accordance with an error correction mode set by a control part and adds a syndrome of a fixed length in which dummy bits are added to the calculated syndrome, to the information data. When code data is read out, the ECC circuit performs a correction process on the code data by using the syndrome included in the code data.

Abstract: A processing arrangement of a data communication apparatus is arranged to derive an ordered plurality of modulo-2 summations of respective selections of data bits of a binary data set. The data communication apparatus may either be transmitting apparatus with the processing arrangement serving to determine a target syndrome for subsequent use in error correction, or receiving apparatus with the data processing arrangement being arranged to effect error correction of received data. The processing arrangement effects its selections of bits from the binary data set in accordance with the interconnection of nodes in a logical network of nodes and edges that together define at least a continuum of cells covering a finite toroid. The structuring provided to bit selection by this continuum can be offset by randomness provided by other structures of the network and by the random association of bits of the binary data set with the nodes of the continuum.

Abstract: According to one embodiment a computer system is disclosed. The computer system includes memory. The memory includes two or more rows, where each row has a plurality of memory devices. The computer system also includes a chipset. The chipset includes a detection/correction circuit to detect single and double symbol errors and correct single symbol errors for each memory row, and markers to maintain a log of errors within each memory row.

Abstract: Methods for Error Correction Code (ECC) decoding include producing syndromes from a set of bits, which represent data that has been encoded with the ECC. An Error Locator Polynomial (ELP) is generated based on the syndromes. At least some of the ELP roots are identified, and the errors indicated by these roots are corrected. Each syndrome may be produced by applying to the bits vector operations in a vector space. Each syndrome is produced by applying vector operations using a different basis of the vector space. The ELP may be evaluated on a given field element by operating on ELP coefficients using serial multipliers, wherein each serial multiplier performs a sequence of multiplication cycles and produces an interim result in each cycle. Responsively to detecting at least one interim result indicating that the given element is not an ELP root, the multiplication cycles are terminated before completion of the sequence.

Abstract: A syndrome generator generates odd syndromes of a sequence of syndromes and stores the odd syndromes in registers. A syndrome sequencer identifies the register storing the next syndrome of the sequence of syndromes, reads the syndrome from the register, and outputs the syndrome to a sequential polynomial generator. Further, the syndrome sequencer generates an even syndrome by squaring the syndrome read from the register and writes the even syndrome into the same register. Moreover, the syndrome sequencer outputs each syndrome of the sequence of syndromes in sequential order. The sequential polynomial generator generates a locator polynomial in a number of iterations based on the sequence of syndromes received from the syndrome sequencer.

Abstract: Encoder and decoder apparatus and methods derive a plurality of parity bits from a single codeword. Encoder apparatus may include a receive module receiving a data stream, a parity generation module generating a plurality of parity bits based on the data stream and a word of a tensor-product code, and a parity insertion module combining the plurality of parity bits and the data stream to generate encoded bits. Decoder apparatus may include a detector receiving and outputting encoded data, a first decoder generating first log-likelihood ratios (LLRs) from the encoded data, an error recovery module generating second LLRs from the encoded data, a second decoder that derives syndrome data from the first and second LLRs, a post-processor that combines data from the first decoder with error events from the error recovery module to generate corrected data, the post-processor further identifying a plurality of parity bits in the corrected data.

Abstract: A method which makes use of the syndrome information at each iteration, combined with the bit reliability information available at a FEC decoder, to extract the minimum estimated bit error configuration, i.e. the block which is closest to the transmitted codeword during the decoding process, and to select such block if the result at the final decoding iteration has a higher number of estimated bit errors.

Abstract: Methods of error correction code (ECC) debugging may comprise detecting whether a bit error has occurred; determining which bit or bits were in error; and using the bit error information for debug. The method may further comprise comparing ECC syndromes against one or more ECC syndrome patterns. The method may allow for accumulating bit error information, comparing error bit failures against a pattern, trapping data, counting errors, determining pick/drop information, or stopping the machine for debug.

Abstract: Disclosed is an error correcting method which includes detecting an error of meta data having a seed used to randomize user data; correcting the error of the meta data when the error is detected from the meta data; receiving the user data based upon seed confirmation information associated with an error existence of the seed or an error correction result of the seed; detecting an error of the user data; and correcting the error of the user data when the error is detected from the user data.

Abstract: An apparatus for error checking is described. The apparatus includes a matrix having a plurality of bit position columns and rows, where the bit position columns are equal in number to data bits of a word length, the word length for a word serial transmission of a data vector, where the bit position columns are one each for each data bit. The bit position rows are equal in number to syndrome bits, and the bit position rows are one each for each syndrome bit. A portion of the bit position columns are allocated to parity bits for a selected word of the data vector, where the portion of the bit position columns for the selected word are one each for each parity bit allocated to the selected word.

Abstract: A decoder is disclosed that can reduce power consumption at different stages of a decoding process. At a first stage where the decoder calculates residual values, the decoder can reduce power consumption by calculating residual values using less than a full set of division circuits. A reduced number of division circuits may be sufficient to successfully calculate residuals associated with the codeword to complete the decoding process. Division circuits that are not used may be disabled to reduce power consumption. At another stage of the decoding process where the decoder generates coefficients that are used to identify locations of errors in the codeword, the decoding process can limit power consumption by reducing the number of iterations of a polynomial generator by incorporating termination decision circuitry.

Abstract: A QC-LDPC decoding system employing a trapping set look-up table is provided. The QC-LDPC decoding system includes an iterative decoder that utilizes a message-passing algorithm to decode a received codeword. If the iterative decoder fails to produce a valid codeword, additional processing is performed to decode the received codeword. The additional processing includes the steps of computing the syndrome pattern of the received codeword, searching the look-up table for a trapping set class that is responsible for the iterative decoder's failure, retrieving from the look-up table a syndrome pattern and an error pattern of a member of the responsible trapping set class, and calculating the error pattern of the received codeword based on its syndrome pattern and the information retrieved from the look-up table. The received codeword is then corrected based on its error pattern.

Abstract: An error correction decoder includes a syndrome computation circuit, an error correction and computation circuit and an error correction circuit. The syndrome computation circuit calculates a syndrome of read data. The error correction and computation circuit calculates a location of a single-bit error using a division operation between elements of the syndrome when the single-bit error exists in the read data. The error correction circuit corrects the single-bit error of the read data based on the location of the single-bit error.

Abstract: Systems and methods are provided for implementing various aspects of a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. If the decision-codeword corresponds to an inner code and an RS code is the outer code, a soft-information map can process the soft-information for the decision-codeword to produce soft-information for a RS decision-codeword. A RS decoder can employ the Berlekamp-Massey algorithm (BMA), list decoding, and a Chien search, and can include a pipelined architecture. A threshold-based control circuit can be used to predict whether list decoding will be needed and can suspend the list decoding operation if it predicts that list decoding is not needed.

Abstract: There is disclosed a memory device with an error detection and correction system formed therein, the error detection and correction system being configured to detect and correct errors in read out data by use of a BCH code, wherein the error detection and correction system is 4-bit error correctable, and searches error locations in such a way as to: divide an error location searching biquadratic equation into two or more factor equations; convert the factor equations to have unknown parts and syndrome parts separated from each other for solving them; and compare indexes of the solution candidates with those of the syndromes, the corresponding relationships being previously obtained as a table, thereby obtaining error locations.

Abstract: A method to generate an erasure locator polynomial in an error-and-erasure decode. The method generally includes the steps of (A) storing current values in multiple registers at a current moment, (B) generating first values by multiplying each current value by a respective one of multiple constants, (C) generating second values by gating at least all but one of the first values with a current one of multiple erasure values of an erasure position vector, (D) generating next values by combining each one of the second values with a corresponding one of the first values, (E) loading the next values into the registers in place of the current values at a next moment and (F) generating an output signal carrying the current values at a last moment such that the current values form the coefficients of the erasure locator polynomial.

Abstract: An error correction code (ECC) decoder processing data read from a storage media includes a plurality of processing elements for detecting an error in at least one of a plurality of channel data, wherein the plurality of channel data is received via a plurality of channels, and wherein the plurality of processing elements are driven independently from the plurality of channels

Abstract: Error detection and error location determination circuitry is provided for detecting and locating soft errors in random-access-memory arrays on programmable integrated circuits. The random-access-memory arrays contain rows and columns of random-access-memory cells. Some of the cells are loaded with configuration data and produce static output signals that are used to program associated regions of programmable logic. Cyclic redundancy check error correction check bits are computed for each column of an array. The cyclic redundancy check error correction check bits are stored in corresponding columns of cells in the array. During normal operation of an integrated circuit in a system, the cells are subject to soft errors caused by background radiation strikes. The error detection and error location determination circuitry uses parallel processing to continuously monitor the data to identify the row and column location of each error.

Abstract: Embodiments of an invention for verifying firmware using system memory error check logic are disclosed. In one embodiment, an apparatus includes an execution core, firmware, error check logic, non-volatile memory, comparison logic, and security logic. The error check logic is to generate, for each line of firmware, an error check value. The comparison logic is to compare stored error check values from the non-volatile memory with generated error check values from the error check logic. The security logic is to prevent the execution core from executing the firmware if the comparison logic detects a mismatch between the stored error code values and the generated error code values.

Abstract: In a particular embodiment, a forward error correction (FEC) decoder is disclosed that includes an input responsive to a communication channel to receive sampled bits from a continuous bit stream. The circuit device further includes a logic circuit to alternately provide sets of the received sampled bits from the continuous bit stream to one of a first syndrome generator and a second syndrome generator to correct errors in the sets of sampled bits to produce a decoded output related to the continuous bit stream.

Abstract: The subject matter disclosed herein provides an outer coding framework for reducing the correlation between packet errors in a wireless network. In one aspect, there is provided a method. The method may include receiving a packet including information. The received packet may be encoded using a forward error correction code to provide at least one, but no more than two, codewords. At least a portion of each codeword may be inserted into a transport packet for transmission to a client station, wherein the transport packet comprises information from at least one, but no more than two, of the codewords. The transport packet may be sent. Related systems, apparatus, methods, and/or articles are also described.

Abstract: Systems and methods for identifying error bits in encoded data are disclosed. As a part of identifying error bits, encoded data that is provided from a data source and that includes data and parity check portions is accessed. Based on the encoded data, syndromes are calculated, and based on the calculated syndromes, an equation is determined. The roots of the equation are determined and based on the determined roots of the equation, one or more error bits are identified. The error bits are identified using a circuit that presents a binary representation of the roots. The error bits are corrected based on the error bits that are identified.

Abstract: According to one embodiment, a data storage device includes a read module, an ECC module, and a controller. The read module is configured to read data to be accessed and designation data designating the data, from nonvolatile memories. The ECC module is configured to perform an error check and correction process on the data and designation data read by the read module. The controller is configured to correct the designation data if the ECC module cannot correct the designation data and to perform an error detection process based on the designation data corrected.

Abstract: A decoding method of a cyclic code decoder includes the machine-implemented steps of: establishing a lookup table; receiving a codeword; computing a syndrome and a Hamming weight; if the Hamming weight is not equal to zero and not greater than an error correcting capability value, performing a first error correcting operation; if the Hamming weight is greater than the error correcting capability value, and if the syndrome has a matching syndrome pattern in the lookup table, performing a second error correcting operation; if a second Hamming weight corresponding to a syndrome difference is smaller than a check value, performing a third error correcting operation, otherwise performing a fourth error correcting operation; and if a counter value is greater than zero, performing a fifth error correcting operation before decoding a corrected codeword.

Abstract: Code designs for channel coding with side information (CCSI) based on combined source-channel coding are disclosed. These code designs combine trellis-coded quantization (TCQ) with irregular repeat accumulate (IRA) codes. The EXIT chart technique is used for IRA channel code design (and especially for capacity-approaching IRA channel code design). We emphasize the role of strong source coding and endeavor to achieve as much granular gain as possible by using TCQ. These code designs synergistically combine TCQ with IRA codes. By bringing together TCQ and EXIT chart-based IRA code designs, we are able to approach the theoretical limit of dirty-paper coding.

Abstract: For algebraic single symbol error correction and detection, a method is proposed which achieves correcting single symbol errors at unknown positions within codewords, identifying cases where multiple symbols within a codeword are uncorrectably corrupted, and identifying cases where a single symbol within a codeword is uncorrectably corrupted. The method comprises the steps of calculating a syndrome of a received word, splitting the syndrome into two parts, checking 3 integer weight quantities calculated from the two syndrome parts, converting the syndrome into a vector of integer valued “orthogonal bit error weights” associated to the received bits, and toggling those bits of the received word, where the associated “orthogonal bit error weight” is in the upper half of its possible value range.

Abstract: An error-correction code is generated on a line-by-line basis of the physical logic register and latch contents that store encoded words within a processor just before the processor is put into sleep mode, and later-generated syndrome bits are checked for any soft errors when the processor wakes back up, e.g., as part of the power-up sequence.

Abstract: A wireless communication device is provided to make it possible to detect errors with high accuracy while to suppress reduction in throughput in the case that an LDPC (Low-Density Parity-Check) code is used for an error correcting code. In the wireless communication device, a CRC (Cyclic Redundancy Check) coding unit (101) for carrying out a CRC coding of a part of a transmitting bit sequence in accordance with a row weight of an examination matrix of the LDPC code, an LDPC coding unit (102) for carrying out the LDPC coding and generating LDPC coding data by using the same examination matrix as used for the LDPC coding carried out in the CRC coding unit (101).

Abstract: In one embodiment, an apparatus includes a check/correct circuit coupled to a control circuit. The check/correct circuit is coupled to receive a block of data and corresponding check bits. The block of data is received as N transmissions, each transmission including M data bits and L check bits. The check/correct circuit is configured to detect one or more errors in each of a plurality of non-overlapping windows of K bits in the M data bits, responsive to the M data bits and the L check bits. The control circuit is configured to record which of the plurality of windows have had errors detected and, if a given window of the plurality of windows has had errors detected in each of the N transmissions of the block, the control circuit is configured to signal a device failure. Each of K, L, M, and N are integers greater than one.

Abstract: The Error Correction Code (ECC) circuit generates the first syndrome of write data, which have not been written to the memory. The Error Detection Code (EDC) circuit generates the second syndrome of verification read data, which have been written to the memory. The EDC circuit detects errors due only to the “read disturb phenomenon” using the second syndrome, the errors occurring in data scanned from the memory. The ECC circuit detects and corrects errors due to the “program disturb phenomenon” and the “read disturb phenomenon” using the first syndrome, the errors occurring in the data in which the errors due only to the “read disturb phenomenon” have been detected. As a result, both the circuit size and the processing time can be reduced.

Abstract: A syndrome calculator receives an input codeword and calculates a first set of syndromes. A syndrome transform receives the first set of syndromes having and determines a second set of syndromes. The second set of syndromes is based on the first set of syndromes. The second set of syndromes has number of syndromes that is less than the number of syndromes in the first set of syndromes. A key equation solver receives the second set of syndromes and produces an indication of zero or more error locations and an indication of zero or more error values.

Abstract: Circuitry and methods can be provided to correct errors in decision bits. A plurality of error event syndromes can be computed for a first plurality of error events. For each of a plurality of error event syndromes, two best error events can be selected. A cross-syndrome second best error event can be selected from among the first plurality of error events. A global second best error event can be selected from among the cross-syndrome second best error event and the second best per-syndrome error events. A second plurality of error events can be selected from among the global second best error event and the best per-syndrome error events. The second plurality of error events can be used for data post-processing.

Abstract: A memory device includes an error detection and correction system with an error correcting code over GF(2n), wherein the system has an operation circuit configured to execute addition/subtraction with modulo 2n?1, and wherein the operation circuit has a first operation part for performing addition/subtraction with modulo M and a second operation part for performing addition/subtraction with modulo N (where, M and N are integers which are prime with each other as being obtained by factorizing 2n?1), and wherein the first and second operation parts perform addition/subtraction in parallel to output an operation result of the addition/subtraction with modulo 2n?1.

Abstract: An encoder creates an (p,k,n) n-state codeword with p n-state symbols of which k n-state symbols are data symbols, an n-state symbol being represented by a signal with n>2, p>2 and k>(p?k). Intermediate states of an encoder in forward and in reverse direction are provided in a comparative n-state expression and implemented on a processor. A plurality of signals representing a codeword with at least one n-state symbol in error is processed by the processor by evaluating the comparative n-state expression. A partial result of an expression is determined after a symbol has been received. An error location and an error magnitude are determined. The error is corrected by the processor.

Abstract: An invention is provided for parallel ECC error location in a memory. The invention includes partitioning a set of field elements into w partitions. Then, for each of the w partitions of field elements, i) providing a set of r different field elements of the partition to r parallel search element. Next, in operation ii), each parallel search element computes a sum that is based on a set of coefficients of an error locator polynomial and the field element provided to the particular parallel search element. The set of field elements is advanced r field elements in GF(2m), and operations i) through iii) are repeated using the next r different field elements of the partition.

Abstract: Systems and methods are provided for performing error correction decoding. The coefficients of the error locator polynomial are iteratively determined for each codeword using a modular implementation of a single recursion key-equation solver algorithm. According to this implementation, modules are used to calculate the current and previous coefficients of the error locator polynomial. One module is used for each correctable error. The modular single recursion implementation is programmable, because the number of modules can be easily changed to correct any number of correctable errors. Galois field tower arithmetic can be used to calculate the inverse of an error term. Galois field tower arithmetic greatly reduces the size of the inversion unit. The latency time can be reduced by placing the computations of the inverse error term outside the critical path of the error locator polynomial algorithm.