Abstract: Various embodiments of the present invention provide systems and methods for encoding data. As an example, a data encoding circuit is disclosed that includes a first stage data encoder circuit and a second stage data encoder circuit. The first stage data encoder circuit is operable to provide a first stage output. The first stage data encoder circuit includes a first vector multiplier circuit operable to receive a data input and to multiply the data input by a first sparse matrix to yield a first interim value. The second stage encoder circuit includes a second vector multiplier circuit operable to multiply the first stage output by a second sparse matrix to yield a second interim value.

Abstract: Disclosed is a method and system of determining a data block of a RAID level 6 stripe that has corrupted or incorrect data. For each data block of the stripe, a reconstructed data block is created using the other data blocks and the P syndrome data block. The reconstructed data block and the other data blocks are used to create a new Q syndrome data block. The new Q syndrome data block and the stored Q syndrome data block are compared. If the new Q syndrome data block and the stored Q syndrome data block match, the data block is marked as being suspected as having corrupted or incorrect data. This process is repeated for every data block in the stripe. If there is only a single suspected data block, the reconstructed data block is stored as a replacement of the suspect data block in the stripe.

Abstract: A broadcast transmitting system and a method of processing broadcast data in the broadcast transmitting system are disclosed. Herein, the broadcast transmitting system includes a block processor for encoding mobile service data at a coding rate of 1/H, a group formatter for mapping the encoded mobile service data into at least one region of a data group that has a plurality of regions, wherein the data group further includes a plurality of known data sequences, a trellis encoder for trellis encoding data being outputted from the group formatter, the trellis encoder having at least one memory that is initialized at a start of each known data sequence, a multiplexer for multiplexing the trellis-encoded data with segment synchronization data and field synchronization data, and a modulator for modulating a broadcast signal including the multiplexed data.

Abstract: A hard input low density parity check decoder is provided that shares logic between a bit-flipping decoder and a syndrome calculator. The hard-decision decoder decodes one or more error-correcting (EC) codewords and comprises a bit-flipping decoder that flips one or more bit nodes connected to one or more unsatisfied parity checks; and a syndrome calculator that performs a parity check to determine whether the bit-flipping decoder has converged on a valid codeword, wherein the bit-flipping decoder and the syndrome calculator share one or more logic elements. The decoder optionally includes means for updating a parity check equation of each flipped bit. Error-correcting (EC) codewords are decoded by flipping one or more bit nodes connected to one or more unsatisfied parity checks; and updating one or more parity check equations associated with the one or more bit nodes each time the one or more bit nodes are flipped. The parity check equations are updated whenever a bit is updated.

Abstract: Error detection and error location determination circuitry is provided for detecting and locating soft errors in random-access-memory arrays on programmable integrated circuits. The random-access-memory arrays contain rows and columns of random-access-memory cells. Some of the cells are loaded with configuration data and produce static output signals that are used to program associated regions of programmable logic. Cyclic redundancy check error correction check bits are computed for each column of each array. The error correction check bits are stored in corresponding columns of cells in the array. During normal operation of an integrated circuit in a system, the cells are subject to soft errors caused by background radiation strikes. The error detection and error location determination circuitry contains linear feedback shift register circuitry that processes columns of array data. The circuitry continuously processes the data to identify the row and column location of each error.

Abstract: Cyclic redundancy check (CRC) processing is applied to a received sequence of data blocks that are defined by respective sequences of sets of parallel data. For each data block, there is produced a sequence of syndromes that respectively correspond to the sets of parallel data within the data block. The final syndrome in the sequence of syndromes corresponds to all of the data in the data block. The time required for CRC processing can be reduced by concurrently producing first and second ones of the syndromes that respectively correspond to first and second ones of the sets that are respectively contained in first and second ones of the data blocks.

Abstract: An error correction and/or error detection method reads of stored information data from a storage device; wherein in addition to the information data, code data is read from the storage device. Syndrome data is formed from the information data and the code data in order to determine errors and/or error positions in the read data. For detection of multiple errors, it is verified whether in the case of a determined error position, the information data or code data associated with the relevant storage positions are either all equal to 0, or are all equal to 1.

Abstract: The present invention relates to a method for analyzing a decoded digital signal stream. The method comprises decoding an encoded digital signal stream to obtain a decoded digital stream and terminating the decoding operation in an N dimension, wherein N is an integer greater than one. The method further comprises calculating one or more syndromes in a dimension not comprising the N dimension of the decoded digital signal stream. At least one invalid syndrome is then detected from the one or more calculated syndromes. In one embodiment, an error is reported in the decoded digital stream based upon detecting at least one invalid syndrome.

Abstract: An error correction decoder includes a syndrome generator and an error correction value generator. The syndrome generator is operable to generate a plurality of syndromes based upon a received signal generated according to a generator polynomial. The error correction value generator is operable to generate a plurality of product values. Each of the product values is generated for one of the syndromes based upon a respective power of the roots of the generator polynomial. The respective power is determined based upon a respective index corresponding to one of the syndromes to be considered and unit positions of the received signal. The error correction value generator is further operable to generate an error correction value according to the product values, and to provide an error correcting device coupled thereto with the error correction value for correcting an error of the received signal.

Abstract: A circuit and technique for reducing parity bit-widths for check bit and syndrome generation is implemented through the use of additional check bits to increase the number of minimum weighted codes in the Hamming Code H-Matrix. The circuit and technique of the present invention may be implemented while adding no additional correction/detection capability, in order to reduce the number of data bits that are used for each check bit/syndrome generation and to reduce the width of the parity generating circuitry.

Abstract: An error detection and correction system in accordance with an embodiment comprises: an encoding unit; a syndrome calculating unit; a syndrome element calculating unit; an error search unit; and an error correction unit, read and write of a memory cell array being assumed to be performed concurrently for m bits, and error detection and correction being assumed to be performed in data units of M bits (where M is an integer multiple of m), and an encoding unit and a syndrome calculating unit sharing a time-division decoder for performing data bit selection according to respective tables of check bit generation and syndrome generation, the time-division decoder being operative to repeat multiple cycles of m bit concurrent data input.

Abstract: A semiconductor memory device including an error detecting and correcting system, wherein the error detecting and correcting system includes a 3EC system configured to be able to detect and correct 3-bit errors, and wherein the 3EC system is configured to search errors in such a manner that 3-degree error searching equation is divided into a first part containing only unknown numbers and a second part calculative with syndromes via variable transformation by use of two or more parameters, and previously nominated solution indexes collected in a table and syndrome indexes are compared to each other.

Abstract: A decoding method is presented for error-correcting codes based on the syndrome decoding scheme, which means the set of all syndromes is one-to-one corresponding to the set of all correctable error patterns. The improvement in the high-speed error-correcting capability is achieved by searching a syndrome-error table, which is built upon the mathematical basis: there is a one-to-one correspondence between the set of all syndromes and the set of all correctable error patterns. Two embodiments of the present invention are described. The first embodiment uses a full syndrome-error table, whereas the second uses a partial syndrome-error table. The method includes the following steps: calculating a syndrome corresponding to the received bit string; determining whether the syndrome is a zero bit string; when the syndrome is not a zero bit string, determining an error pattern from the syndrome-error table; and correcting the corrupted codeword using the error pattern.

Abstract: The data memory cell array and parity memory cell array in the memory cell array has a constitution that is capable of corresponding with a plurality of ECC code lengths. An input-side parity generation circuit that generates parities from write data, an output-side parity generation circuit that generates parities from read data, and a syndrome generation circuit that generates a syndrome bit that indicates an error bit from the read parity bits and generated parity bits are constituted so as to be capable of switching, according to the plurality of ECC code lengths.

Abstract: The present invention discloses a method and apparatus for processing and error correction of a GFP-T superblock, where the 64 bytes of payload data of a first superblock are buffered in the first page of a two-page buffer. The flag byte is buffered in a separate buffer, and a CRC operation is performed in a separate logic element. The result of the CRC operation is checked against a single syndrome table which may indicate single- or multi-bit errors. As the payload data of the first superblock is processed and read out of the first page of the two-page buffer, the payload data of a second superblock is written into the second page of the two-page buffer to be processed and corrected.

Abstract: An error correction device is provided. Such error correction device may make use of an error-correction code defined by a parity matrix specialized for the application to multilevel memories. For example, the parity matrix is characterized by having a Maximum Row Weight equal to 22.

Abstract: A method for writing data to a multi-protocol encapsulation (MPE) buffer includes the steps of determining whether an error is generated in address information of an MPE section by comparing a location of an erasure table referring to the address of the MPE section, with address information of the MPE section, and when the error is generated in the address information of the MPE section, preventing writing data of the MPE section to a location of the MPE buffer referring to the address information of the MPE section, and when the error is not generated, writing the data of the MPE section to the location of the MPE buffer.

Abstract: The optical line terminal has a PON transceiver including an error correction code decoder. The error correction decoder includes: a shortening compensation parameter table; and a syndrome calculator for calculating a syndrome by referring to the shortening compensation parameter table, or an error search part for calculating an error position or an error value by referring to the shortening compensation parameter table. Also the optical network terminal has a PON transceiver including an error correction code decoder. The error code decoder includes: a shortening compensation parameter table; and a syndrome calculator for calculating a syndrome by referring to the shortening compensation parameter table, or an error search part for calculating an error position or an error value by referring to the shortening compensation parameter table.

Abstract: Embodiments of systems, apparatuses, and methods for correcting double bit burst errors using a low density parity check technique are disclosed. In one embodiment, an apparatus includes an encoder to generate a parity vector by multiplying a first version of a data vector by a matrix. The parity vector is to identify correctable double-bit burst errors in a second version of the data vector. The apparatus also includes logic to concatenate the parity vector and the first version of the data vector.

Abstract: Embodiments of the present invention provide multi-level signal memory with LDPC and interleaving. Thus, various embodiments of the present invention provide a memory apparatus that includes a memory block comprising a plurality of memory cells, each memory cell adapted to operate with multi-level signals. Such a memory apparatus also includes a low density parity check (LDPC) coder to LDPC code data values to be written into the memory cells and an interleaver adapted to apply bit interleaved code modulation (BICM) to the LDPC coded data values to generate BICM coded data values. Other embodiments may be described and claimed.

Abstract: In one embodiment, the present invention includes a method for generating a hybrid error correction code for a data block. The hybrid code, which may be a residual arithmetic-Hamming code, includes a first residue code based on the data block and a first parity code based on the data block and a Hamming matrix. Then the generated code along with the data block can be communicated through at least a portion of a datapath of a processor. Other embodiments are described and claimed.

Abstract: Identifying a burst error is disclosed. Identifying includes computing a syndrome check polynomial corresponding to a burst of length up to 2t?1 in received data and identifying a shortest burst based on the longest consecutive root sequence of the syndrome check polynomial. The received data is corrected based at least in part on the shortest burst.

Abstract: An apparatus comprising a first circuit, a second circuit and a disc. The first circuit may be configured to (i) extract video data as data blocks from an input signal and (ii) perform error correction on the data blocks with a delta syndrome based iterative Reed-Solomon decoding. The second circuit may be configured (i) to decode corrected video data into a video format in a first state, (ii) encode the corrected video data in a second state and (iii) share an external memory between the first circuit and the second circuit. The disc may be configured to store encoded video data in the second state.

Abstract: A memory device has an error detection and correction system constructed on a Galois finite field. The error detection and correction system includes calculation circuits for calculating the finite field elements based on syndromes obtained from read data and searching error locations, the calculation circuits having common circuits, which are used in a time-sharing mode under the control of internal clocks.

Abstract: A method for error detection in a memory system. The method includes calculating one or more signatures associated with data that contains an error. It is determined if the error is a potential correctable error. If the error is a potential correctable error, then the calculated signatures are compared to one or more signatures in a trapping set. The trapping set includes signatures associated with uncorrectable errors. An uncorrectable error flag is set in response to determining that at least one of the calculated signatures is equal to a signature in the trapping set.

Abstract: The present invention proposes a method and apparatus for decoding BCH codes and Reed-Solomon codes, in which a modified Berlekamp-Massey algorithm is used to perform the decoding process and the efficiency of the decoder can be improved by re-defining the error locating polynomial as a reverse error locating polynomial, while the operation of the decoding process can be further realized by a common re-configurable module. Furthermore, the architecture of the decoder is consisted of a plurality of sets of re-configurable modules in order to provide parallel operations with different degrees of parallel so that the decoding speed requirement of the decoder in different applications can be satisfied.

Abstract: A bit detection event within a read period is characterized by sub-dividing each read period into elementary time intervals. Certain ones of the elementary intervals are selected to for a window and a counting operation for a number of bits detected during the intervals within the window is performed. The elementary time intervals are defined by a difference between a frequency corresponding to the read period and a bit detection timing frequency. The counting result for the intervals in the window over several consecutive read periods is statistically processed. A reduction of an integrated electronic circuit test duration results from limiting the counting operations performed to the selected elementary time intervals.

Abstract: A memory device includes an error detection and correction system with an error correcting code over GF(2n) wherein the system has an operation circuit configured to execute addition/subtraction with modulo 2n?1, and wherein the operation circuit has a first operation part for performing addition/subtraction with modulo M and a second operation part for performing addition/subtraction with modulo N (where, M and N are integers which are prime with each other as being obtained by factorizing 2n?1), and wherein the first and second operation parts perform addition/subtraction in parallel to output an operation result of the addition/subtraction with modulo 2n?1.

Abstract: The present invention discloses a method and apparatus for performing forward error correction with a multi-dimensional Bose Ray-Chaudhuri Hocquenghem (BCH) product code, and a method for detecting false decoding errors in frame-based data transmission systems.

Abstract: A RAID 6 system, which has two strips to hold redundant data, employs a memory array controller that at each “read” operation considers not just the data but also the redundant information, even in the absence of any indication from the collection of memory controllers associated with the hard drives that any error condition exists. Thus, with each “read” operation the array controller checks the data for an unreported error, and takes corrective action when an error condition is discovered.

Abstract: This disclosure relates generally to low power data decoding, and more particularly to low power iterative decoders for data encoded with a low-density parity check (LDPC) encoder. Systems and methods are disclosed in which a low-power syndrome check may be performed in the first iteration or part of the first iteration during the process of decoding a LDPC code in an LDPC decoder. Systems and methods are also disclosed in which a control over the precision of messages sent or received and/or a change in the scaling of these messages may be implemented in the LDPC decoder. The low-power techniques described herein may reduce power consumption without a substantial decrease in performance of the applications that make use of LDPC codes or the devices that make use of low-power LDPC decoders.

Abstract: A method to reduce memory requirements for a packet loss concealment algorithm in the event of packet loss in a receiver of pulse code modulated voice signals. A voice playout unit in the receiver shares its nominal delay buffer with a history buffer of a packet loss concealment algorithm up to a maximum limit described in a standard. This reduces or eliminates need to allocate memory for the history buffer. A history buffer can also be extended to retain an original portion of voice signal packets received prior to a packet loss as well as generated voice signals as they are generated. A scratch buffer is used as a working buffer and replaces the function of a pitch buffer.

Abstract: A Digitally Video Broadcasting—Handheld (DVB-H) system for performing forward error correction includes: a tuner for receiving a data stream; a base-band receiver, coupled to the tuner, for extracting data bytes of a multi-protocol-encapsulation forward-error-correction (MPE-FEC) frame, and performing syndrome calculation on each extracted data byte to determine a corresponding partial syndrome; and an embedded memory, coupled to the base-band receiver, for accumulating each partial syndrome to determine a complete syndrome; wherein once all syndromes of the MPE-FEC frame are received, the base-band receiver determines corresponding error values and utilizes the error values to forward error correct the MPE-FEC frame.

Abstract: An efuse device for recording input data according to address data comprises a first check-bit generator, a programming unit, and an efuse array. The first check-bit generator receives the input data and generates first check-bit data according to the input data by a predetermined error correction code. The programming unit generates blowing signals according to the input data and the first check-bit data. The efuse array receives the blowing signals and the address data. The input data and the first check-bit data are recorded in the efuse array according to the blowing signals and the address data.

Abstract: The present invention discloses a frame boundary detection system and a synchronization system for a data stream received by an Ethernet Forward Error Correction layer. The frame boundary detection system includes a shifter, two descramblers, a syndrome generator and trapper. The error trapper includes a big-little endian mode controller for controlling the big-little endian conversion of the error trapper. If the error trapper operates in the big endian mode, the error trapper implements the function of the syndrome generator, operates at the same time with the syndrome generator, and performs a second FEC check, wherein when the shifter performs the FEC check by intercepting data with a length of one frame plus A bits, two start positions of the frame can be verified, where A is a positive integer less than a length of one frame. The invention can improve the frame boundary detection speed and the frame synchronization speed, and increase only a few hardware overheads.

Abstract: A memory system includes a memory array. The memory array includes a plurality of storage locations arranged in rows and columns. The memory system includes error correction circuitry that generates correct data bits from data bits of the memory array and error correction bits. The data bits received by the error correction circuitry are divided in subgroups where each subgroup of data bits is used to generate a subgroup of the correct data bits. The subgroups of data bits are stored in a row of the memory array at locations that are interleaved with each other.

Abstract: A flash memory includes a memory sector, a command interface, a first signal buffer, a control signal generation circuit, a data input buffer, an error correction circuit, an address buffer, an address signal generation circuit, a plurality of data memory circuits, and write circuit. The command interface receives a write data input instruction from an external device to generate a write data input instruction signal, and receives a write instruction from the external device to generate a write instruction signal. The error correction circuit is activated by the write data input instruction signal to receive the write data in synchronization with the write enable signal, and is activated by the write instruction signal to generate a check data for an error correction in synchronization with the control signal.

Abstract: A data modulation method and a data error correction method are provided. The data modulation method includes generating a channel sequence for an input sequence, determining whether or not the channel sequence violates a Run Length Limit (RLL) constraint, and performing, when the channel sequence violates the RLL constraint, bit flip at a position prior to a position at which the RLL constraint is violated among positions of bits included in the channel sequence. The data error correction method includes detecting an error bit of received data using a parity check matrix, determining whether or not the error bit is an error caused by bit flip, and correcting the error bit when the error bit is an error caused by bit flip for applying an RLL constraint.

Abstract: A system, method and program product for utilizing error correction code (ECC) logic to detect multi-bit errors. In one embodiment, a first test pattern and a second test pattern are applied to a set of hardware bit positions. The first and second patterns are multiple logic level patterns and the second test pattern is the logical complement of the first test pattern. The first and second test patterns are utilized by the ECC logic to detect correctable errors having n or fewer bits. One or more bit positions of a first correctable error occurring responsive to applying the first test pattern are determined and one or more bit positions of a second correctable error occurring responsive to applying the second test pattern are determined. The determined bit positions of the first and second correctable errors are processed to identify a multiple-bit error within the set of hardware bit positions.

Abstract: Method and apparatus for error checking information is described. Configuration data includes data bits and parity bits. Notably, parity bits may be relocated for determining a syndrome value. Syndrome bits are determined by computing a partial syndrome value for each word serially transmitted of the configuration data, where the configuration data includes one or more data vectors. Location of each word of the configuration data is identified. It is determined whether a partial syndrome value is an initial partial syndrome value or other partial syndrome value responsive to word location. An initial partial syndrome value is stored, and subsequent partial syndrome values are cumulatively added for each word of a data vector to arrive at a syndrome value for the data vector.

Abstract: An apparatus is capable of executing a facsimile communication using an Error Correction Mode (ECM) function based on a facsimile procedure with a communication partner connected via an Internet Protocol (IP) network. In response to receiving, from the communication partner via the network, a communication start request including information indicating a transport protocol for use in the communication, if the apparatus determines that the transport protocol for use in the communication does not have the error correction function, the apparatus sends to the communication partner a notification indicating that the apparatus is capable of executing the communication using the ECM function. Otherwise, if the apparatus determines that the transport protocol for use in the communication has the error correction function, the apparatus sends to the communication partner a notification indicating that the apparatus is incapable of executing the communication using the ECM function.

Abstract: In an error correction method, a codeword is transmitted through a noisy communication channel and detected by a receiving device. An error detection code is then applied to the detected codeword to generate a syndrome. Where the syndrome is not all zero, the codeword is determined to contain some error. Accordingly, the method computes a set of potential error start positions for a plurality of error events based on a syndrome value corresponding to the syndrome. Next, a confidence value is computed for each of the plurality of error events at each of the potential error start positions in the refined set, and finally, a most likely error event in the detected codeword is corrected based on an error event and corresponding potential error start position having the highest confidence value.

Abstract: Various read level control apparatuses and methods are provided. In various embodiments, the read level control apparatuses may include an error control code (ECC) decoding unit for ECC decoding data read from a storage unit, and a monitoring unit for monitoring a bit error rate (BER) based on the ECC decoded data and the read data. The apparatus may additionally include an error determination unit for determining an error rate of the read data based on the monitored BER, and a level control unit for controlling a read level of the storage unit based on the error rate.

Abstract: A semiconductor memory system includes a memory area and an error-correcting (ECC) circuit. The memory area includes a plurality of cells, and the ECC circuit is configured to determine whether uncorrectable error data exists or not by using a parity according to cell data of the memory area in a read mode and a parity according to an encoding result of corrected data of the cell data.

Abstract: System and method for designing Slepian-Wolf codes by channel code partitioning. A generator matrix is partitioned to generate a plurality of sub-matrices corresponding respectively to a plurality of correlated data sources. The partitioning is performed in accordance with a rate allocation among the plurality of correlated data sources. A corresponding plurality of parity matrices are generated based respectively on the sub-matrices, where each parity matrix is useable to encode data from a respective one of the correlated data sources.

Abstract: The invention provides a method for encoding and decoding an error correction code. First, raw data is received and then divided into a plurality of data segments. A plurality of short parities corresponding to the data segments is then generated according to a first generator polynomial. The short parities are then appended to the data segments to obtain a plurality of short codewords. The short codewords are then concatenated to obtain a code data. A long parity corresponding to the code data is then generated according to a second generator polynomial, wherein the first generator polynomial is a function of at least one minimum polynomial of the second generator polynomial. Finally, the long parity is then appended to the code data to obtain a long codeword as an error correction code corresponding to the raw data.

Abstract: Some embodiments of the present invention provide a system that provides error detection and correction after a failure of a memory component in a memory system. During operation, the system accesses a block of data from the memory system, wherein the memory system is previously determined to have a specific failed memory component. Each block of data in the memory system includes an array of bits logically organized into R rows and C columns, including a row checkbit column including row-checkbits for each of the R rows, an inner checkbit column including X<R inner checkbits and R?X data bits, and C?2 data-bit columns containing data bits. Note that each column is stored in a different memory component, and the checkbits are generated from the data bits to provide block-level detection and correction for a failed memory component. Next, the system attempts to correct a column of the block from the failed memory component by using the checkbits and the data bits to produce a corrected column.

Abstract: Segregation of redundant control bits in an ECC permuted, systematic modulation code. Appropriately encoding of user information via combined modulation and RS (Reed-Solomon) encoding ensures segregation of scrambled user information, modulation redundancy bits, and RS redundancy bits in such a way that each of the components thereof are segregated and stored within any desirable digital information memory storage device. By providing this segregated capability, when accessing a portion of a RS codeword from the memory, an entire RS codeword need not be read from the memory. In fact, only the particular field (or bits) needs to be accessed to perform correction thereon. This segregation provides for a reduction in the hardware complexity of translation between user information and a modulation codeword. Also, this segregation provides for the ability to perform correction of only one of the scrambled user information, the modulation redundancy bits, or the RS redundancy bits.

Abstract: A method for synchronizing receivers that receive turbo encoded signals to a received signal. Turbo encoding may enable signals to be decoded at a much lower signal to noise ratio than previously practical. A traditional method of synchronizing a receiver to an incoming signal is to use a slicer to determine a received symbol and then to compare the determined symbol to the incoming waveform, in order to adjust the phase of the slicer with respect to the incoming signal. At signal low levels, at which turbo encoded signals may be decoded, this slicing method may be prone to errors that may disrupt the synchronization of the receiver to the incoming signal. By replacing the slicer by a Viterbi decoder with zero traceback (i.e., one which does not consider future values of the signal only past values) a prediction as to what the incoming signal is can be made.

Abstract: Data bits to be encoded are split into a plurality of subgroups. Each subgroup is encoded separately to generate a corresponding codeword. Selected subsets are removed from the corresponding codewords, leaving behind shortened codewords, and are many-to-one transformed to condensed bits. The final codeword is a combination of the shortened codewords and the condensed bits. A representation of the final codeword is decoded by being partitioned to a selected subset and a plurality of remaining subsets. Each remaining subset is decoded separately. If one of the decodings fails, the remaining subset whose decoding failed is decoded at least in part according to the selected subset. If the encoding and decoding are systematic then the selected subsets are of parity bits.