Abstract: A disk drive is disclosed comprising a head actuated over a disk comprising a plurality of data sectors. A redundancy generator is loaded with a first seed value corresponding to system data generated internal to the disk drive. First data path redundancy symbols are generated in response to the first seed value, and the system data and the first data path redundancy symbols are written to a first data sector. A syndrome generator is loaded with the first seed value to generate first syndromes when reading the system data and first data path redundancy symbols from the first data sector. The validity of the system data is verified in response to the first syndromes.

Abstract: A system to improve error control coding. An example system includes memory chips of at least two different kinds. The system also includes error control encoder circuitry to substantially encode data for storage in any memory rank. The system further includes error control decoder circuitry to substantially decode encoded data received from any memory rank. The error decoder circuitry is comprised of a slow decoder and a fast decoder.

Abstract: A method and apparatus for providing error correction capability to longitudinal position data are disclosed. Initially, data are encoded via a set of even LPOS words and a set of odd LPOS words. The encoded data are then decoded by generating a set of syndrome bits for each of the LPOS words. A determination is then made as to whether or not there is an error within one of the LPOS words based on its corresponding syndrome bits.

Abstract: A system to improve error code decoding using historical information. An example system includes storage partitioned into memory ranks, and a table to record symbols having failures for each memory rank. The system generates a memory rank score for each memory rank. The system also includes an error control decoder that uses the memory rank score when each memory rank is accessed in order to determine whether an error should be corrected or not.

Abstract: A system to improve error correction includes a fast decoder to process data packets until the fast decoder finds an uncorrectable error in a data packet at which point a request for at least two data packets is generated. The system also includes a slow decoder to correct the uncorrectable error in a data packet based upon the at least two data packets.

Abstract: An apparatus for correcting at least one bit error within a coded bit sequence includes an error syndrome generator and a bit error corrector. The error syndrome generator determines the error syndrome of a coded bit sequence derived by a multiplication of a check matrix with a coded bit sequence.

Abstract: A fixed length Reed-Solomon encoder is configured to produce a first fixed number of redundant symbols. The fixed length Reed-Solomon encoder is configured with an encoding polynomial that is fixed. A symbol preprocessor maps each input data symbol to a transformed input data symbol. A symbol postprocessor maps a second fixed number of redundant symbols output from the fixed length Reed-Solomon encoder to a set of redundant symbols. The second fixed number of redundant symbols is less than the first fixed number of redundant symbols.

Abstract: A system to improve miscorrection rates in error control code may include an error control decoder with a safe decoding mode that processes at least two data packets. The system may also include a buffer to receive the processed at least two data packets from the error control decoder. The error control decoder may apply a logic OR operation to the uncorrectable error signal related to the processing of the at least two data packets to produce a global uncorrectable error signal. The system may further include a recipient to receive the at least two data packets and the global uncorrectable error signal.

Abstract: A system to improve memory reliability in computer systems that may include memory chips, and may rely on a error control encoder to send codeword symbols for storage in each of the memory chips. At least two symbols from a codeword are assigned to each memory chip and therefore failure of any of the memory chips could affect two symbols or more. The system may also include a table to record failures and partial failures of the codeword symbols for each of the memory chips so the error control encoder can correct subsequent partial failures based upon the previous partial failures. The error control coder is capable of correcting and/or detecting more errors if only a fraction of a chip is noted in the table as having a failure as opposed to a full chip noted as having a failure.

Abstract: An encoded message is stored in a first memory. The encoded message is retrieved from the first memory as a retrieved encoded message that may contain an error. Syndromes are generated from the retrieved encoded message. The syndromes are used to determine if the retrieved encoded message has an error. Polynomial coefficients are generated for establishing a polynomial equation having a first number of solutions. The polynomial equation is solved only for a second number of solutions. The first number is greater than the second number. The second number of solutions comprises solutions corresponding to locations in the retrieved encoded message. Each location is corrected in the retrieved encoded message that corresponds to a solution of zero of the polynomial equation. The result is efficient error correction.

Abstract: Data latches, multiplexers, an ECC circuit section, and an input/output circuit section are arranged in columns and adjacent to each other, in an extending direction of data lines that are formed in a direction orthogonal to word lines. A layout of a data path system is formed in bit slices. Further, parity bits are equally distributed so as to cause delay times of bits to be uniform.

Abstract: An error correction circuit, an error correction method, and a semiconductor memory device including the error correction circuit are provided. The error correction circuit includes a partial syndrome generator, first and second error position detectors, a coefficient calculator, and a determiner. The partial syndrome generator calculates at least two partial syndromes using coded data. The first error position detector calculates a first error position using a part of the partial syndromes. The coefficient calculator calculates coefficients of an error position equation using the at least two partial syndromes. The determiner determines an error type based on the coefficients. The second error position detector optionally calculates a second error position based on the error type.

Abstract: A decoder, a method of decoding and systems implementing the same are disclosed. In one example, the method includes calculating syndrome values from input codewords, generating an error location polynomial about the codewords using the syndrome values, determining an error count in the codewords using the error location polynomial, and adjusting power consumption of a circuit in response to the determined error count in the codewords. In one example, a frequency of a clock signal to be provided to a search circuit may be determined based on the error count, and the clock signal may be provided having the determined frequency to a search circuit, such as a Chien search circuit.

Abstract: An approach is provided for encoding information bits to output a coded signal using turbo code encoding with a low code rate.

Abstract: In one embodiment, a memory controller comprises a check bit encoder circuit coupled to receive a data block to be written to memory, a check/correct circuit coupled to receive an encoded data block read from the memory, and a hard failure detection circuit coupled to the check/correct circuit. The check bit encoder circuit is configured to generate a corresponding encoded data block comprising the data block, a first plurality of check bits, and a second plurality of check bits. The check/correct circuit is configured to detect an error in the encoded data block responsive to the first check bits, the second check bits, and the data block within the encoded data block, which is logically arranged as an array of R rows and N columns, wherein R and N are positive integers. Each of the first check bits covers a respective row of the array, and the check/correct circuit is configured to generate a first syndrome corresponding to the first plurality of check bits.

Abstract: According to an example embodiment, an apparatus may include logic. The apparatus may be configured to: determine, based on an error location polynomial, an error location syndrome corresponding to an actual location of a burst error in a data block; select a burst error pattern that is less than or equal to M bits, and having no more than Y consecutive zeros within the burst error, where M is greater than the order of the error location polynomial; determine an error pattern syndrome based on the selected burst error pattern and the error location polynomial; and determine an actual location of the burst error in the data block based on the error location syndrome and the error pattern syndrome.

Abstract: Systems and methods are provided for implementing list decoding in a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. The soft-information can be organized into an order of combinations of error events for list decoding. An RS decoder can employ a list decoder that uses a pipelined list decoder architecture. The list decoder can include one or more syndrome modification circuits that can compute syndromes in parallel. A long division circuit can include multiple units that operate to compute multiple quotient polynomial coefficients in parallel. The list decoder can employ iterative decoding and a validity test to generate error indicators. The iterative decoding and validity test can use the lower syndromes.

Abstract: Systems and methods are provided for implementing various aspects of a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. If the decision-codeword corresponds to an inner code and an RS code is the outer code, a soft-information map can process the soft-information for the decision-codeword to produce soft-information for a RS decision-codeword. A RS decoder can employ the Berlekamp-Massey algorithm (BMA), list decoding, and a Chien search, and can include a pipelined architecture. A threshold-based control circuit can be used to predict whether list decoding will be needed and can suspend the list decoding operation if it predicts that list decoding is not needed.

Abstract: A method of decoding a one-point algebraic geometric code defined on an algebraic curve of type C(a,b) represented by an equation F(X,Y) =0 of degree b in X and of degree a in Y over Fq, includes calculating extended error syndromes (?j(i)) associated with a received word (r) and determining the values of errors in each component r(x,yp,(x)) of the received word r, on the basis of the extended error syndromes calculated.

Abstract: An apparatus generally having a port, a first circuit and a second circuit is disclosed. The port may be configured to receive a current length of a codeword. The current length may be less than a maximum length of the codeword that the apparatus is designed to decode. The first circuit may be configured to calculate in parallel (i) a sequence of intermediate syndromes from the codeword and (ii) a sequence of correction values based on the current length. The second circuit may be configured to generate a particular number of updated syndromes by modifying the intermediate syndromes with the correction values. The particular number is generally twice a maximum error limit of the codeword.

Abstract: A method for determining a fault tolerance of an erasure code includes deriving base erasure patterns from a generator matrix of an erasure code, determining which of the base erasure patterns are adjacent to one another and XORing the adjacent base erasure patterns with one another to produce child erasure patterns of the erasure code. The method further includes combining the base erasure patterns and the child erasure patterns to form a minimal erasures list (MEL) for the erasure code, whereby the MEL corresponds to the fault tolerance of the erasure code. Also provided are methods for communicating and storing data by using the fault tolerance of erasure codes.

Abstract: A QC-LDPC decoding system employing a trapping set look-up table is provided. The QC-LDPC decoding system includes an iterative decoder that utilizes a message-passing algorithm to decode a received codeword. If the iterative decoder fails to produce a valid codeword, additional processing is performed to decode the received codeword. The additional processing includes the steps of computing the syndrome pattern of the received codeword, searching the look-up table for a trapping set class that is responsible for the iterative decoder's failure, retrieving from the look-up table a syndrome pattern and an error pattern of a member of the responsible trapping set class, and calculating the error pattern of the received codeword based on its syndrome pattern and the information retrieved from the look-up table. The received codeword is then corrected based on its error pattern.

Abstract: Cyclic redundancy check processing is applied advantageously to a set of input data that includes an unknown data portion and a data portion that is already known before the unknown data portion becomes available. A syndrome contribution that the already-known data portion contributes to a syndrome for the set of input data is determined before the unknown data portion becomes available. When the unknown data portion becomes available, the syndrome for the set of input data is determined based on the unknown data portion and the syndrome contribution.

Abstract: A circuit and method for generating an Error Correcting Code (ECC) based on an adjacent symbol codeword that is formed in two clock phases. In an embodiment, a set of m bits of a first symbol and a set of m bits of a second symbol from a first set of data for transmission over a channel during a first clock phase are generated. A set of n bits of the first symbol and a set of n bits of the second symbol from a second set of data over a channel are also generated during a second clock phase. Other embodiments are also claimed and/or disclosed.

Abstract: Various read level control apparatuses and methods are provided. In various embodiments, the read level control apparatuses may include an error control code (ECC) decoding unit for ECC decoding data read from a storage unit, and a monitoring unit for monitoring a bit error rate (BER) based on the ECC decoded data and the read data. The apparatus may additionally include an error determination unit for determining an error rate of the read data based on the monitored BER, and a level control unit for controlling a read level of the storage unit based on the error rate.

Abstract: Methods for recycling unused error correction code (ECC) during flash memory programming, comprise generating ECC from user data to form a syndrome and storing the syndrome into volatile memory. ECC is re-encoded corresponding to the syndrome read from the memory with new user data. Re-encoding ECC comprises comparing new ECC with the most recent ECC of the previous syndrome, correcting a bit error in the new ECC, and indicating if the new ECC has failed.

Abstract: An embodiment of a data write path includes encoder and write circuits. The encoder circuit is operable to code data so as to render detectable a write error that occurs during a writing of the coded data to a storage medium, and the write circuit is operable to write the coded data to the storage medium. For example, such an embodiment may allow rendering detectable a write error that occurs while writing data to a bit-patterned storage medium.

Abstract: In accordance with the teachings described herein, systems and methods are provided for performing forward error correction. A decoder for performing forward error correction for a frame in a data stream includes a state machine configured to determine if a code block within the frame received by the decoder is a complete code block or a partial code block, the frame including a plurality of code blocks. A decoding unit is configured to receive the code block, and, when the code block is a partial code block, to generate an output based on decoding the partial code block and an additional partial decoding result that is input to the decoding unit.

Abstract: A method and apparatus for providing error correction capability to longitudinal position data are disclosed. Initially, data are encoded via a set of even LPOS words and a set of odd LPOS words. The encoded data are then decoded by generating a set of syndrome bits for each of the LPOS words. A determination is then made as to whether or not there is an error within one of the LPOS words based on its corresponding syndrome bits.

Abstract: Methods and systems are disclosed for the detection and correction of memory errors using code words with a quantity, divisible by 4, of data bits, with an equal quantity of check bits, and having the check bits and data bits interleaved. Upon execution of a memory write instruction, a processor may send a memory word to a check bit generator that generates the check bits before the code word is written to a memory unit. Upon a signal from the processor that a memory read is requested, the memory unit may send a stored code word to a syndrome bit generator to generate a syndrome vector. The syndrome vector may then be sent to a correction bit generator and an uncorrectable error detector. These units may send corrected bits and an uncorrectable error signal, respectively, to the processor.

Abstract: A data processing method includes the steps of: initializing a syndrome vector to be an (n?1)th symbol; finding a corresponding mask based on the syndrome vector, wherein the mask is zero when the (n?1)th symbol is zero; correcting a known constant, which is zero when the syndrome vector is zero, based on the mask; inputting the syndrome vector to a log look-up table to correspondingly find log data; performing a modulo addition operation corresponding to log maximum data to find a log sum based on the log data and a log known constant; and inputting the log sum to an anti-log look-up table to correspondingly find operational data.

Abstract: Techniques, systems and computer program products are described for providing a Reed Solomon decoder. The Reed Solomon decoder includes a syndrome polynomial generator to generate syndrome polynomials for subchannel data received from subchannels. In addition, a syndrome polynomial selector selects one of the generated syndrome polynomials according to a preset priority. An error location/error value polynomial generator generates an error location polynomial and an error value polynomial by applying a first algorithm to the selected syndrome polynomial. Also an error location/error value calculator calculates an error location by applying a second algorithm to the error location polynomial and calculates an error value by applying a third algorithm to the error value polynomial. Further, an error corrector corrects an error included in the received subchannel data by applying the calculated error location and the calculated error value to the received subchannel data.

Abstract: A system and method corrects erroneous sections received in a memory by pre-filling at least a portion of memory with a pre-defined value. If a received data packet is valid, the valid received data packet is stored over the pre-defined values in the memory location associated with the valid data packet. Values associated with a data segment and an adjacent data segment in the memory are compared to the pre-defined value. When the values of each data segment match the pre-defined values, then each data segment is an erroneous data segment.

Abstract: An error correction method and system includes an Encoder and Syndrome-generator that operate in parallel to reduce the amount of circuitry used to compute check symbols and syndromes for error correcting codes. The system and method computes the contributions to the syndromes and check symbols 1 bit at a time instead of 1 symbol at a time. As a result, the even syndromes can be computed as powers of the odd syndromes. Further, the system assigns symbol addresses so that there are, for an example GF(28) which has 72 symbols, three (3) blocks of addresses which differ by a cube root of unity to allow the data symbols to be combined for reducing size and complexity of odd syndrome circuits. Further, the implementation circuit for generating check symbols is derived from syndrome circuit using the inverse of the part of the syndrome matrix for check locations.

Abstract: Defining a set of correctable error and uncorrectable error syndrome code points, generating an error correction code (ECC) syndrome decode, regarding the uncorrectable error syndrome code points as “don't cares” and logically minimizing the ECC syndrome decode for the determination of the correctable error syndrome code points based on the regarding of the uncorrectable error syndrome code points as the “don't cares” whereby output data can be ignored for the uncorrectable error syndrome code points.

Abstract: Error correction and detection in a redundant memory system including a a computer implemented method that includes receiving data including error correction code (ECC) bits, the receiving from a plurality of channels, each channel comprising a plurality of memory devices at memory device locations. The method also includes computing syndromes of the data; receiving a channel identifier of one of the channels; and removing a contribution of data received on the channel from the computed syndromes, the removing resulting in channel adjusted syndromes. The channel adjusted syndromes are decoded resulting in channel adjusted memory device locations of failing memory devices, the channel adjusted memory device locations corresponding to memory device locations.

Abstract: The present invention is all error detection and correction scheme that enables the use of Horner's algorithm for the computation of EDC syndromes from the computed error pattern. Specifically, “transformed” EDC syndromes are computed during the read back of data and parity from the medium. The transformed syndromes are values of the polynomial whose coefficients occur in reverse order from that of the EDC codeword polynomial. In essence, by reversing the order of the coefficients, the Chien search processes the terms in descending order which is the right direction for Horner evaluation.

Abstract: A data processing method is provided. Target page data are read from a memory cell array and addresses of multiple programmed-error bits are stored. A first syndrome polynomial and a second syndrome polynomial are obtained according to the target page data, and the target page data are saved as a first codeword and a second codeword. An errata locator polynomial is obtained according to the syndrome polynomials, and a first error count and a second error count are obtained according to the errata locator polynomial, the first codeword and the second codeword. A set of reference codes is obtained according to the errata locator polynomial. Read page data are outputted according to the addresses of the programmed-error bits, the first error count and the second error count. The read page data are corrected according to the set of reference codes to obtain corrected read page data.

Abstract: Provided are an encoder and a syndrome computer for cyclic codes which process M codeword symbols per cycle where M is greater than or equal to one, whereby the encoder and syndrome computer optionally further provide the configurability of a different M value for each cycle and/or the configurability of a different cyclic code for each codeword. Further provided is a hybrid device which provides the configurability of two modes of operation, whereby in one mode, the hybrid device functions as the encoder as provided above and, in the other mode, the hybrid device functions as the syndrome computer as provided above, with the majority of the components of the hybrid device being shared between the encoding function and the syndrome computing function.

Abstract: An apparatus and a method of processing cyclic codes are disclosed herein, where the apparatus includes at least one reconfigurable module and an encoder controller. The reconfigurable module includes a plurality of linear feedback shift registers. The encoder controller can control the reconfigurable module to factor a generator polynomial into a factorial polynomial. In the reconfigurable module, the linear feedback shift registers can register a plurality of factors of the factorial polynomial respectively.

Abstract: Disclosed are a method and apparatus for detecting frame boundary for a data stream received at an Ethernet FEC layer, as well as a decoding method and system for the same. The apparatus for detecting frame boundary may comprise: a buffer for buffering data in a data stream, a length of the data in the buffer being greater than one frame; a syndrome generator for calculating a current syndrome based on a first data item, a second data item, and an intermediate calculation result of a previous syndrome, wherein the first data item is the last bit in a current candidate frame, and the second data item is a bit preceding the current candidate frame; and a comparator for using the current syndrome to check whether the bit preceding the current candidate frame is a frame boundary of an Ethernet FEC layer. The apparatus for detecting frame boundary can improve the speed of frame boundary detection.

Abstract: The disclosed embodiments relate to a memory system that facilitates probabilistic error correction for a failed memory component with partial-component sparing. During operation, the memory system accesses blocks of data, wherein each block of data includes an array of bits logically organized into R rows and C columns. The C columns include (1) a row-checkbit column containing row-parity bits for each of the R rows, (2) an inner-checkbit column containing X=R?S inner checkbits and S spare bits, and (3) C-2 data-bit columns containing data bits. Moreover, each column is stored in a different memory component, and the checkbits are generated from the data bits to provide guaranteed detection and probabilistic correction for a failed memory component.

Abstract: The disclosed embodiments relate to a memory system that provides guaranteed component-failure correction and double-error correction. During operation, the memory system accesses a block of data, wherein each block of data in the memory system includes an array of bits logically organized into R rows and C columns. The C columns include (1) a row-checkbit column containing row checkbits for each of the R rows, (2) an inner-checkbit column containing R inner checkbits, and (3) C-2 data-bit columns containing databits. In addition, each column is stored in a different memory component, and the checkbits are generated from the databits to provide block-level correction for a failed memory component, and double-error correction for errors in different memory components. Next, the system calculates a row syndrome and an inner syndrome for the block of data, wherein the inner syndrome that results from any two-bit error in the same row is unique.

Abstract: A cache memory system is provided that uses multi-bit Error Correcting Code (ECC) with a low storage and complexity overhead. The cache memory system can be operated at very low idle power, without dramatically increasing transition latency to and from an idle power state due to loss of state.

Abstract: An erasures assisted block code decoder and related method are provided. The erasures assisted block code decoder includes a first block decoder, an erasures processor, and a second block code decoder. The first block decoder, for example, a Reed-Solomon decoder, is configured to decode blocks of data elements, e.g., bytes, that were previously affected by bursty errors. The first block decoder is also configured to identify those of such blocks it is unable to decode. The erasures processor is configured to identify, as erasures, data elements in the un-decodable blocks by utilizing, in the erasures identification process, data elements in the decoded blocks that were corrected by the first block decoder. The second block decoder, e.g., the same or different Reed-Solomon decoder, is configured to decode one or more of the un-decodable blocks by utilizing, in the decoding, the erasures identified by the erasures processor.

Abstract: An error detection module includes a known-syndrome computing unit, an unknown-syndrome computing unit, and an error detection unit. The known-syndrome computing unit is operable to convert a received signal into a target signal, to obtain known syndromes based upon the target signal, and to generate an errata-locator polynomial based upon an erasure-locator polynomial and the known syndromes. The unknown-syndrome computing unit is operable to compute unknown syndromes based upon the errata-locator polynomial and the known syndromes. The error detection unit is operable to obtain a syndrome set that includes the known syndromes and the unknown syndromes, to obtain an error detection signal according to the syndrome set, and to provide an error correction module coupled thereto with the syndrome set and the error detection signal for enabling the error correction module to correct an error of the received signal.

Abstract: A method for combining a simple forward error correction code i.e., a Hamming-like code with scrambling and descrambling functions is disclosed. Therefore, irrespective of the information to be transported, received data may be corrected, bit error spreading effects being handled, while providing desirable signal characteristics such as signal DC balance and enough signal transitions. The overhead introduced by the method is a modest increase over the original overhead of the 10 Gb Ethernet 64B/66B code.

Abstract: An approach to dividing syndrome calculations into two steps and serially processing them requires a long time for the syndrome calculations with respect to an entire decoding process. Therefore, there is disclosed an error correction decoding circuit for a playing signal having a code sequence having a decoding unit generating first decoded signal and second decoded signal based on the code sequence and an error correction unit performing error correction for the second signal in response to the first signal.

Abstract: In one embodiment, an apparatus includes a check/correct circuit coupled to a control circuit. The check/correct circuit is coupled to receive a block of data and corresponding check bits. The block of data is received as N transmissions, each transmission including M data bits and L check bits. The check/correct circuit is configured to detect one or more errors in each of a plurality of non-overlapping windows of K bits in the M data bits, responsive to the M data bits and the L check bits. The control circuit is configured to record which of the plurality of windows have had errors detected and, if a given window of the plurality of windows has had errors detected in each of the N transmissions of the block, the control circuit is configured to signal a device failure. Each of K, L, M, and N are integers greater than one.

Abstract: A parallel-to-serial conversion method for IBMA in a Reed Solomon decoder is used for obtaining discrepancies in IBMA iterations, thereby acquiring an error location polynomial and an error value polynomial. Syndrome sequences for the calculation of discrepancies in IBMA iterations have a fixed length. The number of syndromes is t+1, where t is the largest number of symbols that can be corrected of the error location polynomial. The feature that syndrome sequences have the same length is based on the fact that the discrepancies are not affected if the coefficients of polynomial orders of the error location polynomial are zero.