Abstract: In one embodiment, the present patent application comprises a method and apparatus to generate low rate protographs from high rate protographs, comprising copying a base graph; permuting end points of edges of a same type in copies of the base graph to produce a permuted graph; and pruning systematic input nodes in the permuted graph and the edges connected to them. In another embodiment, the present patent application comprises a method and apparatus to generate high-rate codes from low-rate codes, comprising puncturing a subset of codeword bits, wherein the step of puncturing a subset of codeword bits comprises regular-irregular puncturing the subset of codeword bits, random puncturing variable nodes, or progressive node puncturing variable nodes to obtain a desired code from a preceding code.

Abstract: Circuit, method, and computer program for reordering data units of a data block in accordance with a first pre-determined function. The method includes, for each data unit of the data block—(i) generating an address corresponding to a memory location of a single-port memory module into which the data unit is to be stored, and (ii) storing the data unit in the memory location based on the address generated for the data unit. Each address is generated in accordance with the first pre-determined function, and each memory location of the single-port memory has a different delay associated with the memory location. The method further includes reading each data unit out of the single-port memory in accordance with the first pre-determined function, wherein data units of the data block are reordered based on each different delay associated with each memory location.

Abstract: A method for reducing fading channel signal data loss for serial data rates up to approximately 10 gigabits per second includes sequentially distributing serial data to multiple encoders. Individual data bytes are sent from the encoders to a convolutional interleaver. Each byte is distributed to an individual memory element of the interleaver in a received byte sequence. An address generator generates write and read addresses assignable to each memory element. Multiple shift registers have variably graduated lengths. The serial data is distributed between channels each having a different delay element created by shift register length differences. The delay elements are adjustable to correct data dropout due to daily atmospheric/channel changes. Fade detection signals are inserted before transmission and measured at a receiver. The fade signals help create erasure bits to improve decoding accuracy and adjust interleaver delay parameters.

Abstract: An SDRAM convolutional interleaver with two paths. Symbols are assigned to a given one of the two paths, then are sorted to minimize (to one) a number of breaks in a sequential Interleaver write address. After sorting, the symbols are stored staggered in SRAM and burst written to SDRAM. Before writing to SDRAM, data is accumulated for four symbols at a time, and the data is written four symbols wide to optimize SDRAM access time. 8 bit symbols are written 32 bits at a time to SDRAM.

Abstract: An optical transport system (OTS) having a plurality of optical transponders (OTs) connected via one or more optical links and adapted to communicate with one another using respective rate-adaptive forward-error-correction (FEC) codes. In one embodiment, the OTS has a rate control unit (RCU) adapted to configure the OTs to dynamically adjust the rates of the FEC codes based on an estimated performance margin for each link between two respective communicating OTs to optimize the overall capacity of the OTS while maintaining an adequate, but not excessive, overall system margin.

Abstract: A system comprising a plurality of channel detectors (CDs) receiving quantized and equalized ISI channel information indicative of an LDPC codeword. The channel information is split for input to the CDs, such that each CD receives channel information indicative of a portion of the LDPC codeword. Each CD outputs at least first soft information for bits of the codeword portion of that CD. The first soft information for the codeword is received by an LDPC decoder, which uses the soft information to produce a user bit sequence and second soft information about the user bit sequence. The system can cause the second soft information to be input to the plurality of CDs, such that iterative processing can occur for the codeword. Other aspects include a system providing clocking of one or more CDs at a frequency selected to balance codeword throughput of the CDs with codeword throughput of an LDPC decoder clocked by a second clock, and methods according to each system.

Abstract: In a decoding apparatus in a portable Internet terminal, a channel encoded symbol received from a transmitter is decoded by one of a chase-combining scheme and a code-combining scheme selected based on an ID value of the subpacket indicating a start position of the symbol. In this case, the chase-combining scheme is partly used for the encoded symbol of the information bit. With such a mode, decoding can be performed at a low code rate.

Abstract: A system including a forecasting module, a decoder module, and an error detecting module. The forecasting module is configured to forecast a number of erasures in an input signal, where the erasures include information about errors in the input signal due to a burst error. The decoder module is configured to decode codewords received in the input signal based on the erasures in response to the number of the erasures being less than or equal to a predetermined threshold. The decoder module is configured to not decode the codewords based on the erasures in response to the number of the erasures being greater than the predetermined threshold. The error detecting module is configured to (i) detect the burst error and (ii) decode the codewords in response to the decoder module not decoding the codewords due to the number of the erasures being greater than the predetermined threshold.

Abstract: The present invention relates to data processing apparatus and method, and a program which make it possible to scatter burst errors with respect to both codes of a product code. A block-wise interleaver performs interleaving A, which is a process of inputting data in the order of the column direction as one direction, and reading the data in the order of the direction diagonally downward to the right, NB bits by NB bits (=block by block) with respect to ND×NB×NA bits of a product code. Next, the block-wise interleaver performs interleaving B, which is a process of inputting data in the order of the column direction as one direction, and reading the data in the order of the row direction as the other direction, NB bits by NB bits with respect to (NC?ND)×NB×NA bits representing the parity portion of an inner code indicated by P, of the product code. The present invention can be applied to, for example, a recording/reproducing apparatus.

Abstract: Disclosed is a transmission device which transmits a systematic code obtained by adding parity bits to information bits. When the code rate of the systematic code is a value in a specific range determined by the decoding characteristic in a case where dummy bits are not inserted, a dummy bit insertion portion inserts dummy bits into the information bits and shifts the decoding characteristic, so that the code rate assumes a value outside a specific range determined by the decoding characteristic after shifting. An encoding portion performs systematic encoding of the information bits into which the dummy bits are inserted, and deletes the dummy bits from the results of the encoding to generate a systematic code, and a rate matching portion, performs rate matching such that the size of the systematic code is equal to a size determined by the physical channel transmission rate, and transmits the systematic code.

Abstract: A decoding apparatus and method are described. The decoder includes N successive decoder groups numbered 1 to N arranged in series. Each decoder group includes primary decoding means for decoding the first sequence of codewords in combination with the source sequence of symbols to produce a sequence of primary decoded symbols; intermediate interleaving means for interleaving the sequence of primary decoded symbols using intra-block permutations on the source sequence of symbols and inter-block permutations on each intra-block permuted block across the predetermined number of the intra-block permuted blocks to produce a sequence of intermediate symbols; secondary decoding means for decoding the second sequence of codewords in combination with the sequence of intermediate symbols and a sequence of interleaved source symbols to produce a sequence of secondary decoded symbols; and de-interleaving means for de-interleaving the sequence of secondary decoded symbols to produce a sequence of estimated symbols.

Abstract: Provided are a forward error correction decoder and a method thereof. The method comprises: generating mapping information on a location of a symbol; deciding a location of an error in a packet; deciding an erasure of a subsequent packet following the packet on the basis of the error location and the mapping information; and decoding the subsequent packet on the basis of the erasure.

Abstract: Systems and methods for iterative decoding in the presence of burst errors are provided. The methods include acquiring extrinsic and channel information for received ECC-encoded data symbols, selecting a window including a subset of the received ECC-encoded symbols, determining the likelihood of a burst error in the window, and updating channel information for selected data symbols in the window. In one embodiment, burst error detection circuitry is used to determine the likelihood of a burst error in the window.

Abstract: A digital data recording/reproducing method includes the steps of: interleaving data on a PI code for each PI code of a 208-row ECC block; and converting a short burst error into random errors by dispersing errors on the PI codes. Moreover, the digital data recording/reproducing method increases correction capability against several bytes to several tens bytes of errors generated at random without changing burst error correction length by performing this processing for respective PI codes by using interleave rules that are different as much as possible from one another.

Abstract: A digital data recording/reproducing method includes the steps of: interleaving data on a PI code for each PI code of a 208-row ECC block; and converting a short burst error into random errors by dispersing errors on the PI codes. Moreover, the digital data recording/reproducing method increases correction capability against several bytes to several tens bytes of errors generated at random without changing burst error correction length by performing this processing for respective PI codes by using interleave rules that are different as much as possible from one another.

Abstract: A method for operating a contention-free interleaver for channel coding is provided that includes generating a sub-table based on a data block size, N, and an offset vector, v, of length x and generating an interleave table based on the sub-table. For a particular embodiment, the interleave table is generated based on the sub-table by generating a plurality of multiplets that together form the interleave table. In addition, the sub-table may be generated based on the data block size and the offset vector by (i) rounding the data block size up to a nearest multiple of the length, x, of the offset vector to generate a modified block size, N?, and (ii) generating the sub-table of a size equal to N?/x.

Abstract: A method for performing Viterbi decoding using a reduced trellis memory is provided that includes dividing a block of data into a plurality of segments. A feed-forward process is performed on each of the segments to generate a trellis for each of the segments. A traceback process is performed on each of a plurality of overlapping segment pairs, each segment pair comprising a first segment and a second segment, to generate a traceback result for the first segment and a traceback result for the second segment. The traceback result for the second segment is discarded to generate a decoder output based on the traceback result for the first segment.

Abstract: A digital data recording/reproducing method includes the steps of: interleaving data on a PI code for each PI code of a 208-row ECC block; and converting a short burst error into random errors by dispersing errors on the PI codes. Moreover, the digital data recording/reproducing method increases correction capability against several bytes to several tens bytes of errors generated at random without changing burst error correction length by performing this processing for respective PI codes by using interleave rules that are different as much as possible from one another.

Abstract: Embodiments disclosed herein address the need in the art for an efficient multi-symbol deinterleaver. In one aspect, a plurality of memory banks are deployed to receive and simultaneously store a plurality of values, such as soft decision values determined from a modulation constellation, in accordance with a storing pattern. In another aspect, the storing pattern comprises a plurality of cycles, a selected subset of the plurality of memory banks and an address offset for use in determining the address for storing into the respective memory banks indicated for each cycle. In yet another aspect, the stored values may be accessed in order with a sequentially increasing index, such as an address. Various other aspects are also presented. These aspects have the benefit of allowing multiple symbol values to be deinterleaved in an efficient manner, thus meeting computation time constraints, and conserving power.

Abstract: An apparatus for encrypting and decrypting an original data stream is provided. The apparatus comprises: a key including a key-algorithm, an interleaver having at least one dynamically changeable interleaving parameter, and a de-interleaver adapted to communicate with a communication channel.

Abstract: An outer encoder includes a bit detector that receives a turbo stream provided with a parity insertion region and that detects data bits from the turbo stream, an encoder that convolution-encodes the detected data bits, and a bit inserter that inserts an encoded value outputted from the encoder into the parity insertion region in the turbo stream.

Abstract: A memory access device includes logic to switch data from a processor memory bus to a memory bus in a first operational mode, and to switch data from a test bus to the memory bus in a second operational mode, and logic to switch address signals from the processor memory bus to the memory bus in the first operational mode. In the second operational mode the device accepts from the test bus a starting memory address for memory reads and writes, and automatically and independently of the test bus adjusts a memory address for reads and writes during burst memory operations.

Abstract: A digital television transmitting system includes a pre-processor, a packet generator, an RS encoder, and a trellis encoder. The pre-processor pre-processes enhanced data by coding the enhanced data for first forward error correction and expanding the FEC-coded enhanced data. The packet generator generates enhanced data packets including the pre-processed enhanced data and main data packets and multiplexes the enhanced and main data packets. Each enhanced data packet includes an adaptation field in which the pre-processed enhanced data are inserted. The RS encoder performs RS encoding on the multiplexed data packets for second forward error correction, and the trellis encoder performs trellis encoding on the RS-coded data packets.

Abstract: An efficient method and system for detecting frame slip in an inband signalling block in pulse code modulation. The effect of frame slip on the inband signalling block is that the bits following the frame slip are transferred from the signalling block into an adjacent block. The octet slip is detected by searching an error bit in a signalling block by comparing it to a sample block. If an error bit is found, an error count for the adjacent block starting from the error bit is calculated. If the error count is more than one, a second error bit of the signalling block is searched (26) and bits of the adjacent block after second error bit are verified (27). If bits of the adjacent block after the second error bit are not correct, the octet slip cannot be assumed (29). Otherwise the octet slip can be assumed by analyzing error count and error bits.

Abstract: A method of storing DVB-H data from a DVB-H data burst, the method comprising: identifying erasures in the data burst; and storing non-erasure data from the data burst in memory locations of a memory that would be used to store erasures.

Abstract: A method and apparatus for decoding received digital data representing video, audio, information or a combination thereof. After a forward error correction (FEC) frame sync lock is detected, a counter is incremented corresponding to the number of identical control words decoded from the received data. If the number of identical control words is above a threshold value, the control word is used to operate the decoder in a mode corresponding to the control word. Otherwise, the system repeats the operation of determining whether a FEC frame sync lock is detected.

Abstract: The invention relates to an encoding system and method for generating concatenated codes which utilize interleaving and data puncturing. The method includes selecting first and second puncture location sets defining desired puncture locations in non-interleaved and interleaved data sequences, respectively. A puncture-constrained interleaver is provided, which permutes the first puncture location set into the second puncture location set, so as to provide desired regular puncture patterns for all constituent codes. In a preferred embodiment, the puncture-constrained interleaving alters a symbol location relative to a puncture mask so as to satisfy a pre-defined spread or distance constraint.

Abstract: A system for transmitting a digital broadcasting signal includes a Reed-Solomon encoder that encodes a dual transport stream including a normal stream and a turbo stream to obtain an encoded dual transport stream; an interleaver that interleaves the encoded dual transport stream to obtain an interleaved dual transport stream; and a turbo processor that detects the turbo stream from the interleaved dual transport stream to obtain a detected turbo stream, encodes the detected turbo stream to obtain an encoded turbo stream, stuffs the encoded turbo stream back into the interleaved dual transport stream to obtain a reconstructed dual transport stream, and compensates the reconstructed dual transport stream for a parity error due to the encoded turbo stream to obtain a parity-compensated dual transport stream.

Abstract: A turbo stream processing device and method. A turbo stream processing device includes a turbo stream detector to receive a dual transmission stream in which a turbo stream and a normal stream are multiplexed, and to detect the turbo stream; an outer encoder to encode the turbo stream; an outer encoder to interleave the turbo stream which is encoded at the outer encoder; and a turbo stream stuffer to reconstruct the dual transmission stream by stuffing the interleaved turbo stream into the dual transmission stream. Accordingly, the reception performance can be enhanced by more robustly processing the turbo stream in the dual transmission stream.

Abstract: A virtual display driver that can be dynamically loaded and unloaded for remote control of a host computing system. The host computing system includes an original display driver that updates an output display of the computing system based on display commands. A remote control executive executes in kernel-mode within an operating environment provided by the computing system and dynamically loads and unloads the virtual display driver as requested by a user. The remote control executive inserts hooks within the functions provided by the original display driver to trap the display commands received by the original display driver and direct the commands to the virtual display driver for communication to a remote client computer.

Abstract: A method and apparatus for decoding data is provided herein to show how to turbo decode LDPC codes that contain a partial dual diagonal parity-check portion, and how to avoid memory access contentions in such a turbo decoder. During operation, a decoder will receive a signal vector corresponding to information bits and parity bits and separate the received signal vector into two groups, a first group comprising signals corresponding to the information bits and one or more parity bits, a second group comprising a remainder of the parity bits. The first group of received signals is passed to a first decoder and the second group of received signals is passed to a second decoder. The decoders are separated by an interleaver and a deinterleaver. Iterative decoding takes place by passing messages between the decoders, through the interleaver and the deinterleaver, and producing an estimate of the information bits from the output of the first decoder.

Abstract: A technique for resolving access contention in a parallel turbo decoder is described. The technique includes associating a plurality of buffer memories with the subdecoders so that accesses to banks of a shared interleaver memory can be rescheduled. Accesses can be rescheduled to prevent simultaneous accesses to a single bank of the shared interleaver memory based on an interleaver pattern.

Abstract: A digital television transmitting system includes a pre-processor, a packet generator, an RS encoder, and a trellis encoder. The pre-processor pre-processes enhanced data by coding the enhanced data for first forward error correction and expanding the FEC-coded enhanced data. The packet generator generates enhanced data packets including the pre-processed enhanced data and main data packets and multiplexes the enhanced and main data packets. Each enhanced data packet includes an adaptation field in which the pre-processed enhanced data are inserted. The RS encoder performs RS encoding on the multiplexed data packets for second forward error correction, and the trellis encoder performs trellis encoding on the RS-coded data packets.

Abstract: A MIMO transmitter comprises a scrambler; an encoder parser responsive to the scrambler; a forward error correction encoder responsive to the encoder parser, wherein the encoder applies a parity check matrix derived from a base matrix; an interleaver responsive to the forward error correction encoder; a QAM mapping module responsive to the interleaver; an inverse fast Fourier transform module responsive to the QAM mapping module; and an output module responsive to the inverse fast Fourier transform module.

Abstract: A method for encrypting and decrypting an original data stream comprising: (A) transmitting a copy of a key to an interleaver and to a de-interleaver, wherein the key includes a key-algorithm configured to describe an evolution in time of at least one interleaving parameter; (B) interleaving the original data stream by using the interleaver, wherein the interleaver compensates for a change in latency caused by at least one dynamically changeable interleaving parameter; and (C) recovering the original data stream from the interleaved data stream propagated through the communication channel by using the de-interleaver adapted to communicate with the communication channel, wherein the de-interleaver compensates for a change in latency caused by at least one dynamically changeable interleaving parameter.

Abstract: A digital data recording/reproducing method includes the steps of: interleaving data on a PI code for each PI code of a 208-row ECC block; and converting a short burst error into random errors by dispersing errors on the PI codes. Moreover, the digital data recording/reproducing method increases correction capability against several bytes to several tens bytes of errors generated at random without changing burst error correction length by performing this processing for respective PI codes by using interleave rules that are different as much as possible from one another.

Abstract: Disclosed is a method and apparatus for completely recovering received data with high reliability using LDPC codes without short-sized cycles in a digital communication system using an error-correcting code. The method includes performing exponent conversion of a predetermined number of exponent matrixes stored in advance in a memory so as to generate new exponent matrixes based on the exponent conversion, and generating new LDPC codes using the new exponent matrixes.

Abstract: The present invention provides a method and apparatus for the efficient implementation of a totally general convolutional interleaver in a discrete multi-tone (DMT)-based digital subscriber line (xDSL) system, such as a modem or the like, that uses forward error correction (FEC) and convolutional interleaving to combat the effects of impulse noise and the like. More specifically, the present invention provides a method and apparatus for implementing a general convolutional interleaver, with no constraints, in an efficient manner, using (D?1)*(I?1)/2 memory locations for the interleaved data in all cases.

Abstract: Embodiments disclosed herein address the need in the art for an efficient multi-symbol deinterleaver. In one aspect, a plurality of memory banks are deployed to receive and simultaneously store a plurality of values, such as soft decision values determined from a modulation constellation, in accordance with a storing pattern. In another aspect, the storing pattern comprises a plurality of cycles, a selected subset of the plurality of memory banks and an address offset for use in determining the address for storing into the respective memory banks indicated for each cycle. In yet another aspect, the stored values may be accessed in order with a sequentially increasing index, such as an address. Various other aspects are also presented. These aspects have the benefit of allowing multiple symbol values to be deinterleaved in an efficient manner, thus meeting computation time constraints, and conserving power.

Abstract: An erasure forecasting system includes a control module, an erasure feed-forward module, and an erasure decoder. The control module selects erasure parameters and determines error-detection thresholds for forecasting erasure in an input signal. The erasure feed-forward module receives the input signal, forecasts erasure in the input signal, generates an erasure feed-forward signal based on the erasure parameters and the error-detection thresholds, and generates codewords based on the erasure feed-forward signal and the input signal. The erasure decoder determines that the input signal is one of erroneous and not erroneous based on the erasure feed-forward signal.

Abstract: In an exemplary embodiment, a base station includes an antenna for transmitting signals on a downlink to a plurality of user devices. The base station also includes a processor, and memory in electronic communication with the processor. Interleaving instructions are stored in the memory. The interleaving instructions are executable by the processor to interleave coded data in accordance with an interleaving algorithm in order to generate interleaved data. The interleaving algorithm is configured to accommodate use of different transmission bandwidths for data transmission. OFDMA processing instructions are also stored in the memory. The OFDMA processing instructions are executable by the processor to perform OFDMA processing on the interleaved data. The OFDMA processing facilitates the use of a varying number of sub-carriers for channel transmission.

Abstract: A system, an apparatus and a method for transmitting/receiving data coded by a low density parity check matrix code are provided. The apparatus for transmitting data coded by a low density parity check code includes: a low density parity check encoder for encoding input data based on the low density parity check code; and a bit puncturer for puncturing columns in an order of columns which least degrade a performance caused by puncturing in the low density check code according to a code rate of an output data. Accordingly, the low density parity check code having superior performance can be implemented to the next generation mobile communication system supporting various code rates.

Abstract: A data transmission system respectively encodes successive bits representing information to be transmitted. An interleaver receives the bits from the encoder and interleaves the bits. The interleaver includes a memory and a memory read write controller configured to write the bits to the memory in accordance with a diagonal write pattern and to read the bits from the memory in a diagonal read pattern. A symbol mapper receives the interleaved bits and maps the encoded interleaved bits into symbols using a transmission format.

Abstract: A circuit is provided for performing interleaving and deinterleaving functions in a digital communication system. The circuit includes a single-port memory that reads first data units from a first interleaved sequence of address locations to generate a first data stream and that writes second data units from a second data stream to the address locations. A first address generator module communicates with the single-port memory and generates a first interleaved sequence of addresses that correspond to the address locations and correspond to one of an interleaving function and deinterleaving function between the first data stream and the second data stream.

Abstract: A method and apparatus for decoding and de-interleaving a received encoded and interleaved signal, the method employing and the apparatus including a single decoder coupled to a common buffer, the common buffer size equal to a frame of the received signal and the method further employing, and the apparatus further including, an address controller that causes data to be de-interleaved when read from the buffer and data to be interleaved when written to the buffer.

Abstract: Algebraic method to construct LDPC (Low Density Parity Check) codes with parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices. A novel approach is presented by which identity sub-matrices undergo cyclic shifting, thereby generating CSI sub-matrices that are arranged forming a parity check matrix of an LDPC code. The parity check matrix of the LDPC code may correspond to a regular LDPC code, or the parity check matrix of the LDPC code may undergo further modification to transform it to that of an irregular LDPC code. The parity check matrix of the LDPC code may be partitioned into 2 sub-matrices such that one of these 2 sub-matrices is transformed to be a block dual diagonal matrix; the other of these 2 sub-matrices may be modified using a variety of means, including the density evolution approach, to ensure the desired bit and check degrees of the irregular LDPC code.

Abstract: An interleaver parameter generator circuit used to calculate and generate on an as needed basis interleaver parameters for interleaving blocks of information of varying lengths in accordance with a pseudorandom pattern defined by the 3GPP standard. The interleaver parameter generator circuit calculates and generates the defined interleaver parameters based on an input parameter that represents the length of the block of information to be interleaved. At least one of the defined parameters is calculated and generated using a decomposed form of its definition. The interleaver parameter generator circuit uses well known circuit blocks such as multipliers, subtractors, Compare-and-Select circuits and other circuits to calculate and generate the defined parameters.

Abstract: Methods, apparatuses, and systems are presented for performing data encoding involving receiving a sequence of data bits, encoding the sequence of data bits in accordance with a parity check matrix (H-matrix) to generate a sequence of encoded bits, wherein the H-matrix is capable of being partitioned into a first matrix and a second matrix, the first matrix being a dual-diagonal matrix, the second matrix comprising one or more vertically stacked sub-matrices, each sub-matrix consisting of a plurality of columns, each column having a column weight of no more than 1, wherein the second matrix is capable of being expressed as a product of a parity check matrix, an interleaver permutation matrix, and a repeat block matrix, and the interleaver permutation matrix satisfies a clash-free interleaver constraint, and outputting the sequence of encoded bits.

Abstract: A 2-dimensional interleaving method is disclosed. The method comprises dividing a frame of input information bits into a plurality of groups and sequentially storing the divided groups in a memory; permuting the information bits of the groups according to a given rule and shifting an information bit existing at the last position of the last group to a position preceding the last position; and selecting the groups according to a predetermined order, and selecting one of the information bits in the selected group.

Abstract: A 2-dimensional interleaving method is disclosed. The method comprises dividing a frame of input information bits into a plurality of groups and sequentially storing the divided groups in a memory; permuting the information bits of the groups according to a given rule and shifting an information bit existing at the last position of the last group to a position preceding the last position; and selecting the groups according to a predetermined order, and selecting one of the information bits in the selected group.