Abstract: An interleaver (11b) for filling an interleaver matrix (51) used in interleaving a packet of bits for transmission as symbols via a wireless communication channel in a wireless communication system (11 12) including a modulator (11c), the interleaver (11b) having a number of rows (or columns, depending on whether bits are pulled column-wise or row-wise for encoding as symbols by the modulator) that is not divisible by the number of bits in a symbol, but having at least as many bits as in a packet, and so having, unavoidably, more elements than there are bits in a packet.

Abstract: A memory-efficient convolutional interleaver/deinterleaver with a memory array, a write commutator, and a read commutator wherein the commutators perform their respective write and read operations relative to a preselected memory cell after a predetermined delay. The delay is chosen using a modulo-based technique, such that an efficient implementation of a Ramsey Type-II interleaver is realized.

Abstract: A data transmission system is provided for transmitting user data to and receiving data from a communication channel, including a parity check matrix having M tiers, wherein M?2, Dmin=2*M for M=1 . . . 3 or 2*M?Dmin?6 for M>3, wherein Dmin is the minimum Hamming distance, tc=M, wherein tc is the column weight, and cycle?4=0. A linear block encoder encodes the user data in response to the parity check matrix, and a transmitter transmits an output of the linear block encoder to the communication channel. A soft channel decoder decodes data, and a soft linear block code decoder to decode data decoded by the soft channel decoder in response to the parity check matrix.

Abstract: A syndrome S is found from a received information D and a parity check matrix for correcting burst errors up to b bits. The syndrome S is inputted to p sets of burst error pattern generation circuits that correspond to information frames overlapping each other by (b?1) bits and each having a length of 2b bits. If a burst error is included entirely in any one of the p sets of burst error pattern generation circuits, then the burst error pattern is outputted. An error pattern calculation circuit executes OR respectively on overlapping bits output from the error pattern generation circuits. By executing exclusive OR on an output of the error pattern calculation circuit and received information D, corrected information Ds is obtained. As a result, a burst error in the received information can be detected and corrected.

Abstract: A memory optimized system and method for data interleaving/de-interleaving are disclosed. A data interleaver/de-interleaver may be implemented with a memory device and an improved data interleaver/de-interleaver. The improved data interleaver/de-interleaver may be implemented with a controller, a first array, and a second array. The first array identifies a maximum depth value for each of a plurality of memory segments responsive to both a block data length and the desired interleaving/de-interleaving depth. The second array comprises an index associated with each of the plurality of memory segments that may be used to derive write and read addresses.

Abstract: Disclosed is a turbo channel encoding and decoding device for a CDMA communication system. When the input data frames are very short, the device assembles input frames into one super frame of an appropriate length and then encodes and decodes the super frame. After frame encoding and decoding, the frames are reassembled into the original input frames.

Abstract: A turbo channel encoding/decoding device for a CDMA communication system. The device segments an input frame into multiple sub frames of an appropriate length when the input data frame is very long, and then encodes and decodes the sub frames. Otherwise, when the input data frames are very short, the device composes input frames into one super frame of an appropriate length and then encodes and decodes the super frame. After frame encoding/decoding, the frames are recomposed into the original input frames.

Abstract: Techniques are described for maintaining the orthogonality of user waveforms in multi-user wireless communication systems, such as systems using the code division multiple access (CDMA) modulation scheme in the presence of frequency-selective fading channels. Unlike conventional systems in which spreading is performed on individual information-bearing symbols, the “chip-interleaved block-spreading” (CIBS) techniques described herein spread blocks of symbols. A transmitter includes a block-spreading unit to form a set of chips for each symbol of a block of information-bearing symbols and to produce a stream of chips in which the chips from different sets are interleaved. A pulse shaping unit within the transmitter generates a transmission signal from the stream of interleaved chips and transmits the signal through a communication channel.

Abstract: A method for interleaving data frames transmitted via a modem pool, each of the data frames including a plurality of codewords having a predefined level of error correction, including assigning the data frames to corresponding modem timeframes, where codeword symbols in each of the data frames are assigned to time slots in the modems in the corresponding timeframes such that the level of error correction is sufficient to correct error/loss caused to any of the symbols given a predefined level of modem loss/malfunction, and moving any of the codeword symbols assigned to one of the timeframes to another of the timeframes such that the level of error correction is sufficient to correct error/loss caused to any of the symbols given a predefined level of cross-modem error burst while preserving the level of error correction sufficient to correct error/loss caused to any of the symbols given the level of modem loss/malfunction.

Abstract: A digital signal forming method and apparatus therefore for improved error correction capability without requiring a change to the number of error correcting codes includes forming a plurality of data sectors from an information stream, forming sector data blocks by dividing up each data sector, adding error correction codes to the sector data blocks, and combining the sector data blocks to produce interleaved allocations (also known as recording sectors).

Abstract: An interleaver that implements the LCS turbo interleaver algorithm utilized by the CDMA2000 standard is described. The interleaver includes a first computation unit for receiving an input address and computing a first sequential interleaved address during a first clock cycle in response thereto. A second computation unit is included for receiving an input address and computing a second sequential interleaved address during the first clock cycle in response thereto. The interleaver further includes a comparator for determining whether the first or the second sequential interleaved address is invalid and generating a signal in response thereto. The output of the comparator provides a control signal to a switch which selects the first or the second sequential interleaved address as an output interleaved address for the first clock cycle. The interleaver is further designed to move in a forward direction or a reverse direction.

Abstract: A process and apparatus is described for recovering from optical transmission degradation due to scintillation effects in optical free space. A payload bit stream is encoded into Reed-Solomon codewords. These are fragmented and distributed as interleaved segments over a cell matrix of a SDRAM buffer store which is made large enough to correct a burst error occurring over 20 million consecutive bits. The rate imbalance between conventional read vs. write operations for SDRAM devices, which would otherwise obviate their use in this application by preventing real time operation, is overcome by an address remapping that avoids having to changing page addresses each time SDRAM memory is referenced. The remapping facilitates a more nearly equal allocation of READ overhead and WRITE overhead. An optical communications system employs at both the transmit and receive ends, substantially equivalent SDRAM buffer with address remapping capability.

Abstract: A data packet type communication system utilizes packet framing wherein preambles are split into two or more subpreambles, separated by a number of data or a priori known symbols. A receiver chooses among individual and combined subpreamble options for determining synchronization. When a noise impulse prevents detection of one subpreamble, the impulse is detected, and preamble correlation proceeds using an unaffected subpreamble. When no impulse is detected, combined subpreambles are used.

Abstract: A communication system 100 employs turbo encoding having a turbo interleaver 106 that interleaves input data 101 efficiently with little use of system resources. The turbo interleaver 106 reads address locations of the data bits into an interleaver matrix array 206 row by row and interleaves the address locations by bit reversal of the row indexes with accompanying permutation of the corresponding address locations in the rows of the matrix 206, bit reversal of the column indexes with accompanying permutation of the corresponding address locations in the columns of the matrix 206 and shifting the address locations within each row a predetermined number of column locations based on the particular row number.

Abstract: Memory may be partitioned into ever-sliding FIFOs. Each of the FIFOs may be stacked end-to-end in memory with the oldest data at the base offset and the newest at the end (or vice-virsa). Each symbol, the pointer may be incremented (modulo the set size) by an appropriate amount (typically J more than for the previous symbol). After each set, the pointers may be incremented by J more than the previous increment and the process starts over, wrapping around the memory if the end of the memory is reached. After a preset number of symbols, the process may restart from an increment of J. Alternatively, the pointers may be decremented rather than incremented. Thus, the newest symbol cannibalizes the memory position vacated by the oldest symbol in the current FIFO, causing the FIFOs to “slide”, providing for a very efficient and reliable use of memory for error-correcting code interleaving.

Abstract: An efficient method for finding all the possible corrections of a bust of length b and e random errors consists of finding a polynomial whose roots are the candidate location for l— the location of the beginning of the burst—thus avoiding the search over all possible values of l (it is assumed that the burst is non-trivial, i.e., at least one of its errors has a non-zero value). In order to reduce the number of spurious solutions, it is assumed that the number of syndromes is t=2e+b+s, where s is at least 2. The larger the value of s the less likely it is that the algorithm will generate “spurious” solutions. Once the location of the burst is known, standard procedures are used to determine the magnitudes of the burst errors and the location and magnitude of the random errors.

Abstract: A transport systems is equipped with a burst error detecting unit that monitors a predetermined byte, which is specified in advance in a frame to be monitored, in a transmission signal having header information and data information multiplexed into the frame in bytes. The burst error detecting unit detects a burst error based on a change in a state of occurrence of a bit error in the predetermined byte in a predetermined time window.

Abstract: A convolutional interleaver includes an interleaver memory partitioned into a plurality of circular buffers, wherein each of the circular buffers has associated write pointers and read pointers, and wherein the interleaver is configured to selectively read symbols from an input vector and store the input symbols in the interleaver memory in accordance with the write pointers, and to selectively read symbols from the interleaver memory to form an output vector in accordance with the read pointers. In one aspect, symbols are written to the interleaver prior to reading; in another, the position of the write pointer corresponds to the position of the read pointer within the circular buffer, and symbols are read from said interleaver memory prior to writing. In another aspect, a de-interleaver applies the concepts and algorithms described above in an inverse manner.

Abstract: A memory-efficient convolutional interleaver/deinterleaver with a memory array, a write commutator, and a read commutator wherein the commutators perform their respective write and read operations relative to a preselected memory cell after a predetermined delay. The delay is chosen using a modulo-based technique, such that an efficient implementation of a Ramsey Type-II interleaver is realized.

Abstract: A method and apparatus for coding and decoding a sequence of data packets with use of a novel class of forward error correcting codes having coding rates greater than 1/2 which nonetheless provide relatively high levels of channel protection against burst erasures with a relatively low decoding delay. In accordance with certain illustrative encoder embodiments of the present invention, the source information contained in each of a plurality of packets to be coded is similarly divided into a plurality of (similar) corresponding portions, and “checksums” are computed over multiple data packets, each such checksum being based on different (i.e., non-corresponding) portions of at least two of the multiple packets. These “checksums” are then advantageously appended to various subsequent data packets to be coded.

Abstract: For iterative detection, an ISI decoder is provided to receive an input waveform comprising an input sequence of symbols and to output an intermediate waveform. The ISI decoder comprises a branch metric generation mechanism and a cost function update mechanism. A code decoder is provided to receive the intermediate waveform via a permutation path, to output an output waveform with the effects of ISI mitigated, and to output new information concerning the input waveform with less influence of the effects of ISI. The cost function update mechanism is adapted to receive branch metric information from the branch metric mechanism and to receive the new information via a repermutation path. A substitute mechanism is provided to substitute the branch metric information received by the cost function update mechanism with substitute information independent of the branch metric information when a given group of symbols of the input waveform are subject to a burst error.

Abstract: An apparatus and method for efficiently performing error control coding tasks. An important aspect of the present invention is the provision of an ECC engine that responds to a specialized ECC instruction set having a plurality of instructions, such as a convolutional encoding instruction, a convolutional decoding instruction, and a cyclic redundancy code (CRC) instruction. The ECC engine has a plurality of functional building blocks (e.g., a configurable convolutional encoding functional block, a convolutional configurable decoding functional block, and a configurable cyclic redundancy check (CRC) functional block) that can be programmed or configured. A single instruction provided to the error control coding engine configures one of the functional blocks to execute a error control coding algorithm specified by the instruction. Each instruction also includes a plurality of fields that can be modified by the user.

Abstract: A 2-dimensional interleaving method is disclosed. The method comprises dividing a frame of input information bits into a plurality of groups and sequentially storing the divided groups in a memory; permuting the information bits of the groups according to a given rule and shifting an information bit existing at the last position of the last group to a position preceding the last position; and selecting the groups according to a predetermined order, and selecting one of the information bits in the selected group.

Abstract: The present invention provides for adaptive and multimode decoding, in a data packet-based communication system, to provide improved received signal quality in the presence of burst erasures or random bit errors, with particular suitability for real-time, delay sensitive applications, such as voice over Internet Protocol. In the presence of burst erasures, the adaptive multimode decoder of the present invention provides burst erasure correction decoding, preferably utilizes a maximally short (MS) burst erasure correcting code, which has a comparatively short decoding delay. Depending upon the level of such burst erasures, different rate MS codes may be utilized, or other codes may be utilized, such as hybrid or multidescriptive codes. When no burst erasures are detected, the adaptive multimode decoder of the present invention provides random bit error correction decoding, in lieu of or in addition to corresponding burst erasure correction coding.

Abstract: To implement plural types of interleaving for decoding each of various codes in an adaptively suitable manner for the code by a simple circuit construction, an interleaver (100) in an element decoder includes a plurality of data storage circuits (407), and in addition, a control circuit (400) which generates address data for use to write data to the storage circuits (407) and address data for use to read date from the storage circuits (400), an address data selection circuit (405) which selects address data to be distributed to the plurality of storage circuits (407) according to a mode indicating the configuration of a code including the type of an interleaving to be done, an input data selection circuit (406) which selects data to be distributed to the plurality of storage circuits (407) according to the mode, and an output data selection circuit (408) which selects data to be outputted according to the mode. Of the plural storage circuits (407), a one to be used is selected.

Abstract: An encoding device adds parity data to source data and outputs the data. The parity data is generated based on the output of the first encoding unit and the second encoding unit. The first encoding unit encodes the source data. The second encoding unit encodes the data obtained by a plurality of interleavers connected in parallel. The plurality of interleavers perform different randomizing processes on the source data.

Abstract: A memory-efficient convolutional interleaver/deinterleaver with a memory array, a write commutator, and a read commutator wherein the commutators perform their respective write and read operations relative to a preselected memory cell after a predetermined delay. The delay is chosen using a modulo-based technique, such that an efficient implementation: of a Ramsey Type-II interleaver is realized.

Abstract: An interleaver in which a frame of data to be interleaved is stored in at least a portion of an array having R rows and C columns, the portion having Nr(l) rows and Nc(l) columns that satisfy the inequality Nr(l)×Nc(l−1)<L<Nr(l)×Nc(l) where Nc(l) is a prime number and Nc(l−1) is the highest prime number less than Nc(l). The elements of each row are permuted according to a predetermined mathematical relationship, and the rows are permuted according to predetermined mapping.

Abstract: An interleaver for interleaving a set of K ordered elements is disclosed herein. The disclosed interleaver can be expressed as a single permutation that corresponds to two local dithering operations and a global permutation operation. The single permutation can be represented as a small collection of short vectors, and can be calculated recursively, allowing the interleaver to be both stored and implemented using a smaller amount of memory than conventionally possible.

Abstract: A syndrome S is found from a received information D and a parity check matrix for correcting burst errors up to b bits. The syndrome S is inputted to p sets of burst error pattern generation circuits that correspond to information frames overlapping each other by (b−1) bits and each having a length of 2b bits. If a burst error is included entirely in any one of the p sets of burst error pattern generation circuits, then the burst error pattern is outputted. An error pattern calculation circuit executes OR respectively on overlapping bits output from the error pattern generation circuits. By executing exclusive OR on an output of the error pattern calculation circuit and received information D, corrected information Ds is obtained. As a result, a burst error in the received information can be detected and corrected.

Abstract: In a data transmission method and system, user signals are transmitted wirelessly, and a maximum delay for the system has been defined. The system includes circuitry at the transmitting end for sequentially performing an outer and inner coding on the signals to be transmitted, and circuitry for performing a first interleaving after the outer coding. The interleaving length of the first interleaving is chosen within the scope of the maximum delay defined for the system. To ensure improved performance, the system includes circuitry for performing a second interleaving after the inner coding, and the interleaving length of the second interleaving is substantially equal to the interleaving length of the first interleaving.

Abstract: The present invention provides a method, a computer medium, and a device for a two stage S_Random interleaver that is constructed based on two optimization criteria. The distance spectrum properties of the code are maximized by designing an interleaver that increases the minimum effective free distance of the code. In addition, the interleaver is designed to reduce the correlation properties of the extrinsic information that is fed into the next stage decoder. Thus, the present invention utilizes the reduced correlation properties to provide a more efficient S-random interleaver with increased iterations, thus maximizing the bit error rate (BER) performance of the code with respect to iterative decoding.

Abstract: Construction of a Turbo code interleaver for blocks of any size is facilitated by partitioning the block into co-sets of predetermined size, permuting each co-set with an interleaver whose parameters are selected and optimized for the predetermined size, and recombining the elements of the permuted co-sets according to a predetermined order. Partitioning of the block into co-sets is accomplished by choosing a value n for the number of co-set, and assigning to each co-set those positions of the block having a common value for modulo-n of the block size. The permuted output may be punctured to maintain a desired ratio.

Abstract: A system receives information from users relating to activities that may impact a network. The system then automatically generates a ticket to track the activity. The system also automatically selects a recipient(s) for a notification message relating to the activity and transmits the notification message to the intended recipient(s).

Abstract: For iterative detection, an ISI decoder is provided to receive an input waveform comprising an input sequence of symbols and to output an intermediate waveform. The ISI decoder comprises a branch metric generation mechanism and a cost function update mechanism. A code decoder is provided to receive the intermediate waveform via a permutation path, to output an output waveform with the effects of ISI mitigated, and to output new information concerning the input waveform with less influence of the effects of ISI. The cost function update mechanism is adapted to receive branch metric information from the branch metric mechanism and to receive the new information via a repermutation path. A substitute mechanism is provided to substitute the branch metric information received by the cost function update mechanism with substitute information independent of the branch metric information when a given group of symbols of the input waveform are subject to a burst error.

Abstract: A programmable logic device can be programmed to configure its logic elements to approximate the normalization of probability values used in the operation of logMAP decoders, thereby significantly reducing the amount of logic resources required in the normalization procedure without significantly degrading performance. In the first preferred embodiment, normalization is achieved by approximating the normalization value by calculating an approximate normalization value which is then deducted from all &agr; values in the trellis at any time. This is done by logically ANDing all &agr; input probability values with the NOT of their own MSBs. The resulting outputs are then all bitwise ORed together, the output of which is the approximate normalization value. In another embodiment, the approximate normalization value is calculated using a fixed constant determinable at the outset of the logMAP decoder operation.

Abstract: Data is encoded to maximize subsequent recovery of lost or damaged compression parameters of encoded data. In one embodiment, at least one compression parameter is used to define a pseudorandom sequence and the data is shuffled using the pseudorandom sequence. In one embodiment, a bit reallocation process and code reallocation process are performed on the data to randomize the data.

Abstract: A turbo coding device includes a bit inserter for inserting at east one specific bit at a last position of a data bit stream being input to a first constituent encoder, and inserting at least one specific bit at a last position of an interleaved data bit stream being input to a second constituent encoder; the first constituent encoder for encoding the specific bit-inserted data bits to generate first parity symbols; an interleaver for interleaving the specific bit-inserted data bits; the second constituent encoder for encoding the interleaved data bits to generate second parity symbols; and a multiplexer for multiplexing outputs of the bit inserter, the first constituent encoder and the second constituent encoder.

Abstract: An address generator for generating addresses in an prescribed order in the case of writing/reading data to/from predetermined storage means, comprises a first address data generating means for generating a plurality of first address data which have predetermined address intervals, a second address data generating means for generating a plurality of second address data representing sequentially shifted positions of the first address data one row by one row within address intervals, and an addition means for generating addresses which have predetermined intervals in order by adding the second address data to the first address data.

Abstract: A novel and improved method and apparatus for address generation in an interleaver is provided. In accordance with one embodiment of the invention, an address is generated using a random address fragment and a bit reversed address fragment. The bit reversed address fragment is selected by first generating two consecutive candidate bit reversed fragments. The second bit reversed address fragment is selected when the first bit reversed address fragment generates an address that is greater than a maximum address. The address generator allows address generation for interleaver and deinterleaver frame sizes of N, where N is not an integer power of two, without any cycle penalty.

Abstract: There is provided a channel encoder having convolutional encoders concatenated in parallel or in series. The channel encoder includes a first encoder for encoding input information bits, an interleaver having a memory and an index generator, for modifying the order of the information bits in a predetermined method, a second encoder for encoding the output of the interleaver, first and second terminating devices for terminating frames of input and output information bits of the first and second encoders, a tail bit generator for storing tails bits used in frame termination, and a controller and a switch for controlling the above procedure.

Abstract: An interleaving apparatus is provided which stores input bits temporarily and transfers some of the bits only required to execute an operation to code each of the stored bits to a coding circuit. This allows a storage region to be decreased as compared with a conventional system.

Abstract: A high performance system and method for trellis coded modulation are provided by virtue of the present invention. In one embodiment, the trellis coded modulation technique optimizes code performance for a given implementation cost. Also, this trellis coded modulation technique provides optimal performance in the context of periodic symbol deletion, whether this deletion is due to intentional puncturing, the use of interleaving in the presence of fading, or the use of interleaving in an OFDM system used to communicate across a frequency-selective channel.

Abstract: A communication system implements detection of bad frames of information by utilizing multiple bit correction thresholds. Equipment used within the communication system adapts to different signaling environments by dynamically altering the bit correction threshold based on a history of the number of consecutive bad frames of information that have been previously erased and the number of bits corrected by a channel decoder (202). By implementing this dynamic bit correction threshold, sufficient bad frame indication (BFI) detection and receiver sensitivity can be obtained simultaneously, which results in an improved perceived audio quality to the end user.

Abstract: A burst error limiting symbol detector system includes a symbol detector circuit responsive to a truncated sample signal for detecting binary symbols encoded in a truncated sample signal with reference to at least one preselected reference level; a feedback equalizer circuit for providing a feedback equalizer signal for cancelling undesired samples in an input signal; a summing circuit, responsive to the input signal and the feedback equalizer signal for providing the truncated sample signal to the symbol detector circuit; and a feedback suppressor circuit responsive to the truncated sample being within a predetermined range of the preselected reference level for suppressing the feedback equalizer signal to prevent marginal detected binary symbols from contributing to the cancellation of undesired samples in the input signal.

Abstract: An error detecting device of received digital data solves a problem for detecting errors in a conventional device in that error detection following the Viterbi decoding performed on most important bits cannot detect errors even if they include a considerable amount of errors, and that odd sounds result from decoding of voice data, for example. The present error detecting device includes a Viterbi decoder for carrying out the Viterbi decoding of the received digital data, an error number decision portion for comparing a threshold value with the number of errors of the path metric obtained by the Viterbi decoding, and a voice decoder for decoding the received digital data, on which the error number decision portion decides that the number of errors is below the threshold value.

Abstract: An apparatus deinterleaves decoded symbols and outputs the deinterleaved symbols in an appropriate form for external devices. In order to achieve the deinterleaving and outputting processes, the apparatus sequentially stores the decoded symbols in response to enable signals and produces output data of P bits based on the stored decoded symbols by using two memory groups which alternately perform the storing and the producing processes. The operations of the two memory groups are controlled by an input control block and an output control block. The input control block produces the enable signals to control the two memory groups to thereby sequentially store the decoded symbols to the two memory groups. The output control block selects one of outputs provided from the two memory groups and provides the selected output as the output data of P bits.

Abstract: In an (de)-interleaver (201) for J long subsequences (640-646) of data units (612), FIFOs are mapped into a memory (245) in such a way that locations (240) needed for one FIFO are moving through the memory (245). A generator (208) modulo increments only a single pointer (p, 230) which activates memory locations (240-p). Thereby, increments .DELTA.j correspond to FIFO sizes. For some p, (de)-interleaver (201) reads (25) a data unit (612) from a location (240) and than writes a new data unit (612) into that location (240), thus saving set-up times to establish a pointer. Also, the (de)-interleaver (201) needs only a number of memory locations K=(D-1 ) corresponding to a (D-1) interleaving depth. The (de)-interleaver (201) as part of a system (200) is fully programmable and can transfer data in two directions. Also, (de-) interleaving parameters (D-1) and J can be reconfigured during data transmission.

Abstract: A weighted interleaving system (10) is used for correlated channel coding. The weighted interleaving system (10) includes a weighted interleaver (12) having a pseudo-random demultiplexer (18), a first branch (28), a second branch (30), a third branch (32) and a pseudo-random multiplexer (38). The pseudo-random demultiplexer (18) receives input data bits at an input (20) and randomly distributes the input data bits to first (22), second (24) and third (26) outputs of the pseudo-random demultiplexer (18). The first branch (28) in communication with the first output (22) delays the transmission of the input data bits routed to it by a minimum delay. The second branch (30) in communication with the second output (24) delays the transmission of the input data bits routed to it by a delay uniform in probability from the minimum delay to a maximum delay. The third branch (32) in communication with the third output (26) delays the transmission of the input data bits routed to it by the maximum delay.

Abstract: Turbo-coding in a communications system involves coding/decoding information in stages in order to avoid retransmission of a full L-bit packet upon occurrence of a packet error. In addition to a set of code bits generated by an encoder using a turbo-coding scheme, a punctured set of code bits is generated and stored in transmitter memory. The original set of code bits is transmitted as an L-bit data packet to a receiver which stores received data samples corresponding to the original set of code bits. The receiver decodes the data packet using a turbo-decoder and determines whether the data packet has been received in error. If so, the received data samples are maintained in memory, and a request for more information is made. Some or all of the punctured information is then forwarded from the transmitter to the receiver.