Burst Error Patents (Class 714/788)
  • Patent number: 7584401
    Abstract: A channel interleaving method and apparatus in a communication system using a low density parity check (LDPC) code. Upon receipt of information data bits, an encoder encodes the information data bits into an LDPC codeword using a predetermined coding scheme. A channel interleaver interleaves the LDPC codeword according to a predetermined channel interleaving rule. A modulator modulates the channel-interleaved LDPC codeword into a modulation symbol using a predetermined modulation scheme.
    Type: Grant
    Filed: July 14, 2006
    Date of Patent: September 1, 2009
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Song-Nam Hong, Jung-Soo Woo, Seung-Hoon Park, Deok-Ki Kim, Su-Ryong Jeong, Young-Kyun Kim, Dong-Seek Park
  • Patent number: 7568145
    Abstract: A system, method and machine-readable medium for pruning an S-random interleaver starting with an interleaver permutation having N elements and alternating between invalidating the last element of the interleaver permutation and invalidating the last element of a corresponding inverse interleaver permutation until the interleaver permutation has K elements, K being less than N, the method being characterized by the use of a reference vector having N flags and comprising: storing a value in an element of the reference vector corresponding to the value of the each element invalidated in the interleaver permutation.
    Type: Grant
    Filed: April 15, 2005
    Date of Patent: July 28, 2009
    Inventors: Libero Dinoi, Sergio Benedetto
  • Patent number: 7555694
    Abstract: In a communication system, information data bits are encoded in a preset coding scheme when the information data bits are input, and a Low Density Parity Check (LDPC) codeword is generated. The LDPC codeword is interleaved according to a preset channel-interleaving rule. A channel-interleaved LDPC codeword is modulated in a preset modulation scheme and a modulation symbol is generated.
    Type: Grant
    Filed: March 8, 2006
    Date of Patent: June 30, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gyu-Bum Kyung, Seung-Hoon Choi, Jae-Yoel Kim, Sung-Eun Park
  • Patent number: 7552376
    Abstract: A method, system and program product accurately model the error characteristics of a communications system, such as a tape storage system. Input parameters are entered which describe defect rates and sizes, Codeword Data Structure bytes, and any interleaving factor. Bit defects from simulated defect sources are generated, defined by the starting and ending bits of each defect within a codeword. Any codewords which are defect-free are filtered out and not processed further, thereby increasing the processing speed of the model. Within the defect streams, overlapping defects are merged, redefining defect regions by starting and ending bits. Because only the definitions are processed, not the entire length of the codewords or defects, processing efficiency is further enhanced. The number of defects that occur in each codeword is determined and the probability of the occurrence of N bytes in error per processed codeword may be computed.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: June 23, 2009
    Assignee: International Business Machines Corporation
    Inventor: Paul J Seger
  • Patent number: 7539930
    Abstract: Embodiments of the present invention provide a method, apparatus and system of protecting a wireless transmission. The method according to some demonstrative embodiments of the invention may include based on one or more burst-related sub-commands of a transmit command corresponding to a current packet to be transmitted during a burst period, applying a protection scheme to one or more subsequent packets of the burst period. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: May 26, 2009
    Assignee: Intel Corporation
    Inventors: Boris Ginzburg, Solomon B. Trainin
  • Patent number: 7530004
    Abstract: An error detection and correction apparatus includes three threshold logic units which make decisions based on current and previous bit values in a bit stream of block-coded data. One of the threshold logic units decodes the data stream based on an advancing time stream of data. Another threshold logic unit decodes the data stream based on a time-reversed stream of data, and the last threshold logic unit decodes the data stream based on a time-reversed input stream of data and a time-reversed set of decisions made by the first threshold logic unit. Each threshold logic unit generates decisions and a parity check of those decisions Error identification information is compared between the three streams of decisions and parity checks on those decisions, thereby producing error information, which is processed by a circuit which determines which is the most likely data transmitted.
    Type: Grant
    Filed: April 19, 2006
    Date of Patent: May 5, 2009
    Assignee: Neural Systems Corp.
    Inventors: Charles Sinclair Weaver, Constance Dell Chittenden, A. Brit Conner
  • Patent number: 7523377
    Abstract: An interleaver that implements the LCS turbo interleaver algorithm utilized by the CDMA2000 standard is described. The interleaver includes a first computation unit for receiving an input address and computing a first sequential interleaved address during a first clock cycle in response thereto. A second computation unit is included for receiving an input address and computing a second sequential interleaved address during the first clock cycle in response thereto. The interleaver further includes a comparator for determining whether the first or the second sequential interleaved address is invalid and generating a signal in response thereto. The output of the comparator provides a control signal to a switch which selects the first or the second sequential interleaved address as an output interleaved address for the first clock cycle. The interleaver is further designed to move in a forward direction or a reverse direction.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: April 21, 2009
    Assignee: QUALCOMM Incorporated
    Inventor: Steven J. Halter
  • Patent number: 7490282
    Abstract: Briefly, an apparatus, a method and a wireless communication device are provided. The wireless communication device includes a turbo encoder to generate an encoded data block and a transmitter to transmit a data sub-block of the encoded data block in a time slot of a physical channel of the wireless communication system. The encoded data block includes real time data.
    Type: Grant
    Filed: November 4, 2004
    Date of Patent: February 10, 2009
    Assignee: Intel Corporation
    Inventors: Paul Spencer, Boaz Pianka
  • Patent number: 7464319
    Abstract: An encoder encodes each of a plurality of data fragments into an encoded packet comprising a plurality of codewords, each codeword comprising a set of data bytes from the data fragment and at least one error-correction byte derived from the set of data bytes. A plurality of cross-interleavers each receive as input one of the plurality of codewords of the encoded packet, after which a concatenator concatenates a plurality of interleaved codewords output by the plurality of cross-interleavers into an interleaved packet to be sent over a network.
    Type: Grant
    Filed: August 13, 2003
    Date of Patent: December 9, 2008
    Assignee: Utah State University
    Inventors: Scott Budge, Yong Zhang
  • Patent number: 7441163
    Abstract: A digital data recording/reproducing method includes the steps of: interleaving data on a PI code for each PI code of a 208-row ECC block; and converting a short burst error into random errors by dispersing errors on the PI codes. Moreover, the digital data recording/reproducing method increases correction capability against several bytes to several tens bytes of errors generated at random without changing burst error correction length by performing this processing for respective PI codes by using interleave rules that are different as much as possible from one another.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: October 21, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Taku Hoshizawa, Shigeki Taira, Osamu Kawamae
  • Patent number: 7437650
    Abstract: An interleaver address generator is provided with pruning avoidance technology. It anticipates the points in time when incorrect addresses are computed by an IAG, and bypasses these events. It produces a stream of valid, contiguous addresses for all specified code block sizes. A single address computation engine firstly ‘trains’ itself about violating generated addresses (for a related block size) during the initial H1 half-iteration of decoder operation, and then produces a continuous, correct stream of addresses as required by the turbo decoder. Thus regions of pruned addresses are determined, and then training is performed only in these regions. Thus, computation and population of a pruned event table is determined in less than 1/10 the time required to do a conventional style full training. The resulting pruned event table is compressed down to 256 bits.
    Type: Grant
    Filed: April 12, 2005
    Date of Patent: October 14, 2008
    Assignee: Agere Systems Inc.
    Inventors: Mark Andrew Bickerstaff, Yi-Chen Li, Chris Nicol, Bejamin John Widdup
  • Patent number: 7434147
    Abstract: Apparatus, and an associated method, for recovering the informational content of an encoded data block. Data bursts are delivered to a receiver. A series of data bursts together include all of the informational content of the encoded data block. A detector detects delivery to the receiver of the data bursts. A determiner determines indicia associated with the communicated data. And, responsive thereto, the data is decoded, selectably utilizing fewer than all of the data bursts that form the encoded data block.
    Type: Grant
    Filed: November 17, 2004
    Date of Patent: October 7, 2008
    Assignee: Research In Motion Limited
    Inventor: Matthias Wandel
  • Patent number: 7434115
    Abstract: An interleaver and method of interleaving operate on data represented in a sequence of symbols to produce an interleaved sequence of symbols. The interleaver performs intra-block and inter-block permutations on the sequence of symbols. An encoder and method of encoding operate on data represented in a source sequence of symbols. The source sequence of symbols is encoded into a first sequence of codewords and interleaved using intra-block and inter-block permutations to produce a sequence of interleaved symbols. The sequence of interleaved symbols is encoded into a second sequence of codewords. A decoder and method of decoding operate on data represented in a sequence of received symbols. The sequence of received symbols comprises a formatted copy of the source sequence of symbols and the first and the second sequence of codewords.
    Type: Grant
    Filed: October 8, 2004
    Date of Patent: October 7, 2008
    Assignee: Industrial Technology Research Institute
    Inventors: Yan-Xiu Zheng, Yu T. Su
  • Patent number: 7421626
    Abstract: A digital data recording/reproducing method includes the steps of: interleaving data on a PI code for each PI code of a 208-row ECC block; and converting a short burst error into random errors by dispersing errors on the PI codes. Moreover, the digital data recording/reproducing method increases correction capability against several bytes to several tens bytes of errors generated at random without changing burst error correction length by performing this processing for respective PI codes by using interleave rules that are different as much as possible from one another.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: September 2, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Taku Hoshizawa, Shigeki Taira, Osamu Kawamae
  • Patent number: 7421627
    Abstract: A digital data recording/reproducing method includes the steps of: interleaving data on a PI code for each PI code of a 208-row ECC block; and converting a short burst error into random errors by dispersing errors on the PI codes. Moreover, the digital data recording/reproducing method increases correction capability against several bytes to several tens bytes of errors generated at random without changing burst error correction length by performing this processing for respective PI codes by using interleave rules that are different as much as possible from one another.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: September 2, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Taku Hoshizawa, Shigeki Taira, Osamu Kawamae
  • Patent number: 7406654
    Abstract: A coding circuit for generating an error correction code from digital data to be recorded in a record medium, includes a buffer manager which successively reads the digital data m bytes at a time from a temporal storage memory in a main scan direction and in a sub-scan direction, a PI parity unit which processes the data m bytes at a time, as the m bytes are supplied from the buffer manager, and generates a PI sequence parity based on the data for one row extending in the main scan direction, and a PO parity unit which includes in operation units, each of which processes a corresponding byte of the data, as m bytes of the digital data are supplied from the buffer manager, and generates a PO sequence parity based on the data for one column extending in the sub-scan direction.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: July 29, 2008
    Assignee: Ricoh Company, Ltd.
    Inventor: Isamu Moriwaki
  • Patent number: 7406636
    Abstract: A digital data recording/reproducing method includes the steps of: interleaving data on a PI code for each PI code of a 208-row ECC block; and converting a short burst error into random errors by dispersing errors on the PI codes. Moreover, the digital data recording/reproducing method increases correction capability against several bytes to several tens bytes of errors generated at random without changing burst error correction length by performing this processing for respective PI codes by using interleave rules that are different as much as possible from one another.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: July 29, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Taku Hoshizawa, Shigeki Taira, Osamu Kawamae
  • Patent number: 7395482
    Abstract: A data storage system includes an encoder subsystem comprising an error correction code encoder, a modulation encoder, and a precoder, and a decoder subsystem similarly comprising a detector, an inverse precoder, a channel decoder, and an error correction code decoder. The error correction encoder applies an error correction code to the incoming user bit stream, and the modulation encoder applies so-called modulation or constrained coding to the error correction coded bit stream. The precoder applies so-called precoding to the modulation encoded bit stream. However, this precoding is applied to selected portions of the bit stream only. There can also be a permutation step where the bit sequence is permuted after the modulation encoder before precoding is applied by the precoder. The decoder subsystem operates in the inverse manner.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: July 1, 2008
    Assignee: International Business Machines Corporation
    Inventors: Roy D. Cideciyan, Ajay Dholakia, Evangelos S. Eleftheriou, Richard L. Galbraith, Weldon M. Hanson, Thomas Mittelholzer, Travis R. Oenning
  • Patent number: 7389467
    Abstract: A method of recording data includes forming a plurality of codewords by error correction coding a predetermined amount of inputted data according to a predetermined method, and recording the data including the plurality of codewords to the small-sized optical disc in a recording unit of a shorter length than a predetermined track of an inner circumference region of the small-sized optical disc.
    Type: Grant
    Filed: May 19, 2004
    Date of Patent: June 17, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-hyun Kim, Yoon-woo Lee, Sung-hee Hwang
  • Patent number: 7382829
    Abstract: This invention has as its object to implement the constitution of a receiver that receives signals sent by performing multi-valued pulse modulation and performs iterative decoding. The constitution includes: (1) a bank of pulse correlators that achieves correlation with all predetermined sent pulse waveforms, (2) a pulse demapper that calculates the log likelihood ratio for each bit of the interleaved code word from said pulse correlator outputs and a priori information for each bit, (3) a deinterleaver that performs deinterleaving on the output from said pulse demapper, (4) a decoder that calculates likelihood information for the deinterleaved code word bits and information bits, respectively, (5) an interleaver that interleaves the output of the decoder in the same manner as on the sending side, and (6) a feedback circuit that provides feedback of the output of said interleaver as a priori probability to the pulse demapper.
    Type: Grant
    Filed: September 9, 2004
    Date of Patent: June 3, 2008
    Assignee: National Institute of Information and Communications Technology Incorporated Administrative Agency
    Inventors: Kenichi Takizawa, Ryuji Kohno
  • Patent number: 7376882
    Abstract: A method for reducing fading channel signal data loss for serial data rates up to approximately 10 gigabits per second includes sequentially distributing serial data to multiple encoders. Individual data bytes are sent from the encoders to a convolutional interleaver. Each byte is distributed to an individual memory element of the interleaver in a received byte sequence. An address generator generates write and read addresses assignable to each memory element. Multiple shift registers have variably graduated lengths. The serial data is distributed between channels each having a different delay element created by shift register length differences. The delay elements are adjustable to correct data dropout due to daily atmospheric/channel changes. Fade detection signals are inserted before transmission and measured at a receiver. The fade signals help create erasure bits to improve decoding accuracy and adjust interleaver delay parameters.
    Type: Grant
    Filed: April 14, 2005
    Date of Patent: May 20, 2008
    Assignee: The Boeing Company
    Inventor: Thomas H Friddell
  • Patent number: 7370246
    Abstract: Successive sequences of interleaved data samples extracted from a virtual memory having L0 columns and C0 rows are de-interleaved. The de-interleaving includes receiving each sequence of the interleaved data samples, and writing row by row the received sequences of interleaved data samples in a de-interleaving memory array having L rows and C columns, with L being greater or equal to L0 and C being greater or equal to C0. The data samples stored in the de-interleaving memory array are de-interleaved sub-array by sub-array. Each sub-array is a square cluster array having a number SQ of rows and columns. A cluster array is a row of the square cluster array comprising SQ data samples, with the number L of rows and the number C of columns of the de-interleaving memory array being multiples of the number SQ of rows and columns.
    Type: Grant
    Filed: December 8, 2004
    Date of Patent: May 6, 2008
    Assignee: STMicroelectronics N.V.
    Inventors: Armin Wellig, Julien Zory
  • Publication number: 20080092024
    Abstract: A system for detecting one or more localized burst errors in a receiving message comprised of a plurality of codewords. The system comprises a trellis code decoder for decoding a receiving message with a plurality of codewords and calculating one or more cumulative metrics of a maximum likelihood path and one or more alternative paths from the receiving message, an error detection code (EDC) decoder for detecting existence of one or more errors in the decoded receiving message received from the trellis decoder, and a localized burst error detector activated by the EDC decoder upon detecting the existence of one or more errors in the decoded receiving message to identify at least one corrupted codeword among the plurality of codewords using the one or more cumulative metrics of a maximum likelihood path and the one or more alternative paths, wherein the system requests the re-transmission of the corrupted codeword.
    Type: Application
    Filed: May 2, 2007
    Publication date: April 17, 2008
    Inventors: Hanqing Lou, Ahmadreza Hedayat, Hang Jin
  • Patent number: 7346827
    Abstract: A method of providing forward error correction for data services uses a parallel concatenated convolutional code which is a Turbo Code comprising a plurality of eight-state constituent encoders wherein a plurality of data block sizes are used in conjunction with said Turbo Code. A variation uses the method in a cellular radio system. Another variation uses the method in both forward and reverse likes of a cellular radio system.
    Type: Grant
    Filed: January 5, 2005
    Date of Patent: March 18, 2008
    Assignee: The DIRECTV Group, Inc.
    Inventors: Mustafa Eroz, A. Roger Hammons, Jr.
  • Patent number: 7340664
    Abstract: A method and apparatus for decoding and de-interleaving a received encoded and interleaved signal, the method employing and the apparatus including a single decoder coupled to a common buffer, the common buffer size equal to a frame of the received signal and the method further employing, and the apparatus further including, an address controller that causes data to be de-interleaved when read from the buffer and data to be interleaved when written to the buffer.
    Type: Grant
    Filed: December 5, 2003
    Date of Patent: March 4, 2008
    Assignee: LSI Logic Corporation
    Inventor: Qiang Shen
  • Patent number: 7336735
    Abstract: Viterbi decoder for decoding a received sequence of data symbols which are coded using a predetermined coding instruction is provided. The Viterbi decoder includes a branch metric calculation circuit for calculation of branch metrics for the received sequence of coded data symbols. The Viterbi decoder includes a path metric calculation circuit for calculation of path metrics as a function of the branch metrics and the coding instruction, with the calculated path metrics in each case being compared with an adjustable decision threshold value in order to produce an associated logic validity value. The Viterbi decoder also includes a selection circuit which temporarily stores those path metrics whose validity value is logic high in a memory, and selects from the temporarily stored path metrics that path with the optimum path metric.
    Type: Grant
    Filed: July 8, 2003
    Date of Patent: February 26, 2008
    Assignee: Infineon Technologies AG
    Inventor: Mario Traeber
  • Patent number: 7305606
    Abstract: A digital data recording/reproducing method includes the steps of: interleaving data on a PI code for each PI code of a 208-row ECC block; and converting a short burst error into random errors by dispersing errors on the PI codes. Moreover, the digital data recording/reproducing method increases correction capability against several bytes to several tens bytes of errors generated at random without changing burst error correction length by performing this processing for respective PI codes by using interleave rules that are different as much as possible from one another.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: December 4, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Taku Hoshizawa, Shigeki Taira, Osamu Kawamae
  • Patent number: 7296209
    Abstract: A communication device which executes proper communications by correcting communication errors caused by noise generated on a transmission line or the like. An encoding device for adding error correction code to an input data sequence is provided with a first code encoding unit for adding binary error correction code to first data blocks into which the input data sequence is divided, and a second code encoding unit for adding a symbol error correction code for correcting errors by a symbol unit of a predetermined length to second data blocks into which the input data sequence is divided in a form different from that of the plurality of first data blocks.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: November 13, 2007
    Assignee: International Business Machines Corporation
    Inventors: Yasunao Katayama, Toshiyuki Yamane
  • Patent number: 7277498
    Abstract: In the code word mapping operation of a radio communication system, mapping patterns are provided for different S/N ratios, the code word bits produced from a coder are not equally assigned to multi-level modulation bits, but weighted according to the resistance of multi-level modulation bits to error before being assigned, and the mapping patterns are switched in accordance with S/N. Since the code word mapping method is updated so that the error rate can be always minimized according to the situations of a propagation path and S/N ratio, communication can be made with high communication quality.
    Type: Grant
    Filed: July 29, 2002
    Date of Patent: October 2, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Seishi Hanaoka, Takashi Yano
  • Patent number: 7278089
    Abstract: A receiver is to receive an encoded data block that was encoded using a convolutional encoder and includes source bits and error detection bits. The receiver may include a Viterbi decoder, a de-mapper and an error detection unit. The error detection unit is to determine whether an error correction capability of the Viterbi decoder is sufficient to recover the source bits from the encoded data block. The Viterbi decoder is to decode the encoded data block only if the encoded data block is not free of errors and if the error correction capability of the Viterbi decoder is sufficient to recover the source bits from the encoded data block.
    Type: Grant
    Filed: October 28, 2004
    Date of Patent: October 2, 2007
    Assignee: Intel Corporation
    Inventors: Sharon Levy, Dov Kimberg
  • Patent number: 7260768
    Abstract: A communication device is provided with a turbo encoder (1) which carries out a turbo encoding process on the lower two bits of transmission data so as to output information bits of two bits and redundant bits of two bits, a conversion (2) which carries out calculations so as to uniform error-correction capabilities on respective information bits by using the output, decoders (11 to 18) which carries out a soft-judgment on the lower two bits of the received signal that are susceptible to degradation in the characteristics so as to estimate the original transmission data, and a second judging device (19) which carries out a hard-judgment on the other bits in the received signal so as to estimate the original transmission data.
    Type: Grant
    Filed: October 20, 2000
    Date of Patent: August 21, 2007
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Wataru Matsumoto, Yoshikuni Miyata
  • Patent number: 7240276
    Abstract: A read channel carrying out turbo coding/iterative decoding is disclosed in a disk drive. The read channel has an iterative decoder including an APP decoder which changes a likelihood equation according to a detection result of a burst noise detection unit so as to correct a burst error and executes APP decoding calculation of an inner code.
    Type: Grant
    Filed: October 1, 2003
    Date of Patent: July 3, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Manabu Akamatsu
  • Patent number: 7228483
    Abstract: To shorten a time required for a decoding process of a turbo codes without an increase in an operating frequency of the decoder by making concurrent operations of two soft-output decoders possible, the present invention provides soft-output decoders (101, 102) for outputting a reliability information likelihood, interleavers (103, 105) for interleaving transmission information to supply to the soft-output decoder, interleaver (104, 106) for interleaving a reliability information likelihood to supply to the soft-output decoder, and deinterleavers (107, 108) for deinterleaving the reliability information likelihood to supply to the soft-output decoder. Since these elements are constructed as two circuits having the same configuration and two soft-output decoders are operated concurrently in an iterative decoding process for a second time et seq. in the iterative decoding process of the turbo codes, a processing time required for the decoding process for the second time et seq. can be reduced by half.
    Type: Grant
    Filed: June 8, 2004
    Date of Patent: June 5, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Yuji Kuwahara
  • Patent number: 7212579
    Abstract: A radio telecommunications receiver operates to receive digital data symbols or bits by iterative determination of soft estimates of symbols or bits followed by a hard decision as to what symbol or bit was intended. The receiver comprises a first processor operative to provide first soft estimates of symbols or bits of the received signal and a second processor operative to decode the first soft estimates and to provide second soft estimates of the symbols or bits. The receiver also comprises a combiner operative to provide third soft estimates back to the first processor for subsequent further decoding, the third soft estimates of each symbol or bit being dependent upon the respective second soft estimate and a respective previous second soft estimate.
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: May 1, 2007
    Assignee: Lucent Technologies Inc.
    Inventors: Holger Claussen, Hamid Reza Karimi
  • Patent number: 7200797
    Abstract: A method of optimizing the size of blocks of coded data intended to be subjected to an iterative decoding process, a maximum error rate of the iterative decoding process being fixed in advance, in which there are sought, among a plurality of block sizes (N/k) which are submultiples of the normal block size by an integer factor (k) greater than or equal to 1 and a plurality of integers giving the maximum number of iterations that can be effected by the said iterative decoding on a block, (1) a submultiple size, and (2) a maximum number of iterations such that they are compatible with the maximum error rate, and such that the mean number of iterations that will be applied by the iterative decoding process on a block of submultiple size is minimized.
    Type: Grant
    Filed: March 6, 2002
    Date of Patent: April 3, 2007
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Arnaud Gueguen
  • Patent number: 7200796
    Abstract: A QCTC (Quasi-Complementary Turbo Code) generating apparatus having a turbo encoder for generating an information symbol sequence and a plurality of parity symbol sequences by encoding the information symbol sequence; a channel interleaver for individually interleaving the symbol sequences, generating new parity symbol sequences by multiplexing the symbols of parity symbol sequences with the same priority levels, and serially concatenating the information symbol sequence and the new parity symbol sequences; and a QCTC generator for generating a sub-code with a given code rate by recursively selecting a predetermined number of symbols from the concatenated symbol sequence at a given starting position.
    Type: Grant
    Filed: October 7, 2003
    Date of Patent: April 3, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-Goo Kim, Jae-Sung Jang
  • Patent number: 7174497
    Abstract: The invention relates to a method of storing a number of data bits of a secondary channel (30) in the frame of a main channel (20) and to a method of decoding a stream of bits relating to a secondary channel (30) embedded in the frames of a main channel (20) into a stream of data bits (62). In order to enable a certain synchronization and to guarantee a fixed amount of storage capacity in the secondary channel as well as to be able to correct deletions or insertions of bits in the secondary channel it is proposed according to the invention to form a secondary frame (11) having a fixed number of frame bits, to fill a fixed part of the secondary frame (11) with data bits (113), an end-bit (114) set to a first bit-value and, if necessary, with filling bits (115) set to a second bit-value, to encode the secondary frame (11) producing encoded data bits (113) and parity bits (112), which are finally embedded in the frame of the main channel (20).
    Type: Grant
    Filed: August 21, 2001
    Date of Patent: February 6, 2007
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Constant Paul Marie Jozef Baggen, Marten Erik Van Dijk, Willem Marie Julia Marcel Coene
  • Patent number: 7168033
    Abstract: A decoder for decoding data from a communication channel includes a parity check matrix including M tiers, wherein M?B, Dmin=B*M for M=1 . . . E or B*M?Dmin?F for M>E. Dmin is the minimum Hamming distance and tc=M, wherein tc is a column weight. The parity check matrix includes no period-four cycles. B, Dmin, E, F and M are integers. A soft channel decoder is configured to decode data. A soft linear block code decoder is configured to decode data decoded by the soft channel decoder in accordance with the parity check matrix.
    Type: Grant
    Filed: November 18, 2005
    Date of Patent: January 23, 2007
    Assignee: Marvell International Ltd.
    Inventors: Zining Wu, Gregory Burd
  • Patent number: 7134068
    Abstract: An apparatus and a method of aligning data bits serially received at a channel input. A number of data bits including a first data bit are stored in a buffer that has a first buffer bit and a buffer size greater than the number of data bits. The data bits in the buffer are shifted to improve alignment of the first data bit and the first buffer bit. The shifted data bits are tested for alignment. If the testing of the data bits indicates correct alignment, then the aligned data bits are transmitted from the buffer to a host for use. If the testing of the data bits indicates misalignment, then the data bits are passed to an error handling process.
    Type: Grant
    Filed: December 4, 2003
    Date of Patent: November 7, 2006
    Assignee: Seagate Technology LLC
    Inventors: Gregory L. Silvus, Ewe Chye Tan
  • Patent number: 7123672
    Abstract: A processor (604) determines (502) a channel metric from a data signal received on a diversity branch. The processor calculates (504) an index into a final metrics buffer (702), the index determined from a position of the channel metric within an interleaved frame of data. The processor places (506) a value derived from the channel metric into the final metrics buffer at a location defined by the index. A corresponding method and apparatus as well as communications receiver utilizing the processor (604) are described.
    Type: Grant
    Filed: April 30, 2003
    Date of Patent: October 17, 2006
    Assignee: Motorola, Inc.
    Inventors: Bradley J. Rainbolt, Stephen R. Carsello
  • Patent number: 7107505
    Abstract: Architecture for enhancing the encoding/decoding of information of a channel. A stream of incoming information bits are arranged into a first array of information bits. The first array of information bits are processed into a first code of bits, which bits form a plurality of first code words having a minimum distance to neighboring error events. Selected bits of the first code are rearranged into a second array of bits by intermittent successive rotations of the selected bits of the first code. A second code is then generated from the second array of bits to increase the minimum distance to the neighboring error events.
    Type: Grant
    Filed: March 27, 2002
    Date of Patent: September 12, 2006
    Assignee: Comtech AHA Corporation
    Inventor: William H. Thesling, III
  • Patent number: 7096402
    Abstract: Detection of errors in the results of turbo decoding is performed while decoding is being repeated. If absence of errors is detected, the results of decoding are output, even though repetition of the decoding operation is in progress, and further decoding is discontinued. Further, the number of times errors are detected in decoded results when decoding has been performed a set number of times is monitored and the decoding operation is executed again if the number of times errors are detected is equal to or less than a set value. Further, one of first and second decoded results output from first and second elementary decoders that construct a turbo decoder is selected as appropriate and is then output.
    Type: Grant
    Filed: July 9, 2001
    Date of Patent: August 22, 2006
    Assignee: Fujitsu Limited
    Inventors: Tetsuya Yano, Kazuhisa Obuchi, Kazuo Kawabata
  • Patent number: 7085969
    Abstract: An interleaver and method of interleaving operate on data represented in a sequence of symbols to produce an interleaved sequence of symbols. The interleaver performs intra-block and inter-block permutations on the sequence of symbols. An encoder and method of encoding operate on data represented in a source sequence of symbols. The source sequence of symbols is encoded into a first sequence of codewords and interleaved using intra-block and inter-block permutations to produce a sequence of interleaved symbols. The sequence of interleaved symbols is encoded into a second sequence of codewords. A decoder and method of decoding operate on data represented in a sequence of received symbols. The sequence of received symbols comprises a formatted copy of the source sequence of symbols and the first and the second sequence of codewords.
    Type: Grant
    Filed: February 6, 2002
    Date of Patent: August 1, 2006
    Assignee: Industrial Technology Research Institute
    Inventors: Yan-Xiu Zheng, Yu T. Su
  • Patent number: 7080311
    Abstract: A method of transmitting convolutionally encoded data with separate, independent and looped encoding over at least one data portion. The data is distributed over one or more cycles, and a plurality of cycles can be grouped into packets for discontinuous transmission if necessary. Weighted decoding is effected independently and cycle by cycle: it starts at a robust location, with a relatively high likelihood, and terminates at a weak location, with a weak likelihood, ignoring the concept of time. This limits the size of the packets of errors and prevents the propagation of packets of errors due to scrambling. Independent encoding and decoding of data can be effected without exchanging parameters between cycles and the parameters of each cycle (size, redundancy, constraint length) can be separate. Different degrees of protection and time-delay are permitted as a function of the nature of the data to be transmitted (voice, digital data, signaling, etc.).
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: July 18, 2006
    Assignee: Alcatel
    Inventors: Thibault Gallet, André Marguinaud, Brigitte Romann
  • Patent number: 7069492
    Abstract: To interleave a binary sequence a represented by the polynomial a ? ( x ) = ? i = 0 n - 1 ? a i ? x i , where n=R.M with R?M, i being an integer which may be written i=r.M+c, r and c being integers, r?0 and c ? [0, M?1], there is obtained, from the sequence a, an interleaved binary sequence a*. The interleaved binary data sequence a* represented by the polynomial a * ? ( x ) = ? i = 0 n - 1 ? a i ? x i * where i*=[r?h(c)].M+c mod n, the h(c) being obtained by the choice of an M-tuple h0=[h0(0), . . . , h0(M?1)] of non-negative integers less than R?1 such that, given a predetermined set ? of circulating matrices P of dimension M×M, for any matrix P of ?, the residues modulo R of the components of the vector h0.P are not nil; and the corresponding choice of an M-tuple h obtained from h0 by the application of a permutation moving h0(c) to position L×c mod M, the integer L being relatively prime with M.
    Type: Grant
    Filed: March 13, 2003
    Date of Patent: June 27, 2006
    Assignee: Canon Kabushiki Kaisha
    Inventor: Philippe Piret
  • Patent number: 7055082
    Abstract: Errors in a first data signal of a first error correction code system in a reproduced signal are corrected to get first correction-resultant data. Errors in a second data signal of a second error correction code system in the reproduced signal are corrected to get second correction-resultant data. All address information pieces in the second correction-resultant data for every error correction block are subjected to error checks. When at least one of all the address information pieces is correct, a descramble initial value is set in response to the correct address information piece. When all the address information pieces are erroneous, a correct address information piece is estimated from an address information piece associated with a previous error correction block and the descramble initial value is set in response to the estimated correct address information piece. The first correction-resultant data are descrambled in response to the descramble initial value.
    Type: Grant
    Filed: October 14, 2003
    Date of Patent: May 30, 2006
    Assignee: Victor Company of Japan, Ltd.
    Inventors: Takaro Mori, Kazumi Iwata
  • Patent number: 7055088
    Abstract: Several embodiments of an interleaved generalized convolutional encoder system and method are provided for communicating data over a transmission path in order to inhibit distortion caused by impulse noise or other correlated noise and enhance transmission rate of data communications. The encoder system is designed to introduce a variable delay to the convolutional encoder. The variable delay effectively spreads correlated noise over a variable number of symbols in time. Correlated noise that is spread over time allows for better error correction encoding.
    Type: Grant
    Filed: February 5, 2001
    Date of Patent: May 30, 2006
    Assignee: Paradyne Corporation
    Inventor: William L. Betts
  • Patent number: 7035338
    Abstract: A method and an apparatus for multitone modulation to transmit at least two packets of data, each comprising a plurality of symbols, to provide inter-packet interleaving. The method utilizes a plurality of tones of different frequencies to transmit the data symbols of the two packets. Transmission of successive data symbols of a first data packet and of a second data packet are delayed over time, such that during at least one symbol period the tones are transmitting at least one first packet data symbol and at least one second packet data symbol. A further embodiment comprises a method for multitone modulation to transmit at least two packets of data which utilizes a plurality of modulation codes to transmit the data symbols of the two packets. The modulation codes comprise a set of orthogonal modulation codes, or the data can be modulated in accordance with CDMA modulation.
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: April 25, 2006
    Assignee: Tioga Technologies Ltd.
    Inventor: Daniel Stopler
  • Patent number: 7032138
    Abstract: A memory-efficient convolutional interleaver/de-interleaver with a memory array, a write commutator, and a read commutator wherein the commutators perform their respective write and read operations relative to a preselected memory cell after a predetermined delay. The delay is chosen using a modulo-based technique, such that an efficient implementation of a Ramsey Type-II interleaver is realized.
    Type: Grant
    Filed: November 21, 2003
    Date of Patent: April 18, 2006
    Assignee: Broadcom Corporation
    Inventor: Kelly Brian Cameron
  • Patent number: 7032154
    Abstract: A method and apparatus for performing error correction is described. A stream of data is encoded using concatenated error correcting codes. The encoded data is communicated over a transmission system. The encoded data is decoded using the codes and three levels of decoding.
    Type: Grant
    Filed: March 25, 2002
    Date of Patent: April 18, 2006
    Assignee: Tyco Telecommunications (US) Inc.
    Inventors: Howard D. Kidorf, Franklin W. Kerfoot, III, Nandakumar Ramanujam, Bo Pedersen