Abstract: A storage system comprises a linear block encoder. A write circuit writes an output of the linear block encoder to a storage medium. A read circuit reads data from the storage medium. A channel decoder decodes the data. A soft linear block code decoder that decodes the data decoded by the channel decoder. The channel decoder decodes the data read in a first iteration. In a subsequent iteration the channel decoder decodes the data read by the read circuit and utilizes information decoded by the soft linear block code decoder. A threshold check circuit selects an output of the soft linear block code decoder if a number of parity check violations has a first relationship with respect to a threshold, or an output of the channel decoder if the number of parity check violations has a second relationship with respect to the threshold.

Abstract: A radio communication apparatus is provided in Protocol Data Unit (PDU) transmission, in which the tail end (boundary) of a packet is detected based on the calculation result of an error detection calculation (Frame Check Sequence (FCS) calculation), without use of Length Indicator (LI) information. Preferably, to avoid incorrect detection, tail end presence/non-presence flag information is set in a header, and the above detection is decided to be valid when the flag information in the header part of PDU, storing the detected tail end, indicates the presence of the tail end.

Abstract: A method for reducing fading channel signal data loss for serial data rates up to approximately 10 gigabits per second includes sequentially distributing serial data to multiple encoders. Individual data bytes are sent from the encoders to a convolutional interleaver. Each byte is distributed to an individual memory element of the interleaver in a received byte sequence. An address generator generates write and read addresses assignable to each memory element. Multiple shift registers have variably graduated lengths. The serial data is distributed between channels each having a different delay element created by shift register length differences. The delay elements are adjustable to correct data dropout due to daily atmospheric/channel changes. Fade detection signals are inserted before transmission and measured at a receiver. The fade signals help create erasure bits to improve decoding accuracy and adjust interleaver delay parameters.

Abstract: Devices, methods, and systems of a communications channel detector are disclosed that can compare a plurality of candidate sequences of bits and decisions to identify unlikely error events. The detector may then discard at least one candidate sequence based on an unlikely error event to produce a set of remaining paths. A branch metric calculator may be adapted to calculate metrics for a set of remaining paths.

Abstract: Various approaches to recover data are described. An one example, an encoded data stream is processed in a first channel decoder producing a channel decoder output. The channel decoder output and the encoded data stream are processed in an error compensation unit to compensate the channel decoder output for low frequency noise and produce an error compensated data stream. The error compensated data stream is processed in a second channel decoder to produce a recovered data stream, wherein the recovered data stream has a reduction in the number of errors as compared to the encoded data stream. Systems to iteratively recover data from an encoded data stream are also described.

Abstract: A system and method of media defect compensation incorporate an architecture capable of modifying a signal representative of data reproduced from a recording medium to compensate for defects in the medium. In accordance with one aspect of the invention, a media defect compensator may incorporate one or two data detectors cooperating with a defect detector to compensate for signal loss due to media defects.

Abstract: Various embodiments of the present invention provide systems and methods for media defect detection. For example, a data receiving system is disclosed that includes a data signal provided from a medium that may include a defective portion. An absolute value circuit receives the data signal and provides an output corresponding to an absolute value of the data signal. The output corresponding to the absolute value of the data signal is input to a filter that filters it and provides a filtered output. In some cases, the filter is a digital filter operable to integrate the absolute value of the data signal. A comparator receives the output from the filter and compares it with a threshold value. The result of the comparison indicates a defect status of the medium.

Abstract: Various embodiments relate to a multi-standard Viterbi decoder. Based on programmable values for constraint length, generator polynomials, and code rate, the multi-standard Viterbi decoder may adhere to a specific convolutional code standard. At a given time, the multi-standard Viterbi decoder may receive a variety of convolutional codes through a channel and may process them using various forms of the trace back method. Various embodiments include a branch metric unit and path metric unit that include a variety of sub-units that may or may not be active based on the value of the programmable value. Various embodiments also enable the multi-standard Viterbi decoder to handle different forms of convolutional codes, such as tail-biting codes. In some embodiments, the multi-standard Viterbi decoder may also process at least two convolutional codes concurrently.

Abstract: A low complexity List Viterbi algorithm (LVA) for decoding tail biting convolutional codes (TBCCs) has lower complexity than a solution of running the LVA algorithm for all states. In one aspect, a low complexity LVA-TBCC process includes finding a list of states from a single Viterbi algorithm and finding a list of potential codewords for each state in the state list using the LVA. A cyclic redundancy check may prune out false solutions. The disclosed method may be applied to many communication systems to improve error performance similar to LTE downlink PBCH decoding enhancements.

Abstract: According to one aspect of the present invention, an apparatus is provided to enable weather band radio signals to be received and processed using a digital signal processor (DSP). The DSP can include functionality to implement both frequency modulation (FM) demodulation and weather band data demodulation, i.e., specific area encoding (SAME) demodulation. In one such embodiment, soft decision samples of a SAME message can be combined, and based on a combined result, a hard decision unit can generate a bit value of weather band data.

Abstract: Techniques for sending signaling information using hierarchical coding are described. With hierarchical coding, individual messages for users are encoded using multiple interconnected encoders such that (1) the message for each user is sent at a data rate suitable for that user and (2) a single multicast message is generated for the messages for all users. A base station determines data rates supported by the users and the code rates to achieve these data rates. Each data rate is determined by one or more code rates. Signaling information for the users is mapped to data blocks to be sent at different data rates. Each data block is then encoded in accordance with the code rate(s) associated with the data rate for that data block. A final coded block is generated for all users and transmitted. Each user performs the complementary decoding to recover the message sent to that user.

Abstract: Methods and corresponding systems in a Viterbi decoder include selecting an input symbol in an input block, wherein the input block has a plurality of input symbols, wherein each input symbol has a Boolean value, a quality value, and an associated stage, and wherein the selected symbol is selected based upon the quality value of the selected symbol relative to a quality value of other input symbols in the input block. Thereafter, the Boolean value of the selected symbol is complemented to produce a complemented symbol. The complemented symbol is substituted for the selected symbol to produce an alternate input block. A Viterbi algorithm is executed using the alternate input block to produce an alternate decoded bit sequence, which is then checked for errors using an error check. The alternate decoded bit sequence is output in response to the alternate decoded bit sequence passing the error check.

Abstract: A communication apparatus includes a plurality of descramblers for subjecting a second header portion of a received frame to descrambling processing using pseudo-random sequences that differ from one another; a plurality of syndrome arithmetic units for performing a syndrome calculation, which is in accordance with a cyclic redundancy check code, with respect to headers descrambled by respective ones of the plurality of descramblers, and an error correction unit for selecting a header that has been descrambled by one descrambler among the plurality of descramblers as a receive header, in accordance with syndrome values calculated by respective ones of the plurality of syndrome arithmetic units.

Abstract: Embodiments of a system and method for signal processing in a wireless communication device are generally described herein. Other embodiments may be described and claimed. In some embodiments, the wireless communication device comprises a first reconfigurable processing engine for configuration by a processing unit to perform a plurality of baseband processing operations on baseband samples. The processing unit may reconfigure the first reconfigurable processing engine for performing each of the plurality of baseband processing operations after completion of a prior one of the baseband processing operations. A second reconfigurable processing engine for configuration by the processing unit may perform decoding operations on output data generated by the first reconfigurable processing engine.

Abstract: In a hard-disc drive, a defect region on the hard disc is detected by generating two statistical measures (e.g., ?1(k) and ?2(k)) based on signal values (e.g., x[n] or y[n]) and soft-decision values (e.g., L[n]) corresponding to the signal values. The measures are compared to detect the location of the defect region of the hard drive. Using the soft-decision values reduces fluctuations in a ratio of the statistical measures compared to a ratio formed from statistical measures that are not based on soft-decision values, resulting in a more-reliable test for detecting defect regions.

Abstract: Serial concatenated trellis coded modulation (SCTCM) includes an outer coder, an interleaver, a recursive inner coder and a mapping element. The outer coder receives data to be coded and produces outer coded data. The interleaver permutes the outer coded data to produce interleaved data. The recursive inner coder codes the interleaved data to produce inner coded data. The mapping element maps the inner coded data to a symbol. The recursive inner coder has a structure which facilitates iterative decoding of the symbols at a decoder system. The recursive inner coder and the mapping element are selected to maximize the effective free Euclidean distance of a trellis coded modulator formed from the recursive inner coder and the mapping element. The decoder system includes a demodulation unit, an inner SISO (soft-input soft-output) decoder, a deinterleaver, an outer SISO decoder, and an interleaver.

Abstract: A high-speed maximum likelihood sequence estimation method and device. The method includes identifying candidate paths through a state trellis based on a group of observed data, where each candidate path corresponds to a best path through a trellis beginning at one of a possible prior states (and corresponding prior data bit or bits), and then selecting one of the paths based on candidate sequence selection information, typically prior state decisions (e.g., data symbols in the form of one or more bits). The path selection, in turn, provides decoding of symbols and data bit information for use in selecting one of the candidate paths in a subsequent stage.

Abstract: A Viterbi decoder includes a decision generator configured to generate a full decision output. An error detector is configured to detect errors in the full decision output and generate a signal when the full decision output errors are detected.

Abstract: A method of estimating signal-to-noise ratio in a Viterbi decoder comprising: setting a threshold SNR value; determining a dependence on SNR of the average decoding path length; filling branch metrics matrix, minimal path metrics matrix, path metrics matrix and paths matrix with initial values; receiving packets from a communication channel; calculating the matrices that contains paths stored during operation of Viterbi algorithm in its rows, and a minimal path metrics matrix, including calculating an estimate of a decoding path length, where all the paths converge, based on the paths matrix; calculating current SNR estimate using an estimate of a decoding path length, based on results of previous steps; setting a decoder control signal to an active state if the current estimated SNR does not exceed the threshold, and to an inactive state otherwise; if the decoder control signal is in active state, the branch metrics matrix, the minimal path metrics matrix, the paths metrics matrix and the paths matrix are fi

Abstract: A wireless receiver detects signals generated with a multiple-input, multiple-output (MIMO) transmitter. The receiver applies maximum-likelihood detection (MLD) for soft-output signal detection, where an MLD exhaustive search across all candidate vectors is performed recursively by computing and accumulating the differences between, for example, the Euclidean metrics of consecutive candidate tests. Difference terms used for the accumulation are also calculated recursively. An ordering of candidates, such as by a triangular-waveform shaped ordering, is employed such that only one candidate variable is changed between any two consecutive candidate evaluations, leading to a reduced set of computations.

Abstract: A first convolutional coder (building-block trellis coder) is used to establish a minimum squared Euclidian distance (MSED) between signal points within a coded constellation building block. A second convolutional encoder (tiling encoder) is designed to ensure that the building block's MSED is maintained between building blocks once they are tiled onto an integer lattice. When this approach is applied to the trellis code of the WiMAX standard, a 3 dB coding is realized. Recall that Wei's 16-state 4D code suffered from a 1.36 dB due to constellation expansion, resulting in a net 4.66 dB coding gain. Our building block approach recovers 1.33 dB of this loss with only a minor increase in coding complexity. We then use the building block approach to derive simpler and more powerful higher dimensional codes that provide further gains still over the Wei family of multidimensional codes.

Abstract: Techniques are provided to compute the carrier to interference-plus-noise ratio (CINR) in a wireless communication system using log-likelihood ratio (LLR) data generated from a received transmission. The LLR data are collected as they are sent from a detector to a forward error correction (FEC) decoder in a wireless communications device. In one embodiment, decision-aided LLR based CINR is computed using the decoded bits output from the FEC decoder as feedback. In another embodiment, blind LLR based CINR is computed without feedback. The CINR may be used to adjust a modulation and/or coding parameters associated with wireless communication between wireless communication devices.

Abstract: Methods and apparatus are provided for reduced complexity Soft-Output Viterbi detection. A Soft-Output Viterbi algorithm processes a signal by determining branch metrics using a branch metrics unit; determining survivor paths for sequence detection using a first add-compare select unit; and determining survivor paths for generating one or more bit reliability values using a second add-compare select unit, wherein the first and second add-compare select units process the branch metrics determined by the branch metrics unit. The first and second add-compare select units can optionally process branch metrics having a different number of bits.

Abstract: A signal detector comprises a first detector that generates raw decisions as a function of a read back signal. A selector generates a modified decision by at least one of applying a correction technique to soft information that is based on the raw decisions and marking an erasure in the soft information. A decoder decodes the modified decision to generate a final decision and determines whether a correct codeword is generated by evaluating the final decision. The decoder performs at least one of Reed-Solomon decoding, Bose Chaudhuri Hocquerghen (BCH) decoding, Hamming decoding, and Trellis decoding.

Abstract: Sliding block traceback decoding of block codes. Block by block basis decoding is performed in which a single block, and its corresponding overlap portion, are processed during a given time. The traceback saves a record of decision (e.g., among possible trellis branches between various trellis stages) and constructs only the surviving paths through each individual block. Since only one block (by also employing its corresponding overlap portion) is decoded per time, the traceback through the coded block signal is short. One block of the coded block signal is decoded at a time, and certain resulting information (e.g., bit estimates and/or states) of a first decoded block can be leveraged when decoding a second/adjacent block.

Abstract: Systems and methods are disclosed for detecting temporary high level impairments, such as noise or interference, for example, in a communications channel, and subsequently, mitigating the deleterious effects of the dynamic impairments. In one embodiment, the method not only performs dynamic characterization of channel fidelity against impairments, but also uses this dynamic characterization of the channel fidelity to adapt the receiver processing and to affect an improvement in the performance of the receiver. For example, in this embodiment, the method increases the accuracy of the estimation of the transmitted information, or similarly, increases the probability of making the correct estimates of the transmitted information, even in the presence of temporary severe levels of impairment. The channel fidelity history may also be stored and catalogued for use in, for example, future optimization of the transmit waveform.

Abstract: A system and method for channel equalization using a Viterbi algorithm. Information from an output of a matched filter and channel parameters from a channel estimation circuit are correlated and passed on to a reconfigurable data path. The reconfigurable data path includes a reconfigurable branch metric calculation block. The reconfigurable data path also includes a reconfigurable add-compare-select and path metric calculation block. The reconfigurable data path is controlled using a programmable finite state machine. The programmable finite state machine executes a plurality of context-related instructions associated with the Viterbi algorithm. The system and method for channel equalization supports multiple standards using Viterbi algorithms.

Abstract: Subject matter disclosed herein relates to semiconductor memories and, more particularly, to multilevel non-volatile or volatile memories.

Abstract: A modified classical Viterbi decoder which can take extrinsic information and output hard decisions. A modified Viterbi decoder is provided comprising a branch metric unit, the unit having a calculator; and a processor adapted to compute a revised branch metric by combining the initial branch metric and an additional weight parameter. The modified classical Viterbi decoder computes a branch metric by summing an initial branch metric and the additional weight parameter.

Abstract: A Viterbi decoder includes a survival memory unit, for storing a plurality of survivor metric into a writing column of a writing bank of a plurality of banks in alternating intervals of a clock according to a writing bank order and a writing column order, and a trace back unit, for reading a reading column of each bank not performing storing operations according to a reading bank order and a reading column order in every interval of the clock.

Abstract: The present invention relates to a decoder for tail-biting convolution codes and a method thereof. The decoder receives an encoding bit sequence in a convolutional encoding method from a channel, generates an expanded encoding bit sequence, Viterbi decodes the expanded encoding bit sequence, and generates decoded data. In addition, the decoder selects a central bit sequence of the decoded data, rearranges the central bit sequence, and generates final decoded data. Accordingly, the decoder has a simplified configuration for decoding the bit sequence encoded in the tail biting convolutional encoding method, and the decoder also decodes a bit sequence encoded in a zero-tail convolutional encoding method.

Abstract: According to one embodiment, a data reproducing apparatus includes a reader, Viterbi decoder, metric difference calculator, an error correction decoder, and a detector. The reader reads data. The Viterbi decoder decodes the data read by the reader. The metric difference calculator calculates a metric difference between a maximum likelihood path and a competitive path, based on an output from the Viterbi decoder. The error correction decoder executes an error correction decoding for the output of the Viterbi decoder. The detector detects that an error detected by the error correction decoder is uncorrectable, and the metric difference detected by the metric difference calculator is larger than a predetermined value.

Abstract: Apparatus and methods store error recovery data in different dimensions of a memory array. For example, in one dimension, block error correction codes (ECC) are used, and in another dimension, supplemental error correction codes, such as convolutional codes, are used. By using separate dimensions, the likelihood that a defect affects both error recovery techniques is lessened, thereby increasing the probability that error recovery can be performed successfully. In one example, block error correction codes are used for data stored along rows, and this data is stored in one level of multiple-level cells of the array. Supplemental error correction codes are used for data stored along columns, such as along the cells of a string, and the supplemental error correction codes are stored in a different level than the error correction codes.

Abstract: Apparatus and methods are disclosed for decoding data stored on a data storage medium. A disclosed decoding method and decoder include a radial incoherence (RI) detector that increases the probability of detecting RI and improves the decoding performance in terms of the bit error rate of the decoded signal. RI is detected by comparing an input signal to the decoder against a RI threshold value and generating a RI-type signal. The RI detector may include a filter for filtering out noise and error in the RI-type signal, an adaptive threshold unit that adjusts the RI threshold value based upon the RI-type signal, a transition-based threshold unit that adjusts the RI threshold value based upon each transition in the input signal, or a path-based threshold unit that adjusts the RI threshold value based upon a best surviving path corresponding to the input signal, in combination or alone.

Abstract: In a communication system, a transmitter receives an input bit, and in response thereto, generates at least an n-bit codeword, each bit of which is generated by a respective one of n generators of which m are exactly the same, m being greater than n/2. A receiver comprises: m detectors, each adapted to receive the bit generated by a respective one of the m generators, and provide a respective one of m partial detection signals if a strength of the received bit exceeds a predetermined minimum threshold; and a majority logic element adapted to receive each of the m partial detection signals, and provide an output bit indicative of the input bit only if more than m/2 of the received m partial detection signals exceeds the minimum threshold.

Abstract: According to one embodiment, a signal processing device comprises a first waveform equalizer, a second waveform equalizer, a first Viterbi decoder, a second Viterbi decoder. The first and the second waveform equalizers equalize a waveform of the input signal according to first and second partial response characteristics and output first and second partial response signals. The first and second Viterbi decoders decode the first and the second partial response signals by means of Viterbi decoding process. The input signal is reproduced based on an output of the first Viterbi decoder and an output of the second Viterbi decoder.

Abstract: A Viterbi decoder includes an early decision generator that generates an early decision output. An error detector detects errors in the early decision output and generates a signal when the early decision output errors are detected.

Abstract: A method of double detection in a perpendicular magnetic read channel is disclosed. The method generally includes the steps of (A) generating an intermediate signal by performing a first detection on an input signal of the perpendicular read channel, the first detection having a first error rate, (B) generating a statistics signal based on the intermediate signal, the statistics signal conveying noise statistics that depend on data in the input signal and (C) generating an output signal by performing a second detection on the input signal using the noise statistics to reduce a second error rate of the second detection compared with the first error rate, wherein the first detection is independent of the second detection.

Abstract: A novel method to divide the whole decoding process of the Viterbi decoder into four pipeline stages and the Viterbi decoder therefore. With an appropriate choice on the system clock, the invention trade-off the decoding speed with the hardware cost so that the designed Viterbi decoder is able to satisfy the decoding speed requirement for the highest speed profile in VDSL2 systems, 30 MHz profile. At the same time, with four-stage pipeline to just enough to meet the speed requirement, the hardware cost for the new designed Viterbi decoder is reduced compared with single-staged decoding.

Abstract: Systems and methods for processing and decoding TCM/BCM-coded signal vectors. A multi-dimensional signal vector is received by, for example, a TCM or BCM decoder. The TCM/BCM decoder identifies the closest signal points in the signal constellation set, or “nearest neighbors,” for each dimension of the received signal vector. The TCM/BCM decoder then forms a test set that includes a plurality of multi-dimensional test vectors, where each dimension of each test vector is based on an identified nearest neighbor. In particular, each test point in the test set is based on a different combination of the nearest neighbors. The TCM/BCM decoder can compute branch metrics based on only the test points in the test set, and can make detection decisions using the computed branch metrics.

Abstract: The present invention relates to a method of calculating a log-likelihood ratio and a method of detecting a transmission signal. According to the present invention, when a transmission symbol candidate vector is detected on the basis of a received signal, a threshold value and an ML metric of each transmission symbol candidate vector are calculated and the ML metric that is larger than the threshold value is updated by the threshold value. Further, a log-likelihood ratio of the transmission signal bit is calculated using the updated ML metric and the threshold value, and a transmission signal is detected using the log-likelihood ratio.

Abstract: Provided is an iterative residual frequency and phase compensation apparatus for an OFDM system and a method thereof. The apparatus includes: a first classifying unit for classifying symbol sequences by each subcarrier wave; a soft-decision calculating unit for calculating a soft-decision value of a data symbol using a soft-decision reliability obtained from iterative decoding performed by the iterative decoder; a classifying unit for classifying the soft-decision values by a carrier wave; a frequency estimating unit for estimating a residual frequency error of each carrier wave using the soft-decision value; a phase estimating unit for estimating an average residual phase error using the soft-decision value; a frequency and phase compensating unit for compensating frequencies and phases for input symbols of each carrier wave using the estimated frequency error and the estimated phase error; and a buffer for temporally storing the compensated symbols to provide it to the first classifying unit.

Abstract: Methods and apparatus are provided for storing survivor paths in a Viterbi detector. At least one register and at least one pointer are maintained for each state. Each register stores a bit sequence associated with a Viterbi state and each pointer points to one of the registers. A trellis transition type is determined, for example, based on a decision from an add/compare/select unit. One or more predefined rules based on a trellis structure and the trellis transition type are employed to exchange one or more of the pointers and to update one or more of the at least one registers. A survivor path memory is also disclosed for a Viterbi detector. The survivor path memory comprises a plurality of columns, each associated with a different time step, and an input processor. Each column comprises a latch for storing one bit of a bit sequence associated with a Viterbi state.

Abstract: A method for implementation of error correction decoding of quadrature layered modulation QLM communications. A bound on communications capacity derived using ideal QLM is approximated with QLM communications links which support data rates independent of the Shannon bound. Trellis symbol and bit demodulation algorithms recover QLM data symbols and bit algorithms offer computational efficiency at a cost of decisioning errors. Correlated bit decisioning error correction decoding and re-encoding can be implemented in a bit demodulation algorithm. Trellis demodulation and trellis decoding algorithms support parallel implementations, and concatenated implementations wherein the error correction decoding is implemented after the QLM demodulation. Concatenated implementation supports turbo decoding, MAP decoding, convolutional decoding, and block decoding by using the decisioning metrics available from QLM demodulation in place of generating the decisioning metrics directly from the detected symbol measurements.

Abstract: One embodiment of the present invention relates to a method of monitoring impulse noise. In the method, clusters of corrupted symbols in a stream of symbols are characterized in accordance with a cluster parameter associated with the clusters. Other methods and systems are also disclosed.

Abstract: A system and method for Viterbi decoding utilizes a general purpose processor with application specific extensions to perform Viterbi decoding operations specified in a Viterbi decoding algorithm stored in memory.

Abstract: A method and a circuit for decoding a coded signal including a first decoding system capable of receiving the coded signal and of providing a first signal comprising portions considered correct and a second decoding system capable of providing a second signal from the coded signal and from portions considered correct of the first signal.

Abstract: An apparatus and method of encoding a block Low Density Parity Check (LDPC) code in a signal transmission apparatus is disclosed. The method includes generating a block LDPC codeword by encoding an information vector using a second parity check matrix when a code rate to be used in the signal transmission apparatus is a second code rate less than a code rate of a first parity check matrix as a first code rate.

Abstract: An improved Viterbi detector is disclosed in which each branch metric is calculated based on noise statistics that depend on the signal hypothesis corresponding to the branch. Also disclosed is a method of reducing the complexity of the branch metric calculations by clustering branches corresponding to signals with similar signal-dependent noise statistics. A feature of this architecture is that the branch metrics (and their corresponding square difference operators) are clustered into multiple groups, where all the members of each group draw input from a single, shared noise predictive filter corresponding to the group. In recording technologies as practiced today, physical imperfections in the representation of recorded user data in the recording medium itself are becoming the dominate source of noise in the read back data. This noise is highly dependent on what was (intended to be) written in the medium. The disclosed Viterbi detector exploits this statistical dependence of the noise on the signal.

Abstract: Techniques for detecting received sequences when certain signaling characteristics (e.g., transport formats, rates) are not known a priori at the receiver. In one method, a sequence for a transmitted message is received, and a metric value is computed for each of a number of hypothesized messages corresponding to a number of hypotheses for the unknown signaling characteristic of the transmitted message. The metric value is computed based on a MAP metric derived to approximately maximize a joint a posteriori probability between the received sequence and the hypothesized messages. The hypothesized message having the best metric value is selected as the transmitted message. The specific form of the MAP metric is dependent on the particular signaling scheme used to map the message to its corresponding sequence, and may be used for blind transport format detection (BTFD) in a W-CDMA system and blind rate detection in an IS-95 CDMA system.