Abstract: Techniques are provided for transmitting and receiving a mother code in an incremental redundancy hybrid automatic repeat-request protocol. A set of information bits corresponding to a message is encoded and interleaved to produce the mother code. Each bit position of the mother code is mapped to an output symbol, and each output symbol is mapped to an antenna for transmission. One or more transmissions are performed, where each transmission includes puncturing the mother code by selecting one or more symbols from the output symbols, and transmitting each symbol in the one or more symbols on an antenna corresponding to that symbol. The mother code is decoded, in part, by determining combinable bits contained within a set of received symbols and computing one or more log-likelihood ratio values corresponding to each symbol in the set of received symbols.

Abstract: A wireless receiver uses a joint detection Viterbi (JDV) algorithm to demodulate a signal that has a desired signal component and an interference signal component. The desired signal component includes a training sequence and at least one data field. The training sequence and a corresponding portion of the interference signal component is demodulated using the JDV algorithm to evaluate possible transmitted training sequences and interference signal sequences, and channel estimations for the desired signal component and the interference signal component are generated. The at least one data field is demodulated according to the JDV algorithm using the channel estimations as initial channel estimates for the JDV algorithm.

Abstract: A decoding device includes a BM calculator calculating a branch metric in a Log-MAP algorithm from received data and extrinsic information, an ACS operator calculating a maximum value of a path metric based on the branch metric, a correction term calculator calculating a Jacobian correction value of the path metric, and a correction operator correcting the path metric by adjusting a value of the Jacobian correction value based on a size of the received data and adding the adjusted correction value to the maximum value.

Abstract: A non-linear post-processor for estimating at least one source of signal-dependent noise is disclosed. The post processor may receive a set of preliminary decisions from a sub-optimal detector along with the sampled data signal. The post-processor may then compute the transition jitter and white noise associated with each preliminary decision in the set and assign a cost metric to each decision based on the total signal noise. The post-processor may output the decision with the lowest cost metric as the final decision of the detector.

Abstract: One embodiment of the invention features a programmable gain stage in analog update circuitry to overcome the accuracy limitation of the circuit gain and the maintenance of small finite number of possible sequence estimates.

Abstract: Systems, devices and techniques for soft-in, soft-out (SISO) decoding can include accessing initial soft information on a series of data units received over a communication channel, using a cyclic graphical model to represent a coding scheme associated with the received data units, obtaining cycle-free graphical models for a plurality of second conditions allowable by the coding scheme, and generating soft-out decision information by using information that includes the obtained cycle-free graphical models and the initial soft information. The number of obtained cycle-free graphical models can be less than a total number of conditions associated with the cyclic graphical model. Soft decision information can include confidence levels for each data unit.

Abstract: Apparatus and methods are disclosed for decoding data stored on a data storage medium. A disclosed decoding method and decoder include a radial incoherence (RI) detector that increases the probability of detecting RI and improves the decoding performance in terms of the bit error rate of the decoded signal. RI is detected by comparing an input signal to the decoder against a RI threshold value and generating a RI-type signal. The RI detector may include a filter for filtering out noise and error in the RI-type signal, an adaptive threshold unit that adjusts the RI threshold value based upon the RI-type signal, a transition-based threshold unit that adjusts the RI threshold value based upon each transition in the input signal, or a path-based threshold unit that adjusts the RI threshold value based upon a best surviving path corresponding to the input signal, in combination or alone.

Abstract: In a particular embodiment, a forward error correction (FEC) decoder is disclosed that includes an input responsive to a communication channel to receive sampled bits from a continuous bit stream. The circuit device further includes a logic circuit to alternately provide sets of the received sampled bits from the continuous bit stream to one of a first syndrome generator and a second syndrome generator to correct errors in the sets of sampled bits to produce a decoded output related to the continuous bit stream.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide data processing circuits including a pattern detection circuit having at least two data detector circuits each operable to receive the same series of data samples and to provide a first detected data output and a second detected data output, respectively. In addition, the data pattern detection circuit includes a result combining circuit that is operable to assert a pattern found output based at least in part on the first detected data output and the second detected data output.

Abstract: An application specific processor to implement a Viterbi decode algorithm for channel decoding functions of received symbols. The Viterbi decode algorithm is at least one of a Bit Serial decode algorithm, and block based decode algorithm. The application specific processor includes a Load-Store, Logical and De-puncturing (LLD) slot that performs a Load-Store function, a Logical function, a De-puncturing function, and a Trace-back Address generation function, a Branch Metric Compute (BMU) slot that performs Radix-2 branch metric computations, Radix-4 branch metric computations, and Squared Euclidean Branch Metric computations, and an Add-Compare-Select (ACS) slot that performs Radix-2 Path metric computations, Radix-4 Path metric computations, best state computations, and a decision bit generation. The LLD slot, the BMU slot and the ACS slot perform in a software pipelined manner to enable high speed Viterbi decoding functions.

Abstract: A method for decoding of multiple wireless signals by a chase combining hybrid-automatic-repeat-request CC-HARQ receiver includes demodulating wireless signals received from respective mobile sources using an effective channel matrix and decision statistics; updating log-likelihood-ratios LLRs and decoding the received codewords using the corresponding updated LLRs; determining set of correctly decoded codewords using a cyclic redundancy check; updating the effective channel matrix and decision statistics responsive to the step of determining; and resetting the effective channel matrix and decision statistics in the event that the number of decoding errors for a codeword exceeds its maximum limit after storing the updated LLRs of all remaining erroneously decoded codewords for which the number of decoding errors is below the respective maximum limit.

Abstract: The present patent application discloses a method and apparatus for decoding, comprising decoding signals iteratively, mutually exchanging extrinsic information, calculating APP LLRs for both systematic and parity bits and making a hard decision after a plurality of iterations is completed based on accumulated soft information. The present patent application also discloses a method and apparatus for post decoding soft interference canceling, comprising generating updated a posteriori probabilities for systematic and parity bits from a turbo decoder, mapping the posteriori probabilities to soft symbols, quantizing the soft symbols, re-encoding a data packet, filtering a chip sequence, reconstructing an interference waveform, and scaling reconstruction filter coefficients using the symbols.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is disclosed that includes a first data detection circuit that applies a phase dependent data detection algorithm to a data set such that a first output of the first data detection circuit varies depending upon a phase of the data set presented to the first data detection circuit. A first phase of the data set is presented to the first data detection circuit. The circuits further include a decoder circuit that applies a decoding algorithm to the first output to yield a decoded output, and a phase shift circuit that phase shifts the decoded output such that a second phase of the data set is provided as a phase shifted output.

Abstract: Apparatus and methods store error recovery data in different dimensions of a memory array. For example, in one dimension, block error correction codes (ECC) are used, and in another dimension, supplemental error correction codes, such as convolutional codes, are used. By using separate dimensions, the likelihood that a defect affects both error recovery techniques is lessened, thereby increasing the probability that error recovery can be performed successfully. In one example, block error correction codes are used for data stored along rows, and this data is stored in one level of multiple-level cells of the array. Supplemental error correction codes are used for data stored along columns, such as along the cells of a string, and the supplemental error correction codes are stored in a different level than the error correction codes.

Abstract: A code encoding apparatus includes a delay circuit and a code generator. The delay circuit generates delayed information based on p-bit input information received in parallel. The delayed information is generated according to a clock. The code generator generates n·p-bit code based on at least one of the input information and the delayed information, where n is a rational number.

Abstract: A method includes estimating quadrature amplitude modulated QAM symbols in an LDPC encoded OFDM signal for transmission, performing channel estimation by training sequence to determine channel coefficients in reception of the LDPC encoded OFDM signal; and obtaining channel information detection and decoding of the LDPC encoded signal.

Abstract: A decoder includes circuitry for generating bits representing received signals, and beliefs representing an associated reliability of each bit. A bit node computation block receives the bits and associated beliefs, and generates a plurality of bit node messages. A plurality of M serially-connected pipeline stages receive the bit node messages and after M decoding cycles, and generate a plurality of check node messages once per decoding cycle, wherein for each iteration cycle, each of the M serially-connected pipeline stages performs check node computations using all of J component codes, wherein each one of the M serially-connected pipeline stages performs check node computations once per decoding cycle using a single component code that is different that component codes used for all other of the M serially-connected pipeline stages, wherein J is at least as great as M, and wherein each iteration includes M decoding cycles.

Abstract: Embodiments of a broadcast receiver and method for optimizing a scale factor in a log-likelihood ratio (LLR) mapper are generally described herein. In some embodiments, the broadcast receiver includes an LLR mapper to generate LLRs from demodulated data samples, a low-density parity-check (LDPC) decoder to generate decoded data from the LLRs, and an LLR optimizer to dynamically select a scale factor for the LLR mapper based on a number of iterations for convergence of the LDPC decoder. In some embodiments, the LLR optimizer iteratively revises the scale factor during receipt of broadcast signals until the number of iterations of the iterative decoder is either minimized for convergence or minimized for convergence failures.

Abstract: A system having a transmission unit transmitting an output data signal formed from output data and related error detection code and a corresponding receiving unit. The output data signal is pre-emphasized by a pre-emphasis driver in the transmission unit. The receiving unit includes an equalizer equalizing the received output data signal and an error detector analyzing the error detection code to determine whether a bit error is present in the received data. Upon successive data transmission failures either an equalization coefficient in the equalizer or a pre-emphasis coefficient in the pre-emphasis driver are changed.

Abstract: Methods and devices are disclosed for encoding and decoding convolutional codes in a communication system. In various embodiments of the disclosure, a codeword comprises message data and parity data. A convolutional codeword is generated by multiplying the message data and the parity data with a convolutional polynomial. The convolutional codeword may be decoded by a convolutional code decoder that uses the convolutional polynomial and a maximum likelihood divisor to obtain a maximum likelihood message from the convolutional codeword.

Abstract: A method and apparatus for turbo code decoding are provided to reduce memory consumption during calculation of state metrics. In an embodiment of a turbo code decoder, a natural recursion unit comprises a plurality of add-compare-select (ACS) units performing natural recursion operations to generate a state metric. The original state metric is then converted to a differential metric before being stored into a memory device. The differential metric contains less data than the state metric so that memory consumption is reduced. To restore the original state metric from the differential metric, a plurality of revival units operating in parallel is provided. Thereby, the state metric is reacquired from the differential metric, and a Log Likelihood Recursion (LLR) operation is accordingly performed by an LLR unit.

Abstract: A feedforward receiver and method are described herein that address inter-symbol interference in received symbols by using an enhanced equalizer to generate joint soft values (joint information of a previous modem bit x? and a modem bit x) and an enhanced decoder which uses the joint soft values and side information (bias about the previous modem bit x?) to output a more reliable information bit x.

Abstract: The present disclosure includes apparatus, systems and techniques relating to iterative decoder memory arrangement. In some implementations, an apparatus includes a memory module to communicate with an iterative code decoder. The memory module includes a single R memory component to store R data associated with a current codeword, and R data associated with a previous codeword. The memory module includes a Q memory component to store Q data associated with the current codeword, and Q data associated with the previous codeword. The memory module includes a channel detector memory component to store channel extrinsic information.

Abstract: In at least some disclosed embodiments, a system includes a Viterbi decoder and predecoding logic coupled to the Viterbi decoder. The predecoding logic decodes encoded data. The system further includes detection logic coupled to the predecoding logic. The detection logic tests decoded data, and the detection logic produces a binary result. The Viterbi decoder is enabled if the binary result is a first value, and the Viterbi decoder is disabled if the binary result is a second value.

Abstract: The claimed subject matter relates to encoding and decoding information in a wireless communication system using soft-demodulation and interleaving of concatenated code received in a strip channel. A set of symbols is received containing a plurality of information bits, dividing the received set of symbols into a plurality of subsets of symbols, each subset corresponding to the input of an inner code demodulation selecting a set of initial a priori values of the inner code demodulation for each subset of symbols, and demodulating each subset of symbols, using the initial a priori values of the subset of symbols and an inner code generator matrix, to generate a plurality of first soft information values as the output of the inner code demodulation.

Abstract: A decoder is provided which is configured to operate upon an input encoded sequence using a wrap around Viterbi procedure, and a decoding method which employs the decoder. The decoder/method is configured to output a selected path as a decode sequence, and to avoid storing, for a current iteration of the wrap-around Viterbi procedure other than a first iteration, a best path up to the current iteration.

Abstract: An apparatus for determining a symbol estimate includes a detection unit, an information storage, a channel decoder, and an estimator. One or more detectors of the detection unit is configured to detect a first data stream and the one or more detectors or one or more other detectors are configured to detect a second data stream when interference cancellation is carried out and when interference cancellation is not carried out parallel to detection of a first data stream to obtain results of detection. The information storage is configured to store the results of the detection of the second data stream, and the channel decoder is configured to channel decode a detected first data stream. The estimator is configured to determine a symbol estimate by using the stored results of the detection of the second data stream and based on the success of the channel decoding of the first data stream.

Abstract: Circuitry and methods can be provided to correct errors in decision bits. A plurality of error event syndromes can be computed for a first plurality of error events. For each of a plurality of error event syndromes, two best error events can be selected. A cross-syndrome second best error event can be selected from among the first plurality of error events. A global second best error event can be selected from among the cross-syndrome second best error event and the second best per-syndrome error events. A second plurality of error events can be selected from among the global second best error event and the best per-syndrome error events. The second plurality of error events can be used for data post-processing.

Abstract: A method and a system for decoding information signals encoded in accordance with a multi-state encoding scheme and transmitted over a multi-dimensional transmission channel by computing a distance of a received word from a codeword. One-dimensional (1D) input signals are processed in a pair of symbol decoders, implemented as look-up tables, to produce a pair of 1D errors, with each representing a distance metric between the input signal and a symbol in one of two disjoint symbol-subsets. The 1D errors are combined based on the multi-state encoding scheme in order to produce a set of multi-dimensional error terms. Each of the multi-dimensional error terms corresponds to a distance between a received word and a nearest codeword.

Abstract: An improved method and apparatus for performing operations (such as Viterbi decode) in digital processors using a reduced number of cycles. In one aspect, the invention comprises efficient methods for performing multiple “butterfly” add-compare-select (ACS) operations using an improved dual butterfly (DVBF) extension instruction added to the instruction set of a user-configured processor. The DVBF extension allows performance of two butterfly operations in a single cycle. In another aspect, an improved path metric addressing scheme is disclosed. An integrated circuit (IC) device incorporating the aforementioned features, and method of designing such IC, are also disclosed.

Abstract: A decoding apparatus includes a row processing unit 5 and a column processing unit 6 for performing a calculation and an update of probability information with row processing and column processing according to a Min-Sum algorithm on a received signal which is low-density parity-check coded in batches of 1 bit or a predetermined number of bits, a decoded result judgment unit 8 for determining a decoded result from a hard decision of a posterior value, for performing a parity check on the decoded result, and for judging whether or not the decoded result is correct, and a control unit for controlling iteration of decoding processing by the row processing unit 5 and column processing unit 6 on the basis of the judgment result of the decoded result judgment unit 8.

Abstract: Methods, software, circuits and systems involving a low complexity, tailbiting decoder. In various embodiments, the method relates to concatenating an initial and/or terminal subblock of the serial data block and outputting decoded data from an internal block of the modified data block. The circuitry generally includes a buffer, logic configured to concatenate an initial and/or terminal subblock to the serial data block, and a decoder configured to decode the data block, estimate starting and ending states for the data block, and output an internal portion of the serial data block and the one or more sequences as decoded data. The invention advantageously reduces the complexity of a suboptimal convolutional decoder, ensures smooth transitions at the beginning and end of the serial data block during decoding, and increases the reliability of the starting and ending states, without adding overhead to the transmitted data block.

Abstract: A method for communication includes receiving a spatially-multiplexed signal using multiple receivers to produce multiple respective received signals. The spatially-multiplexed signal includes multiple simultaneously-transmitted symbols, which are selected from respective sets of constellation symbols, each constellation symbol representing a respective set of values of a group of data bits. Combinations of the constellation symbols are traversed iteratively. Each combination includes one constellation symbol from each of the sets of the constellation symbols and represents N data bits. The traversed combinations are searched for a combination that matches the received signals. During traversal of the combinations, at least 2N measures of likelihood regarding the values of the data bits represented by each traversed combination are accumulated. The accumulated measures of likelihood are processed to produce soft bit metrics.

Abstract: Novel systems and methods are described in which performance of equalizers can be improved by reducing the effects of error propagation in equalizers that use a Viterbi Decoder. Systems and methods of symbol correction in prediction decision feedback equalization architectures are described including systems and methods that include an enhanced Viterbi decoder and novel methods of symbol correction to obtain better system performance. The use of a blending algorithm is described to reduce errors in symbol decoding. Histories of deep trace back depth symbols can be maintained to enable more accurate decisions. Systems and methods described can provide advantage in the feedback path of adaptive equalizers in trellis decoders. The invention provides novel techniques for improving the performance of equalizers by reducing the effects of error propagation in equalizers that use a Viterbi Decoder.

Abstract: A method for decoding tail-biting convolutional codes. The method includes initializing a correction depth, selecting a first starting state from a set of encoding states, and initializing a metric value for the selected starting state as zero and the other states as infinity. The input bit stream is read and a Search Depth Viterbi algorithm (SDVA) is performed to determine path metrics and identify a minimum-metric path. The ending state for the minimum-metric path is determined and the output for this ending state is identified as “previous output.” A second starting state is set to the ending state of the minimum-metric path, and symbols equal to the correction depth from the previous output are read. The SDVA is performed on the second set of read symbols to generate a corrected output. A decoded output is generated by replacing symbols at the beginning of the previous output with the corrected output.

Abstract: A method and system are provided for improving the performance of a trellis-based decoder. States with reduced uncertainty (SRUs) are defined for one or more predetermined fields in an encoded message. Metrics are set for the SRUs such that candidate paths through a trellis-based decoding process are eliminated for those states that are not SRUs.

Abstract: Embodiments of the present invention provide a read channel including a front end to receive an optical image, convert the optical image into multi-bit soft information, and to serially transmit the multi-bit soft information to other components of the read channel. Other embodiments may be described and claimed.

Abstract: A method of obtaining a Viterbi decoded value is disclosed. A decision output is stored to one of a plurality of buffer elements, wherein at least one other buffer element in the plurality is not changing; and data is exposed in the buffer element. A plurality of stored decision outputs is obtained from the plurality of buffers elements. The obtained plurality of stored decision outputs is processed to obtain a Viterbi decoded value.

Abstract: Joint erasure marking Viterbi algorithm (JEVA), decoder schemes, methods, and systems are provided which perform robust trellis decoder techniques. The provided JEVA decoding schemes are shown to be maximum likelihood decoding schemes that find the most likely transmitted code sequence with a set of symbol erasures, without knowledge of the impulsive noise probability distribution function, and can be implemented sequentially such that they are well suited for dynamically changing impulsive noise channels. In addition, the disclosed details enable various refinements and modifications according to decoder and system design considerations. For example, truncated JEVA is provided for continuous transmission and long frame applications.

Abstract: Methods and corresponding systems in a Viterbi decoder include computing a maximum likelihood (ML) path in a Viterbi trellis in response to executing a first Viterbi algorithm. Thereafter, one or more merge points are selected on the ML path in a second Viterbi algorithm, wherein the merge points each have a path metric difference, which is a difference between an ML path metric at the merge point and a non-surviving path metric at the merge point. Merge points are selected based upon relative path metric differences associated with nodes on the ML path. Next, alternate paths in the Viterbi trellis are computed based on the ML path with alternate paths substituted at corresponding merge points. A passing decoded bit sequence is output in response to passing an error check, wherein the passing decoded bit sequence is associated with one of the one or more alternate paths.

Abstract: A DTV transmitter includes a pre-processor which pre-processes enhanced data by coding the enhanced data for forward error correction (FEC) and expanding the FEC-coded enhanced data, a data formatter which generates enhanced data packets having the pre-processed enhanced data and known data, and a multiplexer which multiplexes the enhanced data packets with main data packets. The DTV transmitter further includes an RS encoder which adds systematic parity data to each main data packet and adds RS parity place holders to each enhanced data packet, and a data interleaver which interleaves the RS-coded main and enhanced data packets and outputs a group of interleaved data packets having a head, a body, and a tail. The body includes a plurality of consecutive enhanced data packets, to which a known data sequence is periodically inserted.

Abstract: A system, method, and device for detecting short burst errors in a queue-based system is disclosed. A first detector performs a data detection on a first input data set at a first time and on a second input data set at a second time. A second detector performs a data re-detection on input data sets. A decoder decodes derivations of the outputs of the first and second detector. A short burst error detector may perform a short burst error detection on decoded data and erase any detected errors. An output data buffer stores and orders the decoded data for output.

Abstract: Systems and techniques to interpret signals on a noisy channel. In general, in one implementation, the technique includes: interpreting an input signal as discrete values, and in response to an inadequate signal, averaging multiple signals to improve interpretation of the input signal. The input signal can be a read signal from a storage medium, such as those found in disk drives. A read channel can include a buffer and an averaging circuit capable of different signal averaging approaches in a retry mode, including making signal averaging decisions based on a signal quality measure. Buffering read signals can be done in alternative locations in the read channel and can involve buffering of many prior read signals and/or buffering of an averaged read signal.

Abstract: A non-linear detector for detecting signals with signal-dependent noise is disclosed. The detector may choose a data sequence that maximizes the conditional probability of detecting the channel data. Since the channel may be time-varying and the precise channel characteristics may be unknown, the detector may adapt one or more branch metric parameters before sending the parameters to a loading block. In the loading block, the branch metric parameters may be normalized and part of the branch metric may be pre-computed to reduce the complexity of the detector. The loading block may then provide the branch metric parameters and any pre-computation to the detector. The detector may then calculate the branch metric associated with the input signal and output the channel data.

Abstract: Various embodiments of the present invention provide systems and methods for data regeneration. For example, a system for data regeneration is disclosed that includes a data input derived from the medium. A data detector and a data recovery system receive the data input. The data detector provides a first soft output, and the data recovery system provides a second soft output. The first soft output and the second soft output are provided to a multiplexer. A media defect detector performs a media defect detection process, and provides a defect flag that indicates whether the data input is derived from a defective portion of the medium. The defect flag is provided to the multiplexer where it is used to select whether the first soft output or the second soft output is provides as an extrinsic output.

Abstract: Aspects of a method and system for redundancy-based decoding of voice content in a wireless local area network (WLAN) system are provided. A WLAN receiver may determine whether a decoded portion of a received packet comprises voice content and may select a redundancy-based decoder to decode a remaining portion of the packet when voice content is detected. The redundancy-based decoder may be a Viterbi decoder. The redundancy-based decoder may be selected to decode a determined number of subsequent packets or to decode subsequent packets for a determined amount of time. After decoding the remaining portion of the packet and any subsequent packets, the WLAN receiver may select a standard Viterbi decoder to decode additional received packets. The WLAN receiver may generate at least one signal to select the redundancy-based decoder and the standard Viterbi decoder.

Abstract: Methods and apparatus are provided for storing survivor paths in a Viterbi detector. The invention maintains at least one register and at least one pointer for each state. Each register stores a bit sequence associated with a Viterbi state and each pointer points to one of the registers. One or more predefined rules based on a trellis structure are employed to exchange one or more of the pointers. A survivor path memory is also disclosed for a Viterbi detector. The survivor path memory comprises a plurality of columns, each associated with a different time step, and an input processor. Each column comprises a flip flop for storing one bit or portion of a bit sequence associated with a Viterbi state; and a multiplexer for each state controlled by a case signal indicating a time step, the multiplexer selecting a state from a previous time step, wherein an output of the multiplexer of a given state is connected to at least one data input of a flip flop of the given state.

Abstract: An ACS unit of a Viterbi decoder and a method for calculating the bit error rate (BER) before Viterbi decoder are provided. The ACS unit includes a state calculator and a BER calculator. The state calculator calculates the state metric of a corresponding target state in the trellis diagram and selects one of two candidate source states as the selected source state of the target state. The state calculator also provides a selection signal indicating the selected source state. The BER calculator is coupled to the state calculator for providing the sum of the BER of the selected source state and the bit error count (BEC) of the transition from the selected source state to the target state as the BER of the target state.

Abstract: A method for decoding tail-biting convolutional codes. The method includes initializing a correction depth, selecting a first starting state from a set of encoding states, and initializing a metric value for the selected starting state as zero and the other states as infinity. The input bit stream is read and a Search Depth Viterbi algorithm (SDVA) is performed to determine path metrics and identify a minimum-metric path. The ending state for the minimum-metric path is determined and the output for this ending state is identified as “previous output.” A second starting state is set to the ending state of the minimum-metric path, and symbols equal to the correction depth from the previous output are read. The SDVA is performed on the second set of read symbols to generate a corrected output. A decoded output is generated by replacing symbols at the beginning of the previous output with the corrected output.

Abstract: Provided are a detector for a multi-level modulated signal and a detection method using the same, and an iterative receiver for a multi-level modulated signal and an iteratively receiving method using the same. The detector includes: a channel estimator estimating a channel response of each of a plurality of bits included in at least one received signal based on multi-level modulation; a hard decision unit, for each bit, selecting at least one of a plurality of bits remaining by excluding the bit and performing a hard decision based on a pre-probability of the selected bit; and a reliability calculator calculating reliability of each of all the bits in the received signal based on the received signal from which the hard-decided bit component is cancelled and the estimated channel response. Accordingly, the computation amount according to detection can be reduced without the degradation of performance.