Abstract: An apparatus having a circuit and one or more processor is disclosed. The circuit is configured to receive a codeword from a memory. The memory is nonvolatile. The codeword generally has one or more errors. The processors are configured to generate read data by decoding the codeword repeatedly. The decoding includes a soft-decision decoding that uses a plurality of parameters calculated by (i) a first procedure, (ii) a second procedure in response to a plurality of failures of the decoding to converge using the first procedure and (iii) a third procedure in response to another failure of the decoding to converge using the second procedure.

Abstract: A receiver system and method for recovering information from a symbol data sequence Y. The symbol data sequence Y corresponds to a symbol data sequence X that is transmitted onto the channel by a transmitter. The symbol data sequence X is generated by the transmitter based on associated information bits. At the receiver, a set of two or more processors operate in parallel on two or more overlapping subsequences of the symbol data sequence Y, where each of the two or more overlapping subsequences of the symbol data sequence Y corresponds to a respective portion of a trellis. The trellis describes redundancy in the symbol data sequence Y. The action of operating in parallel generates soft estimates for the associated information bits. The soft estimates are useable to form a receive message corresponding to the associated information bits.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding.

Abstract: Methods and apparatus for tail termination are provided that include a decoder that includes a processor configured to a forward state metric and a backward state metric wherein each iteration of an initial state of the backward state metric is fetched from a memory and is pre-computed without feedback from a decoding iteration. Each decoding iteration is substantially identical, and the backward state metric that is pre-computed is used for a subsequent iteration. The decoder may include a turbo decoder or a radix-4 decoder.

Abstract: A low-density parity check (LDPC) decoder is provided for decoding low-density parity check (LDPC) encoded data wherein the processing order of the layers of the LDPC parity check matrix are rearranged during the decode process in an attempt to avoid error mechanisms brought about by the iterative nature of the LDPC belief propagation decoding process, such as stopping sets and trapping sets.

Abstract: A bitstream generator includes at least first and second bitstream generator stages connected in a cascaded arrangement. The first bitstream generator stage includes a first adder which receives an input signal and generates a first error signal indicative of a difference between the input signal and a first bitstream candidate representing a closest approximation to the input signal among multiple bitstream candidates generated by the first bitstream generator stage. The second bitstream generator stage includes a second adder which receives the first error signal and generates a second error signal indicative of a difference between the first error signal and a second bitstream candidate representing a closest approximation to the input signal among multiple bitstream candidates generated by the second bitstream generator stage. A third adder in the bitstream generator receives the first and second bitstream candidates and generates an output signal more closely approximating the input signal.

Abstract: Systems and methods are provided for improved designs and performance for iterative decoder systems. In some embodiments, the iterative decoder may be decoupled from FIR samples through an FIR RAM, thus resulting in a less complex design and shorter processing times. In some embodiments, an intermediate memory may be used when passing information between the SOVA and LDPC of the iterative decoder. In some embodiments, the SOVA-required information may be continuously serialized from information received from the LDPC during each LDPC iteration. In some embodiments, the 1/(1+D2) precoder of the HR RLL encoder may be split into two serial, 1/(1+D) precoders. One 1/(1+D) precoder may be pulled outside of the HR RLL encoder and used in conjunction with the iterative decoder. A 1/(1+D) precoder may be used with the iterative decoder while maintaining the RLL constraints imposed upon the encoded information by the HR RLL encoder.

Abstract: A method and system for a sequence estimation in a receiver, such as for use when receiving a sample of a received inter-symbol correlated (ISC) signal corresponding to a transmitted vector of L symbols, with L being a integer greater than 1, and with symbol L being a most-recent symbol and symbol 1 being least recent symbol of the vector. A plurality of candidate vectors may be generated, wherein element L?m of each candidate vector holding one of a plurality of possible values of the symbol L?m, with m is an integer greater than or equal to 1, and elements L?m+1 through L of each candidate vectors holding determined filler values. A plurality of metrics may be generated based on the plurality of candidate vectors, and based on the generated plurality of metrics, a best one of the possible values of the symbol L?m may be selected.

Abstract: A set of reliability metrics is provided for use by an iterative probabilistic decoding process for non-volatile storage. A plurality of sense operations are performed on at least one set of non-volatile storage elements which are programmed to a plurality of programming states. A set of reliability metrics such as logarithmic likelihood ratios is provided based on the sense operations. The set of reliability metrics is can be used by an iterative probabilistic decoding process in determining a programming state of at least one non-volatile storage element based on at least one subsequent sense operation involving the at least one non-volatile storage element. The plurality of sense operations can be performed at different ages (e.g., number of program/erase cycles) of the at least one set of non-volatile storage elements and the set of reliability metrics can be based on an average over the different ages.

Abstract: Apparatus and methods store data in a non-volatile solid state memory device according to a rate-compatible code, such as a rate-compatible convolutional code (RPCC). An example of such a memory device is a flash memory device. Data can initially be block encoded for error correction and detection. The block-coded data can be further convolutionally encoded. Convolutional-coded data can be punctured and stored in the memory device. The puncturing decreases the amount of memory used to store the data. Depending on conditions, the amount of puncturing can vary from no puncturing to a relatively high amount of puncturing to vary the amount of additional error correction provided and memory used. The punctured data can be decoded when data is to be read from the memory device.

Abstract: A Viterbi decoder module includes a branch metric module configured to calculate branch metrics corresponding to a continuous phase modulated signal. Each of the branch metrics corresponds to a respective path between stages of the Viterbi decoder module. A path metric module is configured to calculate a first cost metric associated with the first state of the next stage based on the first branch metric and the second branch metric, and calculate a second cost metric associated with the second state of the next stage based on the third branch metric and the fourth branch metric. A traceback module is configured to determine a maximum likelihood path between stages of the Viterbi decoder based on the first cost metric and the second cost metric. The Viterbi decoder module is configured to output decoded data based on the maximum likelihood path.

Abstract: A method of operation of a communication system includes: calculating a shift distance of a received signal having a distortion; calculating an approximate likelihood of the received signal matching a transmitted signal from the shift distance; determining a bias factor from the distortion; and selecting a determined modulation maximizing a combination of the approximate likelihood and the bias factor for communicating with a device.

Abstract: A technique includes jointly demodulating a desired signal and an interfering signal of a received signal in response to a carrier-to-interference ratio estimate for the received signal being below a threshold level. The jointly demodulating is based on first channel impulse response coefficients associated with the desired signal and second channel impulse response coefficients associated with the interfering signal. The technique includes determining the first channel impulse response coefficients based on a first cross-correlation function between the received signal and a training sequence of the desired signal and determining the second channel impulse response coefficients based on a second cross-correlation function between the received signal and a training sequence of the interfering signal.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a combination data decoder circuit. The combination data decoder circuit includes: a non-binary data decoder circuit and a binary data decoder circuit.

Abstract: An exemplary embodiment of the present invention provides an incremental lattice reduction method comprising: receiving an input signal at a plurality of input terminals; evaluating a reliability assessment condition using a primary symbol vector estimate of at least a portion of the input signal; terminating the incremental lattice reduction method if the reliability assessment condition is satisfied; and if the reliability assessment condition is not satisfied, performing at least one iteration of a lattice reduction detection sub-method to obtain a secondary symbol vector estimate.

Abstract: A decoding system suitable for Viterbi decoding includes a decoder that includes a state metrics array, a butterfly unit, and a constraint length multiplexer. The state metrics array includes registers in which each register is arranged to store a state metric for processing. The butterfly unit includes an array of butterfly elements where each butterfly element is arranged to generate intermediate state metrics in parallel with other butterfly elements in the butterfly unit. The constraint length multiplexer unit is arranged to generate new state metrics in response to the intermediate state metrics and a Viterbi constraint length value stored in a constraint length register. Transition bits can also be generated in response to the constraint length.

Abstract: A processor for processing digital data includes at least one butterfly operator for executing an FFT/IFFT computation. This butterfly operator contains a first stage of complex multiplication and a second stage of complex addition and subtraction. Each of these two stages contains a plurality of addition/subtraction hardware modules and data transmission links between these modules. At least a part of the addition/subtraction modules of each stage of the butterfly operator and at least a part of the links between these modules are configurable with the aid of at least one programmable parameter, between a first configuration in which the butterfly operator carries out said fast Fourier transform computation and a second configuration in which the butterfly operator carries out a computation of branch metrics values and of path metrics and survivors values of a Viterbi algorithm.

Abstract: In one embodiment a data decoding apparatus includes first and second decoding blocks configured to decode codeword bits in a first mode determined by a first probability of non-standard errors and a second mode determined by a second probability of non-standard errors. The apparatus also includes a mode modification logic configured to cause at least one of the first and second decoding blocks to operate in the second mode when the first and second decoding blocks fail to decode the codeword bits in the first mode. In another embodiment, a method includes decoding codeword bits in a first mode determined by a first probability of non-standard errors. When decoding the codeword bits in the first mode fails to decode the codeword bits, the codeword bits are decoded in a second mode determined by a second probability of non-standard errors.

Abstract: In one aspect, the present invention improves Turbo equalization and/or soft interference cancellation processing in communication receivers by providing an efficient and accurate technique to compute the second moment of a received symbol, e.g., an interfering symbol, as a function of the expected bit values of only those bits in the symbol that are magnitude-controlling bits according to a defined modulation constellation. Advantageously, the expected bit values in at least one embodiment are computed using a LUT that maps bit LLRs to corresponding hyperbolic tangent function values. Further, the expected symbol value is computed as a linear function of terms comprising the expected bit values and the soft symbol variance is efficiently computed from the second moment and the expected symbol value squared. This simplified processing reduces receiver complexity, particularly in the context of modulation constellations having non-constant magnitudes, and thus saves power and/or improves design economics.

Abstract: A method and system for decoding control data in GSM-based systems using inherent redundancy and physical constraints are presented. At least one estimated GSM-based bit sequence may be selected by performing searches that start from trellis junctions determined by the decoding algorithm. The estimated bit sequences may be selected based on corresponding redundancy verification parameters. At least one physical constraint test may be performed on the selected estimated GSM-based bit sequences to select a decoded output GSM-based bit sequence. A multilayer decoding process may comprise a burst process and a frame process. Results from a first burst process may be utilized to generate a decoded GSM bit sequence in the frame process. The frame process may utilize redundancy information and physical constraints to improve the performance of a decoding algorithm.

Abstract: A network coding method includes receiving a plurality of message packets each having a packet length. Encoding the plurality of message packets by applying a convolutional code across symbols in corresponding positions of the plurality of message packets obtaining a number of encoded packets. The number of encoded packets obtained being more than the number of message packets.

Abstract: A state metric calculator for calculating state metrics of stages in a trellis of a sequence estimation technique is described. The calculator has a processing path containing operations needed for calculating a state metric of a trellis stage from state metrics of an earlier trellis stage. One or more data stores are located in the processing path to divide the path into separate sections. The sections can then operate on the production of different state metrics to one another in, if desired, the same clock cycle.

Abstract: A method, implementable on a multiple-input, multiple-output symbol receiver, includes selecting a hypothesis for a second symbol value U2 from among the set of fixed constellation points, calculating a hypothesis for a first symbol value U1 from the resultant selected U2 value, and generating a first half of counter-hypotheses from interim results of calculating the hypotheses values.

Abstract: Systems, methods, and apparatus are provided for iteratively decoding a codeword. Once a codeword is received, the codeword is processed to generate an incremental hard decision value and a log likelihood ratio amplitude value. These values are generated by processing the codeword using a soft output Viterbi algorithm. A faulty symbol in the codeword is identified. A complete hard decision value is generated using the incremental hard decision value. The LLR amplitude value and complete hard decision value corresponding to the identified faulty symbol are selectively provided to a decoder and the decoder uses these values to decode the codeword.

Abstract: Various embodiments relate to a multi-standard Viterbi decoder. Based on programmable values for constraint length, generator polynomials, and code rate, the multi-standard Viterbi decoder may adhere to a specific convolutional code standard. At a given time, the multi-standard Viterbi decoder may receive a variety of convolutional codes through a channel and may process them using various forms of the trace back method. Various embodiments include a branch metric unit and path metric unit that include a variety of sub-units that may or may not be active based on the value of the programmable value. Various embodiments also enable the multi-standard Viterbi decoder to handle different forms of convolutional codes, such as tail-biting codes. In some embodiments, the multi-standard Viterbi decoder may also process at least two convolutional codes concurrently.

Abstract: A communication system includes: a module configured to decode a remainder portion of a receiver message using a mechanism with a compensation channel value calculated from decoding an evaluation portion of the receiver message with a different mechanism, or using a mechanism-controller generated using a mismatch characterization based on determining a partial-sensitive output and a partial-insensitive output, or a combination thereof for communicating with a device.

Abstract: Methods and apparatuses for combining error coding and modulation schemes are described herein. One or more methods include encoding data using linear error correcting code, modulating the encoded data, writing the modulated data to memory, and decoding the written data using a Viterbi algorithm and a linear error correcting code decoder.

Abstract: Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for data processing with a linear phase noise predictive filter. A data processing system includes an equalizer circuit operable to filter a digital data input to yield equalized data, a linear phase noise predictive finite impulse response filter operable to filter the equalized data to yield filtered data, and a data detector circuit operable to apply a data detection algorithm to the filtered data to yield a detected output. The greatest tap coefficient for the linear phase noise predictive finite impulse response filter is at a center tap.

Abstract: A communication device includes a turbo encoding section including a plurality of component encoders, wherein the plurality of component encoders within the turbo encoding section use different constraint lengths.

Abstract: An apparatus may include a channel estimation component to determine a channel estimation matrix H for a tone of a multiplicity of tones in a multiple input multiple output (MIMO) communications signal. The apparatus may further include a processor circuit coupled to the receiver component, and a flow selection component for execution on the processor circuit to calculate a figure of merit for power loss for the received tone based upon the channel estimation matrix, and based upon the calculated figure of merit, perform either a max-log calculation or a maximum likelihood calculation to determine a received signal metric, but not both calculations. Other embodiments are described and claimed.

Abstract: A signal detector/decoder is implemented in multiple stages. The beginning stage is configured to input channel data bits and to output hard data bits based on the channel bits and a maximum likelihood (ML) path. The next stage includes a postcoder coupled to receive channel domain information from the first stage and to convert the channel domain information to user domain information. The final stage includes a reliability unit coupled to receive the user domain information from the postcoder and to output user domain soft information for the hard data bits based on the ML path estimation and the user domain information.

Abstract: A method of searching for candidate codewords for a telecommunications system, the method comprising receiving a sequence of constellation points, producing a received FEC vector comprised of bits from the received constellation points, comparing the received FEC vector with a plurality of candidate codewords within a Dorsch decoding process using an ordered pattern, and terminating the search when a candidate codeword from among the plurality of candidate codewords is found residing within a predetermined range of a specified distance of the received FEC vector.

Abstract: The present invention is related to systems and methods for enhancing data detection in a data processing system. In one embodiment, a data processing system is disclosed that includes a data detector circuit that is governed at least in part based upon selected coefficients. The selected coefficients are selected as either a first set of coefficients or a second set of coefficients where the second set of coefficients has fewer coefficients than the first set of coefficients.

Abstract: One embodiment of the present includes a heterogeneous, high-performance, scalable processor having at least one W-type sub-processor capable of processing W bits in parallel, W being an integer value, at least one N-type sub-processor capable of processing N bits in parallel, N being an integer value smaller than W by a factor of two. The processor further includes a shared bus coupling the at least one W-type sub-processor and at least one N-type sub-processor and memory shared coupled to the at least one W-type sub-processor and the at least one N-type sub-processor, wherein the W-type sub-processor rearranges memory to accommodate execution of applications allowing for fast operations.

Abstract: A method for estimating a scrambling code used on an uplink of a WCDMA system. The scrambling code is obtained from a Gold code, sum of a first specific M-sequence of the user and of a second M-sequence known from the receiver. After sampling of the signal received at the chip frequency of the scrambling code, the successive samples are subject to a differential treatment and the sequence of differential values is multiplied by the second M-sequence. The observables thereby obtained are decoded with the aid of a belief propagation iterative decoding. The decoded values then serve to determine the content of the shift register of the generator of the first M-sequence. One then deduces therefrom the Gold code and an estimation of the scrambling code, ?.

Abstract: A method of generating a reliability indicator for decoding an encoded signal transmitted from a transmitter to a receiver via a wireless channel subject to fading. The method comprises: receiving symbols of the encoded signal; generating a reliability indicator for decoding at least some of the symbols selectively based on one or both of a statistical model representing additive white Gaussian noise (AWGN) in the encoded signal and a statistical model representing fading of the encoded signal; and selecting the statistical model based on signal characteristics of the wireless channel.

Abstract: A system and method for determining a transport format of a transport channel is described. A guiding stream is received on a guiding transport channel and a guided stream is received on a guided transport channel. The guided stream is convolutionally decoded to produce a plurality of Viterbi path metrics. A transport format for the guided transport channel is selected from possible transport formats. The possible transport formats are determined by information provided on the guiding transport channel. The selection of the transport format is based at least in part on a metric computed from a combination of the Viterbi path metrics.

Abstract: Provided is a receiver for processing VSB signal. The receiver includes a first equalizer/decoder unit and a second equalizer/decoder unit. The first equalizer/decoder unit performs a first equalizing operation, first TCM decoding and first RS decoding on a received symbol to output a first dibit. The second equalizer/decoder unit performs a second equalizing operation, second TCM decoding and second RS decoding on the received symbol to output a transport stream. The first dibit is provided as a priori information for a soft-decision operation of the second TCM decoding.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is disclosed that includes first and second data detectors and an error cancellation circuit. The first data detector is operable to perform a data detection process on a first signal derived from a data input to yield a detected output. The second data detector circuit is operable to perform a data detection process on a second signal derived from the data input to yield a second detected output. The error cancellation circuit is operable to combine a first error signal derived from the detected output with a second error signal derived from the second detected output to yield a feedback signal. The feedback signal is operable to modify the data input during a subsequent period.

Abstract: Inter-track-interference correlation and cancellation for disk drive application includes receiving an input sequence of samples; and simultaneously processing the input sequence in at least a detector over one or more iterations while processing the input sequence to produce inter-track-interference information during at least a portion of one of the one or more iterations.

Abstract: In one embodiment, a tape drive system includes a soft detector for executing a first forward loop of a detection algorithm on a first block of signal samples during a first time interval; and logic for executing forward and reverse loops during several time intervals; and logic adapted for outputting a first decoded block of signal samples based on the executing the decoding algorithm on the first block during a sixth time interval, wherein a sum of second, third, fourth, fifth, and sixth time intervals are about equal in duration to the first time interval.

Abstract: A continuous parallel Viterbi decoder configured to (a) compute Trellis paths from an input bitstream encoded with a convolutional code, (b) backtrack the Trellis paths to generate an output signal, (c) store the Trellis paths in a shared memory, and (d) coordinate simultaneous read/write operations from and to the shared memory.

Abstract: Systems, circuits, devices and/or methods related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit having a data detection circuit is disclosed that includes: a scaling circuit, a soft output calculation circuit, and a factor calculation circuit. The scaling circuit is operable to scale a branch metric value by a scaling factor to yield a scaled output. The soft output calculation circuit is operable to calculate a soft output based at least in part on the scaled output. The factor calculation circuit operable to modify the scaling factor based at least in part on the soft output.

Abstract: A decoding apparatus and method for estimating a reliability value by detecting uncorrected packet errors. The decoding apparatus includes a hard-decision unit and a reliability determination unit. The hard-decision unit performs hard-decision on a soft-input of a code. The reliability determination unit generates a reliability estimation value of the hard-decision result according to whether a packet error exists in the hard-decision result. The hard-decision unit performs hard-decision in response to the reliability estimation value.

Abstract: In one embodiment, a circular pipeline processing system is provided. The system includes a plurality of processing stages configured to operate in a circular pipeline. Each processing stage is configured to output a fully processed data block in response to completing a final processing iteration, and otherwise, store a partially processed data block in a memory buffer of the processing stage. Each processing stage is configured to select between an unprocessed data block and a partially processed data block from the memory buffer of a preceding processing stage, based on one or more of availability of memory sufficient for storage of an unprocessed data block or availability of a partially processed data block. The processing stage is configured to process the selected data block.

Abstract: A plurality of metrics associated with a plurality of partially decoded codewords is obtained. The plurality of partially decoded codewords has been processed at least once by a first soft output decoder and a second soft output decoder and the plurality of partially decoded codewords is stored in a memory. At least one of the plurality of partially decoded codewords is selected based at least in part on the plurality of metrics; the memory is instructed to vacate the at least one selected codeword.

Abstract: Various embodiments of the present invention provide systems and methods for media defect detection. For example, a data transfer system is disclosed that includes a data detector, a defect detector and a gating circuit. The data detector provides a soft output, and the defect detector is operable to receive the soft output and the data signal, and to assert a defect indication based at least in part on the soft output and the data signal. The gating circuit is operable to modify the soft output of the detector whenever the defect indication is asserted.

Abstract: Disclosed is a method for selecting a design option for a Viterbi decoder model. In some embodiments, the method includes deriving a set of design options for a Viterbi decoder model by differentiating at least one design parameter, where the at least one design parameter comprises at least a first value for a look-ahead parameter. The method further includes performing an evaluation of each design option in the set of design options in a multi-dimensional design space and, based on the evaluation of each design option, selecting a design option in the set of design options that (i) satisfies a predetermined energy efficiency constraint and (ii) yields at least a second value for the look-ahead parameter, wherein the second value is greater than the first value and satisfies a predetermined area budget.

Abstract: Systems, methods, devices, circuits for data processing, and more particularly to data processing including operational marginalization capability, and/or operational improvement capability.