Abstract: A memory system comprises a non-volatile memory device that stores user data and state information regarding the user data. In a read operation of the non-volatile memory device, a memory controller calculates a priori probabilities for the user data based on the state information, calculates a posteriori probabilities based on the a priori probabilities, and performs a soft-decision operation to determine values of the user data based on the a posteriori probabilities.

Abstract: A method of detecting interference in a received sample vector using hidden Markov modelling by first estimating noise variance, where estimating noise variance comprises the steps of receiving a sample vector of noise and interference, sorting the sample vector in the frequency domain by order of increasing magnitude to produce an ordered vector, finding a sub-vector of the ordered vector that minimizes the distance from a noise measure, and estimating the noise variance.

Abstract: In an aspect, in general, a forward error correction algorithm (FEC) utilizes an FEC block structure in a manner that extends the effective error correction such that it can approach an “infinite” length to obtain benefits typical of very large FEC block size without the commensurate computation cost.

Abstract: A method and apparatus for performing demapping in a wireless communication system utilizing a modulo operation are disclosed. The demapping method of a receiver in a wireless communication system includes receiving an input signal and first information indicating whether a first modulo operation is performed on the input signal from a transmitter; if the first information indicates execution of the first modulo operation, performing a second modulo operation of the input signal, and acquiring a reception signal; generating a maximum function value having a highest probability that the reception signal corresponds to a candidate constellation point of an extended constellation; and generating a log-likelihood ratio (LLR) using the generated maximum function value.

Abstract: An extensive use of look-up table (LUT) and single instruction multiple data (SIMD) in different algorithms in a software-defined radio (SDR) system is described. In particular, the LUT is used during spreading modulation, mapping and spreading, scrambling, de-scrambling, soft demapping, and the like. The SIMD is executed by a multi-core processor during implementation of a “min” operation to find an optimal path in a Trellis diagram for a Viterbi decoder.

Abstract: A Viterbi decoder which is based on a special instruction set implemented in the processor, enabling it to handle the Viterbi processing with a much lower CPU loading without significantly increasing the hardware complexity. By careful application of appropriate design constraints specific to the SV navigation and analysis of the Viterbi algorithm an optimised architecture can be realized for embedding Viterbi acceleration logic efficiently into a GNSS chipset.

Abstract: A method of data classification for use in a wireless communication system includes obtaining decoder metrics from a decoder. The decoder metrics correspond to data generated by the decoder. The decoder metrics include a symbol error rate (SER) and an energy metric (EM). The method also includes classifying the data into a first category if the data fails a cyclic redundancy check (CRC) check, into a second category if the data passes the CRC check and is determined to be unreliable, or into a third category if the data passes the CRC check and is determined to be reliable. A reliability of the data is determined based on the decoder metrics and an EM threshold.

Abstract: Systems and methods for processing and decoding TCM/BCM-coded signal vectors. A multi-dimensional signal vector is received by, for example, a TCM or BCM decoder. The TCM/BCM decoder identifies the closest signal points in the signal constellation set, or “nearest neighbors,” for each dimension of the received signal vector. The TCM/BCM decoder then forms a test set that includes a plurality of multi-dimensional test vectors, where each dimension of each test vector is based on an identified nearest neighbor. In particular, each test point in the test set is based on a different combination of the nearest neighbors. The TCM/BCM decoder can compute branch metrics based on only the test points in the test set, and can make detection decisions using the computed branch metrics.

Abstract: A method and system for a sequence estimation in a receiver, such as for use when receiving a sample of a received inter-symbol correlated (ISC) signal corresponding to a transmitted vector of L symbols, with L being a integer greater than 1, and with symbol L being a most-recent symbol and symbol 1 being least recent symbol of the vector. A plurality of candidate vectors may be generated, wherein element L-m of each candidate vector holding one of a plurality of possible values of the symbol L-m, with m is an integer greater than or equal to 1, and elements L-m+1 through L of each candidate vectors holding determined filler values. A plurality of metrics may be generated based on the plurality of candidate vectors, and based on the generated plurality of metrics, a best one of the possible values of the symbol L-m may be selected.

Abstract: Methods and apparatus are provided for processing a plurality of data blocks. In accordance with embodiments of the invention, a correction flag for each of the data blocks can be received, along with information on at least one error event for each of the data blocks. Using this received information, a search trellis corresponding to the data blocks can be determined. Determining the search trellis can include determining a plurality of branches and computing a branch metric for each of the branches. A search on the search trellis can be performed to identify at most one error event for each data block, where the search is based on the branch metrics.

Abstract: Multiple data permutation operations in respective different dimensions are used to provide an overall effective data permutation using smaller blocks of data in each permutation than would be used in directly implementing the overall permutation in a single permutation operation. Data that has been permuted in one permutation operation is block interleaved, and the interleaved data is then permuted in a subsequent permutation operation. A matrix transpose is one example of block interleaving that could be applied between permutation operations.

Abstract: Various embodiments of the present invention provide systems and methods for evaluating and debugging a data decoder. For example, a data decoder circuit is discussed that includes an input memory, a data decoder operable to decode data from the input memory in one or more iterations, an output memory operable to store decoded data from the data decoder, and a test port operable to provide access to the input memory, the data decoder and the output memory.

Abstract: A MAP decoder may be implemented in parallel. In one implementation, a device may receive an input array that represents received encoded data and calculate, in parallel, a series of transition matrices from the input array. The device may further calculate, in parallel, products of the cumulative products of the series of transition matrices and an initialization vector. The device may further calculate, in parallel and based on the products of the cumulative products of the series of transition matrices and the initialization vector, an output array that corresponds to a decoded version of the received encoded data in the input array.

Abstract: A digital broadcasting receiving system and method, where the digital broadcasting receiving system includes: a demodulator receiving and demodulating a dual transmission stream including a turbo stream and a normal stream; an equalizer equalizing the demodulated dual transmission stream; a first processor restoring normal stream data from the equalized dual transmission stream; and a second processor restoring turbo stream data from the equalized dual transmission stream and eraser decoding the turbo stream data. Thus, the reception sensitivity of a transmission stream including a turbo stream can be improved.

Abstract: Systems and techniques to interpret signals on a noisy channel are described. A described technique includes storing a group of signals including a filtered digital signal and one or more previous signals, the filtered digital signal being based on an analog signal; interpreting the filtered digital signal as first discrete values; determining whether the first discrete values are adequately indicated based on a result of the interpreting; initiating a retry mode when the first discrete values are not adequately indicated; producing, in the retry mode, a new signal, the new signal being determined based on an average of at least a portion of the group of signals; interpreting, in the retry mode, the new signal as second discrete values; and determining whether the second discrete values are adequately indicated based on hard decisions indicated by the new signal and hard decisions indicated by the filtered digital signal.

Abstract: The present disclosure describes a method, performed by a data processor comprising a cyclic redundancy check (CRC) module configured for calculating CRC remainders for encoded data and a comparator comprising a shift register, for making a cyclic redundancy check of an encoded data record of bit length L, in which at least A bits of the record represent content data and at least B bits represent check data. A system for performing a cyclic redundancy check is also described.

Abstract: A system and method for Viterbi decoding utilizes a general purpose processor with application specific extensions to perform Viterbi decoding operations specified in a Viterbi decoding algorithm stored in memory.

Abstract: There is provided a communication apparatus, including a transmission pattern generation unit that generates a transmission pattern according to a modulation method, a metric calculation unit that calculates an inter-signal distance between a received signal vector of received signals and an estimation vector, which is a product of channel information and the transmission pattern, a maximum likelihood pattern determination unit that determines a maximum likelihood signal pattern from the inter-signal distance calculated by the metric calculation unit, and an error estimation unit that estimates a phase error component and an amplitude error component contained in the received signal vector. The metric calculation unit calculates the inter-signal distance between the received signal vector and the estimation vector by using the phase error component and/or the amplitude error component estimated by the error estimation unit.

Abstract: The various embodiments provide circuitry and methods for packing Log Likelihood Ratio (“LLR”) values into a buffer memory in a compressed format which reduces the amount of buffer memory required. Various embodiments use a type of quantization which reduces the bit width of the LLR values that are stored, with the particular level of quantization depending upon the code rate of the data. The degree, pattern, and periodicity of bit width compression employed may depend upon the code rate of the received transmission. Bit width patterns use for LLR value quantization may be generated by a shift register circuit which provides an efficient mechanism for controlling an LLR packer circuit based upon the code rate of the received signal.

Abstract: A system is used to predict when a decoding process will fail to correct an error burst within a transmission. A decoder receives an input bit stream and processes it to produce an output bit stream, which is convolutionally encoded. K-bits of the convolutionally encoded output bit stream are compared with a corresponding k-bits of a delayed version of the input bit stream, with the k-bits starting at a first bit and ending at first bit+k. For each bit of the k-bits in the convolutionally encoded output bit stream and in the corresponding k-bits of the delayed version of the input bit stream, a number of conflicting bits and whether the number of conflicting bits exceeds a threshold number of conflicting bits is determined. The output bit stream is sent to a block decoding component for decoding with the bits marked for erasure.

Abstract: Decoders and communications devices including such decoders can obtain a convolutional coded bit stream including a plurality of coded data bits. The convolutional coded bit stream may be coded according to one or more generator polynomials such that each information bit is related to two or more coded data bits in a manner to be determinable from a mathematical combination of the two or more coded data bits of the convolutional coded bit stream. A priori information associated with each information bit can be calculated based at least in part on the mathematical combination of the two or more coded data bits. Employing the a priori information, a binary value for each information bit can be calculated. Other aspects, embodiments, and features are also claimed and described.

Abstract: A method for soft remodulation in a receiver of transmissions over a wireless telecommunication system, the method including obtaining from a FEC decoder a-posteriori LLR values, converting the a-posteriori LLR values into bit probabilities and computing improved soft symbols estimates as expected values using the bit probabilities in a recursive algorithm. Preferably, the step of converting is implemented using a pre-computed Look Up Table (LUT). Preferably, the step of computing is implemented in a Multiplier-Accumulator having a SIMD structure.

Abstract: Various embodiments of the present invention provide systems and methods for updating detector parameters in a data processing circuit. For example, a data processing circuit is disclosed that includes a first detector circuit, a second detector circuit, and a calibration circuit. The first detector circuit is operable to receive a first data set and to apply a data detection algorithm to the first data set, and the second detector circuit is operable to receive a second data set and to apply the data detection algorithm to the second data set. The calibration circuit is operable to calculate a data detection parameter based upon a third data set. The data detection parameter is used by the first detector circuit in applying the data detection algorithm to the first data set during a period that the data detection parameter is used by the second detector circuit in applying the data detection algorithm to the second data set.

Abstract: A method of data classification for use in a wireless communication system includes obtaining decoder metrics from a decoder. The decoder metrics correspond to data generated by the decoder. The decoder metrics include a first metric and a second metric. The method also includes classifying the data into a first category if the data fails an error detection check, into a second category if the data passes the error detection check and is determined to be unreliable, or into a third category if the data passes the error detection check and is determined to be reliable. A reliability of the data is determined based on at least one of the decoder metrics and a threshold.

Abstract: Systems and methods are provided for generating error events for decoded bits using a Soft output Viterbi algorithm (SOVA). A winning path through a trellis can be determined and decoded information can be generated. Path metric differences can be computed within the trellis based on the winning path. A plurality of error event masks and error event metrics can be generated based on the decoded information and the path metric differences.

Abstract: Decoding is performed on input data to obtain first decoded data using a first error correction decoder. If decoding by a second error correction decoder on the first decoded data fails, decoding is performed using an output of the second decoder and using the first decoder. A reservation request is sent from the second error correction decoder to a memory prior to completion of the decoding on the first decoded data. Space is reserved in the memory in response to receiving the reservation request from the second decoder.

Abstract: Turbo decoder employing ARP (almost regular permutation) interleave and arbitrary number of decoding processors. A novel approach is presented herein by which an arbitrarily selected number (M) of decoding processors (e.g., a plurality of parallel implemented turbo decoders) be employed to perform decoding of a turbo coded signal while still using a selected embodiment of an ARP (almost regular permutation) interleave. The desired number of decoding processors is selected, and very slight modification of an information block (thereby generating a virtual information block) is made to accommodate that virtual information block across all of the decoding processors during all decoding cycles except some dummy decoding cycles. In addition, contention-free memory mapping is provided between the decoding processors (e.g., a plurality of turbo decoders) and memory banks (e.g., a plurality of memories).

Abstract: A Software Defined Radio (SDR) subsystem capable of supporting a multiple communication standards and platforms for modulation, demodulation and trans-modulation of an input signal is provided. The SDR subsystem includes a Signal Conditioning Cluster (SCC) unit that includes a signal conditioning CPU adapted for sample based signal processing, a Signal Processing Cluster (SPC) unit that includes a signal processing CPU adapted for block based signal processing, and a Channel Codec Cluster (CCC) unit that performs a channel encoding or a channel decoding operation.

Abstract: A set of one or more receiver parameters is adjusted. It is determined whether to adjust the set of receiver parameters. In the event it is determined to adjust the set of receiver parameters, a new set of values is generated for the set of receiver parameters using a cost function (where the cost function does not assume a noise signal in a receive signal to have a particular statistical distribution) and the set of receiver parameters is changed to have the new set of values.

Abstract: A receiver of a wireless communication system and method thereof include antennas configured to receive data, wherein the data comprises a preamble, a header, and a payload. The receiver also includes a synchronizer configured to perform time synchronization of the data received through corresponding paths of each antenna using corresponding preambles of the data. The receiver includes a header detector configured to detect a header from the data of each of the paths. A surviving path selector in the receiver is configured to select a signal of a surviving path from among the paths based on the header or the preamble. The receiver also includes combiner configured to combine the signal existing in the surviving path to demodulate the payload.

Abstract: Various embodiments relate to a storage unit and a related method in a Viterbi decoder for decoding a binary convolutional code with power efficiency. A storage unit for storing survivor paths may use a register exchange method to append additional information received from an add-compare-select unit onto the end of the survivor path. An exemplary method produces a prediction path after a specified depth in the survivor path processing history and subtracts the prediction path from the survivor path. This may cause a majority of bits that comprise the survivor path to be converted to a low-energy bit, such as a logical “0”. During subsequent copies of a differential survivor path using the register exchange method, less energy is consumed when copying the entire survivor path, as a majority of the bits in the survivor paths are a logical “0”.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. A data processing circuit is disclosed that includes: a data detector circuit, a first symbol constrained arrangement circuit, and a second symbol constrained arrangement circuit. The data detector circuit is operable to apply a data detection algorithm to a combination of a first input data set and a decoded data set to yield a detected output that includes a number of non-binary symbols. The first symbol constrained arrangement circuit is operable to receive the detected output and to re-arrange the detected output in accordance with a first arrangement algorithm to yield a re-arranged output. The bits for at least one non-binary symbol from the detected output are maintained together in the re-arranged output.

Abstract: Methods and apparatuses for enhanced processing of received channels in a mobile communications system is described. Particularly, convolutionally encoded tail biting data in a mobile communications system is efficiently decoding by replicating the received encoded signal N times, where N equals a number of iterations. A Viterbi decoding algorithm is applied and a most likely survivor path is obtained. The ensuing decoding window is set as a fixed decoding window and placed at a mid-section of the most likely survivor path. Simulations have shown codeword accuracy to be comparable to MLSE with less complexity. A high degree of accuracy has been obtained for N=3.

Abstract: A low complexity List Viterbi algorithm (LVA) for decoding tail biting convolutional codes (TBCCs) has lower complexity than a solution of running the LVA algorithm for all states. In one aspect, a low complexity LVA-TBCC process includes finding a list of states from a single Viterbi algorithm and finding a list of potential codewords for each state in the state list using the LVA. A cyclic redundancy check may prune out false solutions. The disclosed method may be applied to many communication systems to improve error performance similar to LTE downlink PBCH decoding enhancements.

Abstract: In a symbol mapping method, transmission data is encoded to generate information bits and redundancy bits. An average LLR value of bits on which the information bits are mapped is different from an average LLR value of bits on which the redundancy bits are mapped.

Abstract: The claimed subject matter relates to encoding and decoding information in a wireless communication system using soft-demodulation and interleaving of concatenated code received in a strip channel. A set of symbols is received containing a plurality of information bits, dividing the received set of symbols into a plurality of subsets of symbols, each subset corresponding to the input of an inner code demodulation selecting a set of initial a priori values of the inner code demodulation for each subset of symbols, and demodulating each subset of symbols, using the initial a priori values of the subset of symbols and an inner code generator matrix, to generate a plurality of first soft information values as the output of the inner code demodulation.

Abstract: An embodiment of the invention includes an efficient error-control system and method for recovering packet losses, especially losses in distributing multicast video over broadband residential networks. Preferably, unlike most existing error-control algorithms designed for Internet multicast, the system and method does not employ substantial feedback suppression. Preferably, the system and method does not employ substantial multicasted retransmission. Preferably, the system and method does not employ substantial parity retransmission. Preferably, the system and method does not employ substantial local loss recovery. The system and method integrates two existing classes of error-control algorithms: Automatic Repeat Request (ARQ) and Forward Error Correction (FEC), to reduce traffic overhead and achieve scalability.

Abstract: Methods and apparatuses for combining error coding and modulation schemes are described herein. One or more methods include encoding data using linear error correcting code, modulating the encoded data, writing the modulated data to memory, and decoding the written data using a Viterbi algorithm and a linear error correcting code decoder.

Abstract: A network coding method includes receiving a plurality of message packets each having a packet length. Encoding the plurality of message packets by applying a convolutional code across symbols in corresponding positions of the plurality of message packets obtaining a number of encoded packets. The number of encoded packets obtained being more than the number of message packets.

Abstract: A method for searching for an input symbol string, includes receiving (B) an input symbol string, proceeding (C) in a trie data structure to a calculation point indicated by the next symbol, calculating (D) distances at the calculation point, selecting (E) repeatedly the next branch to follow (C) to the next calculation point to repeat the calculation (D). After the calculation (G), selecting the symbol string having the shortest distance to the input symbol string on the basis of the performed calculations. To minimize the number of calculations, not only the distances are calculated (D) at the calculation points, but also the smallest possible length difference corresponding to each distance, and on the basis of each distance and corresponding length difference a reference value is calculated, and the branch is selected (E) in such a manner that next the routine proceeds from the calculation point producing the lowest reference value.

Abstract: The present disclosure includes apparatus, systems and techniques relating to iterative decoder memory arrangement. A described apparatus includes a single R memory component including R banks, a Q memory component including Q banks, a channel detector memory component to store channel extrinsic information associated with current and previous codewords, and an iterative decoder communicatively coupled with the single R memory component, the Q memory component, and the channel detector memory component. The apparatus can be configured to alternate among the R banks for storing R data associated with a current codeword. The apparatus can be configured to alternate among the Q banks for storing Q data associated with a current codeword.

Abstract: Systems and methods for out of order memory management.

Abstract: In a multicarrier wireless communication system adopting forward error correction codes, a reception method adapted to a receiver 1 receiving wireless signals is constituted of an interference band detection process for selecting a sub-carrier having low reliability among a plurality of sub-carriers of desired waves as a specific sub-carrier, a weight coefficient generation process for generating weight coefficients for reducing reliability in sub-carriers with respect to the selected specific sub-carrier, a demodulation process for demodulating received wireless signals of sub-carriers, a weighted calculation process for performing weighted calculation applying weight coefficients to demodulated values of sub-carriers of wireless signals, and a decoding process for performing a decoding process for error correction on values calculated of sub-carriers.

Abstract: Techniques are provided for transmitting and receiving a mother code in an incremental redundancy hybrid automatic repeat-request protocol. Each bit position of the mother code may be mapped to an output symbol, and each output symbol may be mapped to an antenna for transmission. One or more transmissions of symbols contained in the output symbols may be performed, where each transmission may include puncturing the mother code by selecting one or more symbols from the of output symbols, and transmitting each symbol in the one or more symbols on an antenna corresponding to that symbol. The mother code may be decoded, in part, by determining combinable bits contained within a set of received symbols, and computing one or more log-likelihood ratio values corresponding to each symbol in the set of received symbols.

Abstract: An analog-digital conversion system comprising at least one variable gain amplifier amplifying an input signal e, an analog-digital converter CAN digitizing said signal e, an interference-suppressing digital processing module, processing the digitized signal, also comprises a first automatic gain control AGC loop, called the analog AGC loop, that compares an estimate of the output power of the CAN converter with a control setpoint g1 called the control setpoint of the analog AGC loop, a gain ga used to control the variable gain amplifier being deduced from this comparison. The system also comprises a second automatic gain control AGC loop called the digital loop, said digital loop comparing an estimate of the power after the interference-suppressing digital processing with a predetermined control setpoint gn, the analog AGC loop being controlled by a control setpoint deduced from this comparison.

Abstract: A multi-channel sequential Viterbi decoder includes: an input buffer, a “Read Data from Input Buffer” signal driver, a processing unit selector, a decoder channel parameters registers unit, a processing unit for a “Reset Path Metrics” command, a processing unit for a “Set Path Metric Value for the Given Path Number” command, a processing unit for a “Get Single Bit from the Path with Given Number” command, a processing unit for a “Process Input Samples” command, a memory for storing decoding paths and path metrics, a unit for generating an address for the memory, and data buffers for decoder channels output.

Abstract: The device is used for decoding convolution-encoded reception symbols. In this context, transmission data are modulated with a modulation scheme to form symbols, which are encoded with a transmission filter to form convolution-encoded transmission symbols. A convolution-encoded transmission symbol contains components of several symbols arranged in time succession. These transmission symbols are transmitted via a transmission channel and received as reception symbols. The Viterbi decoder decodes the reception symbols by use of a modified Viterbi algorithm. Before running through the Viterbi decoder, the reception symbols are processed by a state-reduction device, which determines additional items of information relating to possible consequential states of the decoding independently of the decoding through the Viterbi decoder in every state of the decoding. The state-reduction device uses the additional items of information to restrict the decoding through the Viterbi decoder to given consequential states.

Abstract: A decoding method for determining a preferred survivor path in a decoding process is provided. The method includes calculating a first determination value of a first survivor path at a first time point, the first determination value being determined by a first sub determination value and a second determination value at a second time point, and the second time point being prior to the first time point; calculating a third determination value of a second survivor path at the first time point, the third determination value being determined by a second sub determination value and a fourth determination value at the second time point; and when a difference between the first determination value and the third determination value is equal to or less than a predetermined value, determining the preferred survivor path at the first time point according to the second and the fourth determination values, or the first and the second sub determination values.

Abstract: A method of detecting received data in a communication system includes the steps of: performing a QR decomposition on a received input vector as a function of one or more characteristics of a communication channel over which the input vector was transmitted; generating a subset of best symbol candidates from a symbol constellation by comparing an input sample (corresponding to an element of the input vector) with one or more prescribed thresholds; identifying at least one symbol satisfying prescribed minimum Euclidian distance criteria among multiple ambiguity symbols in the subset of best symbol candidates; and generating a subset of best symbols including a prescribed number of symbols from the symbol constellation determined to be closest to the input sample. The subset of best symbols is used in a subsequent iteration of the steps of generating the subset of best symbol candidates and identifying at least one symbol satisfying the prescribed minimum Euclidian distance criteria.

Abstract: A reliability unit is provided for determining a reliability value for at least one bit decision. The disclosed reliability unit comprises one or more functional elements, wherein each of the functional elements comprises at least four functional units and at least two registers, wherein each functional unit comprises a comparator and a multiplexer, and wherein an output of the comparator and an equivalence bit control the multiplexer. Generally, the reliability unit determines a reliability value for a bit decision associated with a maximum-likelihood path through a multiple-step trellis.