Abstract: A detector recovers servo data from a servo signal generated by a read-write head, and determines the head-connection polarity from the recovered servo data. Such a detector allows a servo circuit to compensate for a reversed-connected read-write head, and thus allows a manufacturer to forego time-consuming and costly testing to determine whether the head is correctly connected to the servo circuit.

Abstract: The invention which relates to a method and to an arrangement for generating soft bit information in a receiver of a multiple antenna system is based on the object of reducing the calculation complexity for generating the soft bit information.

Abstract: A survivor path memory is provided for a Viterbi detector. The survivor path memory comprises a plurality of columns, each associated with a different time step, and an input processor. Each column comprises a flip flop for storing one bit or portion of a bit sequence associated with a Viterbi state; and a multiplexer for each state controlled by a case signal indicating a time step, the multiplexer selecting a state from a previous time step, wherein an output of the multiplexer of a given state is connected to at least one data input of a flip flop of the given state. The input processor generates a control signal that exchanges one or more pointers based on a trellis structure, wherein each of the pointers points to one of the flip flops.

Abstract: A method of generating a set of generator polynomials for use as a tail biting convolution code to operate on data transmitted over a channel comprises: (1) selecting valid combinations of generator polynomials to include in a pool of potential codes, each valid combination being a potential code; (2) determining first lines of a weight spectrum for each potential code in the pool and including potential codes of the pool having best first lines in a candidate set; (3) determining best codes of the candidate set based on the first L number of lines in the weight spectrum; (4) selecting an optimum code(s) from the best codes; and (5) configuring a shift register circuit(s) of a data transceiver to implement the optimum code(s).

Abstract: Outputting information for recovering a sequence of data is disclosed. Outputting includes making a decision that selects a first sequence of states corresponding to a surviving path, determining a second sequence of states corresponding to a non-surviving path associated with the decision, and defining a possible error event based at least in part on the second sequence of states.

Abstract: A soft output Viterbi algorithm (SOVA) decoder arranged to decode symbols received over a transmission channel, the symbols indicating a state transition between two states of a plurality of states that determines a decoded data value, the SOVA decoder comprising a reliability memory unit including at least four stages of logic units, each logic unit including a single buffer and at least four stages including a plurality of full stages comprising a separate logic unit corresponding to each of the plurality of states; and a plurality of compact stages including half or less than half the number of logic units than the number of the plurality of states, each logic unit corresponding to two of the plurality of states.

Abstract: A receiver of a digital signal equipped with an N-state weighted-decision trellis Viterbi decoder, the signal received including a series of symbols, is provided. The receiver comprises a programmable logic circuit that includes a source memory A and a destination memory B each comprising N rows and M+L columns respectively allocated to M fixed fields for describing the trellis, and to L variable fields, and an operator able to calculate the variable fields of a memory as a function of the fixed fields of the said memory, of the symbols received and of the variable fields of the other memory and able to reverse the role of the source memory and destination memory.

Abstract: A testbed for testing health of software includes an input model, a hardware model, and a resource modeler. The input model represents an input system used in conjunction with the software. The hardware model represents one or more hardware components used in conjunction with the software. The resource modeler is coupled to the input model and the hardware model, and is configured to estimate effects on the software of conditions of the hardware components, the input system, or both.

Abstract: Systems and techniques to interpret signals on a noisy channel. A described system includes a filter, buffer, detector, controller, and averager. The buffer can store a group of signals, including a filtered digital signal and previous signal(s). The controller can determine whether first discrete values are adequately indicated and initiate a retry mode when the first discrete values are not adequately indicated. The averager can produce a new signal, in the retry mode, based on an average of at least a portion of the group of signals. The detector can interpret the new signal as second discrete values. The controller can determine whether the second discrete values are adequately indicated based on a measurement of differences between hard decisions indicated by the new signal and hard decisions indicated by the filtered digital signal. The controller can selectively exclude a signal of the group of signals from the average.

Abstract: A method and system of decoding a ccnvolutionally encoded data block having known padding bits. A Viterbi decoder is constrained to a state corresponding to k?1 padding bits immediately adjacent to data bits of the data block, where k is a constraint length of a convolution encoder used to encode the data block. Symbols of the encoded data block that have influence only from the padding bits are discarded.

Abstract: Various embodiments of the present invention provide systems and methods for out of order memory management. For example, a method for out of order data processing is disclosed. The method includes providing an out of order codeword memory circuit that includes a number of codeword memory locations in a codeword memory area and the same number of index values in an index area. Each of the index values corresponds to a respective one of the codeword memory locations. The methods further include receiving a data set; storing the data set to one of the codeword memory locations; receiving an indication that the data set stored in the one of the codeword memory locations has completed processing; and grouping an index value corresponding to the one of the codeword memory locations with one or more other index values corresponding to unused codeword memory locations.

Abstract: Good transmission characteristics are achieved in the presence of fading with a transmitter that employs a trellis coder followed by a block coder. Correspondingly, the receiver comprises a Viterbi decoder followed by a block decoder. Advantageously, the block coder and decoder employ time-space diversity coding which, illustratively, employs two transmitter antennas and one receiver antenna.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is disclosed that includes first and second data detectors and an error cancellation circuit. The first data detector is operable to perform a data detection process on a first signal derived from a data input to yield a detected output. The second data detector circuit is operable to perform a data detection process on a second signal derived from the data input to yield a second detected output. The error cancellation circuit is operable to combine a first error signal derived from the detected output with a second error signal derived from the second detected output to yield a feedback signal. The feedback signal is operable to modify the data input during a subsequent period.

Abstract: In one embodiment, device for early stopping in turbo decoding includes a processor configured to receive a block of data to be decoded, compare hard decision bits resulting from decoding iterations and compare a minimum value of log likelihood ratio (LLR) of decoded bits against a threshold. The processor configured to match hard-decisions with previous iteration results. The processor may be configured to set an early stop rule after the matching hard-decisions with previous iteration results is matched. The processor may be configured to set an early stop rule when the minimum reliability of the output bits exceeds the threshold.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. A data processing circuit is disclosed that includes: a data detector circuit, a first symbol constrained arrangement circuit, and a second symbol constrained arrangement circuit. The data detector circuit is operable to apply a data detection algorithm to a combination of a first input data set and a decoded data set to yield a detected output that includes a number of non-binary symbols. The first symbol constrained arrangement circuit is operable to receive the detected output and to re-arrange the detected output in accordance with a first arrangement algorithm to yield a re-arranged output. The bits for at least one non-binary symbol from the detected output are maintained together in the re-arranged output.

Abstract: A Viterbi trellis processing technique in which soft decisions and hard decisions are derived from a received signal and the soft decisions are enhanced by being modified using the hard decisions. A log likelihood ratio for a bit of the received signal can be derived by grouping candidate metrics associated with the decision that the bit has a first state, grouping candidate metrics associated with the decision that the bit has a second state, applying respective functions to the groups and calculating the difference of the function values.

Abstract: Techniques are provided for iteratively decoding data recorded on a data storage device. An iterative decoder decodes the data using multiple decoding iterations to correct errors. In multiple iterations of the iterative decoder, a post processing block generates soft information, and a decoder applies a minimum sum decoding algorithm to a low density parity check (LDPC) code to generate extrinsic information based on the soft information and updated soft information.

Abstract: Viterbi decoding may be performed on a microcontroller by initializing a state-metric array by executing load instructions to load state-metric data from a memory module into a set of registers in the microcontroller. Butterfly processing on the state-metric array is performed by executing Viterbi processing instructions fetched from a program storage module to manipulate the state-metric (SM) data in the set of registers for each Viterbi butterfly in a stage of Viterbi decoding to form a final set of state-metric data and trace bits. After completing each stage, a final set of state-metric data may be stored in the memory module by executing store instructions.

Abstract: A method of data classification for use in a wireless communication system includes obtaining decoder metrics from a decoder. The decoder metrics correspond to data generated by the decoder. The decoder metrics include a first metric and a second metric. The method also includes classifying the data into a first category if the data fails an error detection check, into a second category if the data passes the error detection check and is determined to be unreliable, or into a third category if the data passes the error detection check and is determined to be reliable. A reliability of the data is determined based on at least one of the decoder metrics and a threshold.

Abstract: Herein described is a system and a method of detecting and correcting data bit errors using a sequence of one or more codewords transmitted through a communication channel without intersymbol interference. Each of the one or more codewords incorporates or encodes one or more parity bits. The codewords are processed by a Non-ISI Meta-Viterbi detector that utilizes a Meta-Viterbi algorithm. The Non-ISI Meta-Viterbi detector comprises an event weight processor, a computational circuitry, a parity syndrome calculator, and an error correction circuitry. The Non-ISI Meta-Viterbi detector receives an output generated from a symbol detector and processes the received output using a trellis having 2t states. In a representative embodiment, the Non-ISI Meta-Viterbi detector performs ?+2t2t add, compare, and select operations.

Abstract: A Viterbi decoder includes: an observation vector sequence generator for generating an observation vector sequence by converting an input speech to a sequence of observation vectors; a local optimal state calculator for obtaining a partial state sequence having a maximum similarity up to a current observation vector as an optimal state; an observation probability calculator for obtaining, as a current observation probability, a probability for observing the current observation vector in the optimal state; a buffer for storing therein a specific number of previous observation probabilities; a non-linear filter for calculating a filtered probability by using the previous observation probabilities stored in the buffer and the current observation probability; and a maximum likelihood calculator for calculating a partial maximum likelihood by using the filtered probability.

Abstract: A method for decoding an encoded message is described. The method includes obtaining a set of metrics which includes first and second state metrics, and first and second branch metrics. First and second offset values for the iteration are obtained. The first state and branch metrics are added together to obtain a first partial result. The second state and branch metrics are added together to obtain a second partial result. The second partial result is subtracted from the first partial result to obtain a difference. The first partial result and the first offset value are added together to obtain a first result. The second partial result and the second offset value are added together to obtain a second result. Either the first result or the second result is selected for output responsive to the difference. A log correction term is selected responsive to the difference.

Abstract: Described herein are system(s) and method(s) for routing data in a parallel Turbo decoder. Aspects of the present invention address the need for reducing the physical circuit area, power consumption, and/or latency of parallel Turbo decoders. According to certain aspects of the present invention, address routing-networks may be eliminated, thereby reducing circuit area and power consumption. According to other aspects of the present invention, address generation may be moved from the processors to dedicated address generation modules, thereby decreasing connectivity overhead and latency.

Abstract: Systems and methods for processing and decoding TCM/BCM-coded signal vectors. A multi-dimensional signal vector is received by, for example, a TCM or BCM decoder. The TCM/BCM decoder identifies the closest signal points in the signal constellation set, or “nearest neighbors,” for each dimension of the received signal vector. The TCM/BCM decoder then forms a test set that includes a plurality of multi-dimensional test vectors, where each dimension of each test vector is based on an identified nearest neighbor. In particular, each test point in the test set is based on a different combination of the nearest neighbors. The TCM/BCM decoder can compute branch metrics based on only the test points in the test set, and can make detection decisions using the computed branch metrics.

Abstract: A communication device configured to perform packet reception processing, with the header of a packet including a header sequence and a Reed-Solomon code, includes: a header check sequence inspecting unit configured to detect, based on the header check sequence included in a received packet header, an error of the header; a Reed-Solomon encoding unit configured to encode the header of a received packet other than the Reed-Solomon code to generate a Reed-Solomon code; a Reed-Solomon code inspecting unit configured to detect whether or not the Reed-Solomon code generated by the Reed-Solomon encoding unit is completely identical to the Reed-Solomon code within the received packet header; and a processing control unit configured to control payload processing of a received packet in accordance with the inspection results of the header check sequence inspecting unit and the Reed-Solomon code inspecting unit.

Abstract: Apparatus and methods store data in a non-volatile solid state memory device according to a rate-compatible code, such as a rate-compatible convolutional code (RPCC). An example of such a memory device is a flash memory device. Data can initially be block encoded for error correction and detection. The block-coded data can be further convolutionally encoded. Convolutional-coded data can be punctured and stored in the memory device. The puncturing decreases the amount of memory used to store the data. Depending on conditions, the amount of puncturing can vary from no puncturing to a relatively high amount of puncturing to vary the amount of additional error correction provided and memory used. The punctured data can be decoded when data is to be read from the memory device.

Abstract: A channel adaptive iterative turbo decoder for computing with MAP decoders a set of branch metrics for a window of received data, computing the forward and reverse recursive path state metrics and computing from the forward and reverse recursive path state metrics the log likelihood ratio for 1 and 0 and interleaving the decision bits; and identifying those MAP decoder decision bits which are non-convergent, computing a set of branch metrics for the received data, computing from the forward and reverse recursive path state metrics the log likelihood ratio (LLR) for 1 and 0 for each non-converged decision bit and interleaving the non-convergent decision bits.

Abstract: A path comparison unit is disclosed for determining paths in a trellis that compete with a survivor path. The disclosed path comparison unit comprises a first type functional unit comprising a multiplexer and a register to store one or more survivor bits associated with the survivor path; and at least two second type functional units, wherein each second type functional unit comprises a multiplexer and a logical circuit to compute at least one equivalence bit indicating whether the bit for a respective path and the bit for the survivor path are equivalent. Generally, the respective path is one or more of a win-lose path and a lose-win path.

Abstract: A technique for decoding information, including a Viterbi decoder configured to decode (1) Front-end processed ADC data and (2) an output of an iterative error correction decoder in the event error correction decoding fails. The iterative error correction decoder is configured to decode Viterbi decoded data generated by the Viterbi decoder.

Abstract: Systems and methods are provided for generating error events for decoded bits using a Soft output Viterbi algorithm (SOYA). A winning path through a trellis can be determined and decoded information can be generated. Path metric differences can be computed within the trellis based on the winning path. A plurality of error event masks and error event metrics can be generated based on the decoded information and the path metric differences.

Abstract: A tail-biting decoding method and device are provided, so as to improve accuracy of backtracking state determination and decrease decoding delay. The method includes the following steps. Survivor paths of a training system are acquired. The training system is formed of a first transport block and a second transport block connected in series. The number of the survivor paths passing through each first state of the second transport block is counted. A first state having a maximum number of the survivor paths may be selected as a backtracking state of the second transport block. Backtracking decoding is performed on the second transport block by using the survivor paths on the backtracking state, so as to obtain a decoding result.

Abstract: Systems and methods are provided for improved designs and performance for iterative decoder systems. In some embodiments, the iterative decoder may be decoupled from FIR samples through an FIR RAM, thus resulting in a less complex design and shorter processing times. In some embodiments, an intermediate memory may be used when passing information between the SOVA and LDPC of the iterative decoder. In some embodiments, the SOVA-required information may be continuously serialized from information received from the LDPC during each LDPC iteration. In some embodiments, the 1/(1+D2) precoder of the HR RLL encoder may be split into two serial, 1/(1+D) precoders. One 1/(1+D) precoder may be pulled outside of the HR RLL encoder and used in conjunction with the iterative decoder. This may allow for a 1/(1+D) precoder that may be used with the iterative decoder while maintaining the RLL constraints imposed upon the encoded information by the HR RLL encoder.

Abstract: In a particular embodiment, a channel detector is disclosed that includes a programmable look-up table (LUT) to relate user bits to channel bits. The programmable LUT is adapted to be implemented on a state trellis of arbitrary radix. The channel detector further includes a sectional precoder coupled to a channel and having access to the programmable LUT. The sectional precoder is adapted to map channel bits to user bits and vice versa using a programmable LUT.

Abstract: A programmable compute unit with an internal register with a bit FIFO for executing Viterbi code is configured to accumulate in the forward path the best-path to each state in an internal register and store the survivor trace back information bit for each state in each stage in a bit FIFO; and in the trace back, selecting the optimal best-path through the Viterbi trellis by tracing through the bit trace back information survivor bits beginning with the survivor bit of the last stage path; and generating in response to the Viterbi constrain length and a current bit FIFO address, the next bit FIFO address and decoded output bit for the next previous stage.

Abstract: Various aspects of a method for minimum mean square error soft interference cancellation (MMSE-SIC) based sub-optimal maximum likelihood (ML) detection for a multiple input multiple output (MIMO) wireless system may comprise selecting at least one constellation point in a constellation map based on at least one of a plurality of received symbols. A number of the at least one constellation point may be less than or equal to a number of previously selected constellation points in a previous constellation map. At least one of the plurality of received symbols may be decoded based on the selected at least one constellation point.

Abstract: A Viterbi detector includes a plurality of possible bit patterns that correspond to branches of a detector trellis and a plurality of data dependent noise prediction filters, with multiple filters of different orders being associated with a given bit pattern. A method of decoding includes applying observables to a Viterbi detector that associates a plurality of data dependent noise filters with a given possible bit pattern that corresponds to a branch of the detector trellis, calculating the composite maximum likelihood branch metric by incorporating the results of filtering the observables through the associated plurality of filters, calculating the composite maximum likelihood branch metrics in the same manner for other possible bit patterns, and so forth, and associating soft output values with detected bits in the observables based on the calculated branch metrics.

Abstract: A Viterbi pack instruction is disclosed that masks the contents of a first predicate register with a first masking value and masks the contents of a second predicate register with a second masking value. The resulting masked data is written to a destination register. The Viterbi pack instruction may be implemented in hardware, firmware, software, or any combination thereof.

Abstract: Certain embodiments of the present invention are improved turbo-equalization methods for decoding encoded codewords. In one embodiment, in global decoding iteration i, the magnitude values of all decoder-input LLR values (Lch) are adjusted based on the number b of unsatisfied check nodes in the decoded codeword produced by global iteration i?1. The improved turbo-equalization methods can be used as the sole turbo-equalization method for a given global decoding session, or interleaved with other turbo-equalization methods.

Abstract: According to one embodiment, a signal processing device comprises a first waveform equalizer, a second waveform equalizer, a first Viterbi decoder, a second Viterbi decoder. The first and the second waveform equalizers equalize a waveform of the input signal according to first and second partial response characteristics and output first and second partial response signals. The first and second Viterbi decoders decode the first and the second partial response signals by means of Viterbi decoding process. The input signal is reproduced based on an output of the first Viterbi decoder and an output of the second Viterbi decoder.

Abstract: A multi-channel sequential Viterbi decoder includes: an input data buffer, a “Read Single Data Word from Input Data Buffer” signal driver, a processing unit selector, a decoder channel parameters registers unit, a processing unit for the “Reset Path Metrics” command, a processing unit for the “Set Path Metric Value for the Given Path Number” command, a processing unit for the “Get Single Bit from the Path with Given Number” command, a processing unit for the “Process Input Samples” command, a decoding paths and path metrics RAM, a unit for generating current decoder channel base address for the decoding paths and path metrics RAM, a unit for generating cell address for the decoding path and path metric RAM, and a data buffers unit for decoder channels output.

Abstract: Certain embodiments of the present disclosure provide a method for frequency-domain gain control in system utilizing orthogonal frequency division multiplexing (OFDM) multiple input multiple output (MIMO). The proposed method reduces the complexity of the system while maximizing the internal accuracy of the OFDM MIMO decoder and preserving the performance of the system.

Abstract: The present invention relates to a receiver device and method of detecting a block length of a data block in a data network, wherein a respective theoretical maximum value for a metric of a decoding operation is calculated for each of a plurality of candidate block lengths, and the calculated respective theoretical maximum value is compared to a respective actual value of the metric obtained for each of the plurality of candidate block lengths by the decoding operation. The candidate block length with the highest ratio between the respective actual value and the respective theoretical maximum value is then selected from the plurality of candidate block lengths to determine the block length of the data block.

Abstract: Provided are: plural circuit components including a circuit component which constitutes a receiving unit receiving a signal sequence which is arranged so that a desired signal and a signal different from the desired signal are lined up in time series, the desired signal indicating desired data which includes at least one of text data, sound data, image data, and a computer program product; and an operating parameter changing unit which changes an operating parameter of at least one of the plural circuit components, during a period in which the receiving unit receives the signal different from the desired signal.

Abstract: A signal decoder, a method of detecting an RF signal at a MIMO receiver and a MIMO receiver are disclosed herein. In one embodiment, the signal decoder includes: (1) a tree pruner configured to reduce a number of nodes of an MLD tree to expand based on modulation properties of the transmitted radio signals and SE enumeration of at least a portion of the MLD tree and (2) a vector sorter configured to sort multiple rows of child nodes of the MLD tree in parallel.

Abstract: A system and method implement low complexity maximum likelihood sequence detection. A decision feedback algorithm computes x(M+D+L?1). Optimality examination is performed for x(M), and state values and values of Markov states along paths from states in x(M) to xl(M+L) are computed.

Abstract: A decoding circuit includes: a level adjuster with pattern dependency arranged to generate a plurality of Viterbi target levels with pattern dependency; and a Viterbi decoder arranged to perform Viterbi decoding according to the Viterbi target levels with pattern dependency. A decoding circuit includes a Viterbi decoder arranged to perform Viterbi decoding, and the Viterbi decoder includes a branch metric generator arranged to generate a plurality of branch metrics with pattern dependency according to an input of the Viterbi decoder and a plurality of Viterbi target levels with pattern dependency. In particular, the branch metric generator includes: a plurality of branch metric generation paths arranged to generate a plurality of intermediate values according to the input of the Viterbi decoder and the Viterbi target levels with pattern dependency, respectively; and a selection unit for selecting a portion of the intermediate values as the branch metrics with pattern dependency.

Abstract: A system and method for recovering the seed of a pseudo-random binary sequence (PRBS) using soft decisions is disclosed. In some implementations, a log-likelihood ratio is calculated to determine the certainty with which each bit in the seed has been recovered, and in some implementations, the value of the PRBS is used in the calculation of the log-likelihood ratio. In some implementations, a linear feedback shift register stores the log-likelihood ratio for each bit in the sequence.

Abstract: A system, apparatus, and method are provided for a nonlinear Viterbi detector that may be used in an iterative decoding system or any other system with multiple, interconnected detectors. At least one of the Viterbi detectors may estimate the digital information sequence in a received signal based on the signal itself and an estimate of the signal from another of the Viterbi detectors. The at least one Viterbi detector may calculate branch metrics for a subset of the branches in an associated trellis diagram by selecting branches that correspond to the output of the other Viterbi detector.

Abstract: A method for communication includes receiving a communication signal conveying multiple encoded bits of an Error Correction Code (ECC). Respective N-bit soft decoding metrics are computed with respect to the bits of the ECC. A scaling factor is computed based on at least one characteristic of the N-bit soft decoding metrics and on at least one property of the received communication signal. The N-bit soft decoding metrics are scaled by the scaling factor. The scaled N-bit soft decoding metrics are quantized to produce respective K-bit metrics, K<N. The ECC is decoded using the scaled and quantized soft decoding metrics.

Abstract: According to one aspect of the present invention, an apparatus is provided to enable weather band radio signals to be received and processed using a digital signal processor (DSP). The DSP can include functionality to implement both frequency modulation (FM) demodulation and weather band data demodulation, i.e., specific area encoding (SAME) demodulation. In one such embodiment, soft decision samples of a SAME message can be combined, and based on a combined result, a hard decision unit can generate a bit value of weather band data.