Abstract: A two-dimensional self-RAID method of protecting page-based storage data in a MLC multiple-level-cell flash memory device. The protection scheme includes reserving one parity sector across each data page, reserving one parity page as the column parity, selecting a specific number of pages to form a parity group, writing into the parity page a group parity value for data stored in the pages of the parity group. The parity sector represents applying a RAID technique in a first dimension. The group parity represents applying a RAID technique in a second dimension. Data protection is achieved because a corrupted data sector can likely be recovered by the two dimensional RAID data.

Abstract: This disclosure relates generally to data decoding, and more particularly to iterative decoders for data encoded with a low-density parity check (LDPC) encoder. LDPC decoders are disclosed that use reduced-complexity circular shifters that may be used to decode predefined or designed QC-LDPC codes. In addition, methods to design codes which may have particular LDPC code performance capabilities and which may operate with such decoders using reduced-complexity circular shifters are provided. The generation of quasi-cyclic low density parity check codes and the use of circular shifters by LDPC decoders, may be done in such a way as to provide increased computational efficiency, decreased routing congestion, easier timing closure, and improved application performance.

Abstract: One embodiment of the present invention relates to an error tolerant memory circuit having a low hardware overhead that can tolerate both single volatile soft errors and permanent errors. In one embodiment, the method and apparatus comprise a memory circuit having a plurality of memory element pairs, respectively having two memory storage elements configured to store a data unit. One or more parity generation circuits are configured to calculate a first parity bit from data written to the plurality of memory element pairs (e.g., the two memory storage elements) and a second parity bit from data read from one of the two memory storage elements in the plurality of memory element pairs. Based upon the calculated first and second parity bits, the memory circuit chooses to selectively output data from memory storage elements not known to contain an error.

Abstract: An apparatus, system, and method for providing error protection for data-masking bits in a memory device of a memory system are provided. The memory device includes a memory core to store data, and a data interface to receive the data and data-masking bits associated with a write command. The memory device also includes a gating block to control writing the data to the memory core, where the writing of the data to the memory core is inhibited upon detecting an error with one or more of the data-masking bits.

Abstract: A method and apparatus for embedded memory security is disclosed. One embodiment protects data in a memory block from unauthorized reading. When writing or reading data to or from the memory block an error correction code is used to calculate an ECC value, wherein the calculation of the ECC value is based on a combination of the data and a access identifier provided to the memory block prior to reading. The access identifier identifies the requesting program. A read error is signalled in case the calculated ECC value does not match a stored value thus indicating an access violation.

Abstract: Example embodiments may provide a memory device and memory data reading method. The memory device according to example embodiments may include a multi-bit cell array, an error detector which may read a first data page from a memory page in the multi-bit cell array and may detect an error-bit of the first data page, and an estimator which may identify a multi-bit cell where the error-bit is stored and may estimate data stored in the identified multi-bit cell among data of a second data page. Therefore, the memory device and memory data reading method may have an effect of reducing an error when reading data stored in the multi-bit cell and monitoring a state of the multi-bit cell without additional overhead.

Abstract: In one embodiment, a system includes a memory, and a memory controller coupled to the memory via an address bus, a data bus, and an error code bus. The memory stores data at an address and stores an error code at the address. The error code is generated based on a function of the corresponding data and address.

Abstract: A method for arranging memories of a low-complexity low-density parity-check (LDPC) decoder and a low-complexity LDPC decoder using the same method are provided. The main idea of the method for arranging memories of a low-complexity LDPC decoder is to merge at least one or two small-capacity memory blocks into one memory group, so that the memory area can be reduced and the power consumption in reading or writing data is lowered. Besides, as the merged memory group shares the same address line in reading or writing data, at least one delay unit is used to adjust the reading or writing order and thereby ensure data validity. A low-complexity LDPC decoder using the disclosed method can meet the demands of high processing rate and low power consumption.

Abstract: A CPU specifies factors related to the month, the day of the week, and a time period including the current point in time, based on time data obtained by a timer. The CPU also specifies factors that are related to a grid ID and a road category of a given link, based on map display data, link data, and the like stored in an update map information database. The CPU then reads a sample collection number indicating the number of samples of probe information required to generate traffic information for that link and in sequence for other links. When a center traffic information DB contains stored therein, samples of probe information equal to or greater than the sample collection number for a link, the CPU generates the traffic information for that link and stores the generated traffic information as current traffic information.

Abstract: An error corrector with a high use efficiency of a memory includes a memory, a bus device, an input buffer and an error correction module. The memory stores data. The bus device controls a memory access. The input buffer receives and temporarily stores a coded blockcode data, and writes the coded blockcode data in the memory through the bus device. The error correction module reads the coded blockcode data in the memory through the bus device and decodes it in rows and columns to thereby obtain decoded data and check bytes. The error correction module writes the decoded data in the memory through the bus device and discards the check bytes.

Abstract: A communication device is disclosed. The device is configured to generate a first block of first cyclic redundancy check (CRC) parity bits on a transport block wherein the first block of CRC parity bits is based on a first generator polynomial, to attach the first block of CRC parity bits to the transport block and to segment the transport block into multiple code blocks. The processor is also configured to generate a second block of CRC parity bits on each code block wherein each of the second blocks of CRC parity bits is based on a second generator polynomial that is different than the first generator polynomial. The first and second generator polynomials have a common degree. A second block of CRC parity bits is attached to each code block, and the code blocks are concatenated after channel encoding.

Abstract: A method for processor error checking including receiving an instruction data, generating a pre-processing parity data based on the instruction data, maintaining the pre-processing parity data, processing the instruction data, generating a post-processing parity data based on the processed instruction data, checking for an error related to processing the instruction data by comparing the post-processing parity data to the pre-processing parity data, and transmitting an error signal that indicates the error related to processing the instruction data occurred if the post-processing parity data does not match the pre-processing parity data, wherein checking for the error related to processing the instruction data is performed without using a duplicate processing circuitry.

Abstract: Systems, methods, and devices are disclosed, including a device that includes a plurality of data locations, a quantizing circuit coupled to the plurality of data locations, and an error detection module coupled to the quantizing circuit. In some embodiments, the error detection module includes an encoder configured to encode incoming data with redundant data derived from the incoming data and a decoder configured to detect errors in stored data based on the redundant data.

Abstract: An encoder includes an information holding section which stores flag bytes and an initial address, a data generation section which generates sets of first parity symbols from the initial address and the flag bytes, a parity generation section which generates and outputs sets of second parity symbols, for each column of data units included in the block, from the columns of data units included in the block and input user control data. The data generation section generates the addresses and the sets of first parity symbols, required to generate the columns of data units included in the block, based on the initial address and the flag bytes, selects necessary portions from the flag bytes and the addresses and the sets of first parity symbols generated, and outputs the portions to the parity generation section, as the columns of data units included in the block.

Abstract: Apparatus and methods for Cyclic Redundancy Check (CRC) error injection between storage controllers and storage devices in a storage system. A plurality of bridge devices are configured in a storage system each coupled persistently coupled to a corresponding one of the plurality of storage devices. Each bridge device may couple to one or more Serial Attached SCSI (SAS) initiators for transferring exchanges between one or more SAS initiators and the attached target storage device. Each bridge device receives parameters from a SAS initiator or an administrative client directing the bridge regarding injection of CRC errors. A log memory in each bridge may log information regarding the injected CRC errors.

Abstract: Systems and methods establishing and/or utilizing an error-tolerant multithreaded register file are provided. The systems and methods employ dynamic multithreading redundancy (DMR) for error correction. Non-overlapped register access patterns associated create hardware redundancy dynamically that is exploited for error control. Immediate write-back and self-recovery techniques are employed to further enhance the error correction functionalities of the disclosed systems and methods. Error control is improved for memory components and processing functions in multithreaded computing systems.

Abstract: A method of storing a plurality of blocks of data in a plurality of physically distinct non-volatile memory devices, each being independently written to or read from, wherein each block of data is the minimum amount of data that can be written to or read from the non-volatile memory device. The method includes generating one or more blocks of error checking data based upon the plurality of blocks of data; and storing the plurality of blocks of said data and the one or more blocks of error checking data in the plurality of distinct physical non-volatile memory devices, with a block of data in a different physical memory device. Further, the method links the address of the plurality of blocks of data and the one or more blocks of error checking data in a cyclical link so that any entry to one of the blocks will result in a link all of the other blocks.

Abstract: Various embodiments of the present invention provide systems and methods for data processing retries. As an example, a data processing retry circuit is discussed that includes a stepped erasure window register, and an erasure flag set circuit. The stepped erasure window register includes: an erasure flag location, an erasure flag length, and a step size. The erasure flag set circuit is operable to assert a first erasure flag beginning at the erasure flag location and having the erasure flag length at a first time. In addition, the erasure flag set circuit is operable to assert a second erasure flag beginning at the erasure flag location plus the step size, and having the erasure flag length at a second time.

Abstract: A system for maximizing the efficiency of a load balancing server for an asymmetric web farm utilizes a TCP stack and data packets to send and receive client service requests. An internal buffer enables each web server in the web farm to balance their loading based on the contents of the client service request. Data switching between the address portion of the user space and the address portion of the kernel space within the load balancing server is eliminated.

Abstract: A semiconductor memory device includes a memory cell array and an error correction code (ECC) engine. The memory cell array stores bits of normal data and parity data therein. The ECC engine performs a masking operation in a masking mode, the ECC engine calculating the parity data using the normal data. The normal data includes a first section that is to be updated and a second section that is to be saved by the masking operation.

Abstract: A system, method and article of manufacture are disclosed for processing Low Density Parity Check (LDPC) codes. The system comprises a multitude of processing units for processing the codes; and a processor chip including an on-chip, multi-port data cache for temporarily storing the LDPC codes. This data cache includes a plurality of input ports for receiving the LDPC codes from some of the processing units, and a plurality of output ports for sending the LDPC codes to others of the processing units. An off-chip, external memory stores the LDPC codes and transmits the LDPC codes to and receives the LDPC codes from at least some of the processing units. A sequence processor controls the transmission of the LDPC codes between the processor units and the on-chip data cache so that the LDPC codes are processed by the processing units according to a given sequence.

Abstract: A method, system and computer program product for assessing information security interviews users regarding technical and non-technical issues. In an embodiment, users are interviewed based on areas of expertise. In an embodiment, information security assessments are performed on domains within an enterprise, the results of which are rolled-up to perform an information security assessment across the enterprise. The invention optionally includes application specific questions and vulnerabilities and/or industry specific questions and vulnerabilities. The invention optionally permits users to query a repository of expert knowledge. The invention optionally provides users with working aids. The invention optionally permits users to execute third party testing/diagnostic applications. The invention, optionally combines results of executed third party testing/diagnostic applications with user responses to interview questions, to assess information security.

Abstract: The present invention provides a method and system for performing in-line error correction in a disk storage system. The system includes an error correction (ECC) module; and a first memory storage device, wherein the first memory storage device and the error correction module simultaneously receive data from a storage disk before being buffered for transfer to a host system. The ECC module provides error correction mask before any data is transferred from the first memory storage device to a second memory buffer.

Abstract: One embodiment of the present invention provides a demultiplexer implemented as a nanowire crossbar or a hybrid nanowire/microscale-signal-line crossbar with resistor-like nanowire junctions. The demultiplexer of one embodiment provides demultiplexing of signals input on k microscale address lines to 2k or fewer nanowires, employing supplemental, internal address lines to map 2k nanowire addresses to a larger, internal, n-bit address space, where n>k. A second demultiplexer embodiment of the present invention provides demultiplexing of signals input on n microscale address lines to 2k nanowires, with n>k, using 2k, well-distributed, n-bit external addresses to access the 2k nanowires.

Abstract: A device includes a tag cache memory array; a pre-parity unit configured to receive an address, and calculate and output a pre-parity bit calculated from all bits of the address. A comparator is configured to compare a tag read from the tag cache memory array with the address, and output a read-hit bit. The read-hit bit is true when the tag and the address are identical, and is false when the tag and the address are not identical. The device further includes a simplified parity-check unit configured to receive and perform operations on the pre-parity bit, the read-hit bit, and a parity bit from the tag cache memory array, and to output a read-parity bit.

Abstract: Methods, apparatuses and systems are disclosed involving a memory device. In one embodiment, a memory device is disclosed that includes a command error module of the memory device operably coupled to at least one of a command signal and an address signal and configured to detect and report a parity error on the command signal, the address signal, or combinations thereof In some embodiments, a memory device may include a temperature sensor operably coupled to a mode register. The temperature sensor may be configured to sense a device temperature and report a temperature status. Furthermore, the memory device may be incorporated into a memory module, which may be included in an electronic system.

Abstract: A method includes checking a first parameter that indicates whether parity generation and checking for a at least a sub-portion of a cache line is disabled, setting at least one parity bit, corresponding to the sub-portion, in the cache line with a second parameter that indicates an action to perform when the first parameter indicates that parity generation and checking is disabled, passing the at least one set parity bit with the sub-portion to a processor for processing, and performing the action when the sub-portion is processed by the processor, wherein the processor performs the action.

Abstract: A parallel CAM that can perform a parity check fast at the search time. The CAM searches all addresses at the same time and determines whether or not the same data as input data is stored. The CAM includes a write search parity generator for generating parities of n-bit write and search data, a plurality of memory locations corresponding to a plurality of addresses, and a NAND circuit for activating a parity error signal if at least one of valid parity match signals outputted from the memory locations is inactive. Each memory location includes n data memory cells, a parity memory cell, an exclusive OR circuit for judging whether or not the parities match, and activating a parity match signal, if they are matched, and a NAND circuit for validating the parity match signal using a data match signal.

Abstract: An apparatus and method for distinguishing correctable bit errors in memory. A bit error detection module detects a correctable bit error in a memory in response to a READ operation. The correctable bit error is correctable using error-correcting code. The READ operation is generated during normal operation. A comparison module compares an error location indicator with a stored error location indicator. The error location indicator includes a memory location of the correctable bit error. The stored error location indicator corresponds to a previously stored error location indicator of a previous correctable bit error. A storage module stores the error location indicator if the comparison module determines that the error location indicator differs from a stored error location indicator. An error counter module increases an error counter corresponding to the error location indicator if the comparison module determines that the error location indicator matches a stored error location indicator.

Abstract: This can relate to non-regular parity distribution of a non-volatile memory (“NVM”), such as flash memory, and detection of the non-regular parity via a metadata tag. For example, each codeword of the NVM can include one or more parity pages that may be distributed at random through the NVM. To identify the page as a parity page, a parity page marker can be included in the metadata of that page. During power-up of the NVM, an address table including the logical-to-physical address mapping of the pages can be created. Pages including a parity page marker, however, can be skipped during the creation of this address table. Additionally, by having two or more parity pages associated with a codeword, an additional layer of protection can be provided for repairing errors in that codeword.

Abstract: In one embodiment, the present invention includes a deinterleaver having an input interface to receive orthogonal frequency division multiplexing (OFDM) symbols from a demodulator, a memory coupled to the input interface to store the OFDM symbols, an output interface coupled to the memory to receive the OFDM symbols stored in the memory, and a digital phase lock loop (PLL) to control and adjust a reading rate of data from the memory responsive to dynamic and static channel conditions.

Abstract: An method of operating a memory system including a nonvolatile memory device and a controller. The method includes receiving a source word, converting the received source word to a codeword, and programming the converted codeword in the nonvolatile memory device. A length of the converted codeword can be greater than a length of the received source word, and a difference between the numbers of first and second digital bits of the converted codeword can be less than a reference value.

Abstract: A method for handling errors in a cache memory without processor core recovery includes receiving a fetch request for data from a processor and simultaneously transmitting fetched data and a parity matching the parity of the fetched data to the processor. The fetched data is received from a higher-level cache into a low level cache of the processor. Upon determining that the fetched data failed an error check indicating that the fetched data is corrupted, the method includes requesting an execution pipeline to discontinue processing and flush its contents, and initiating a clean up sequence, which includes sending an invalidation request to the low level cache causing the low level cache to remove lines associated with the corrupted data, and requesting the execution pipeline to restart. The execution pipeline accesses a copy of the requested data from a higher-level storage location.

Abstract: A method, system, and computer software product for operating a collection of memory cells. Memory cells are organized into a group of memory cells, with each memory cell storing a binary multi-bit value delimited by characteristic parameter bands. Two adjacent characteristic parameter bands are assigned binary multi-bit values that differ by only one bit. In one embodiment, an error correction unit calculates an actual parity check value of the retrieved binary multi-bit values for the group of memory cells. If the actual parity check value is not equal to the expected parity check value, the error correction unit assigns the error memory cell a corrected binary multi-bit value with the characteristic parameter value within the characteristic parameter band adjacent to the characteristic parameter band associated with the retrieved binary multi-bit value such that calculating a second actual parity check value correctly indicates the parity for the group of memory cells.

Abstract: Storing, retrieving, transmitting and receiving data (20) by a) separating the data into a plurality of data subsets (A, B); b) generating parity data (P) from the plurality of data subsets (A, B) such that any one or more of the plurality of data subsets may be recreated from the remaining data subsets and the parity data (P). Steps a and b may be repeated on any one or more each of the plurality of data subsets and parity data providing further data subsets and further parity data; and d) storing each of the further data subsets and further parity data in separate storage locations (380) or transmitting the further data subsets and further parity data.

Abstract: For checking an address decoder of a data memory, from a record of addresses of the data memory, designated as base addresses, one after another each base address is selected, and the following steps are executed for the respectively selected base address: a) determining the content of the base address; and b) selecting an address having the Hamming distance 1 from the base address, designated as the Hamming address; and then: c) changing the content of the Hamming address selected in step b); and then: d) reading the base address and detecting an error of the address decoder if the content read differs from that determined in step a); and e) recovering the content of the Hamming address.

Abstract: A transmission method based on a Hybrid Automatic Repeat Request (HARQ) scheme for in a communication system. A codeword is generated using a Low Density Parity Check (LDPC) code. Parity bits of the codeword are classified on a basis of a transmission priority. Parity bits with an identical transmission priority are grouped. An information bit group of the codeword and parity bit groups with the identical transmission priority are shuffled in a predefined pattern. A packet is generated from the shuffled information bit group and the shuffled parity bit groups based on the transmission priority. The generated packet is retransmitted in response to a retransmission request. The transmission method can obtain the effect of channel interleaving by setting a transmission priority according to importance of puncturing target blocks, shuffling blocks with the same priority, and shuffling and transmitting bits configuring each block.

Abstract: A system and a method detects errors when writing data to a memory in a computer system. An error detection memory write request for writing an error detection value to a memory location within the memory section is issued, the error detection value being associated with the block of data. A data memory write request for writing the block of data to the memory section is issued such that at least part of the block of data is written to the memory location. A check is performed to determine whether the error detection value in the error detection memory write request corresponds to the block of data in the data memory write request.

Abstract: Methods and apparatus for performing parity and/or ECC operations are disclosed. An example method includes determining that an opcode is being transmitted on a bus and determining if the transmitted opcode is a memory operation. In the event the transmitted opcode is a memory write operation, the example method includes calculating a parity bit for data associated with the opcode, writing the calculated parity bit to a parity table and writing the data to a memory. The example method also includes, in the event the transmitted opcode is the memory read operation, recovering data from a previously written memory, calculating a parity bit for the recovered data, recovering a previously stored parity bit for the recovered data, comparing the parity bit for the recovered data with the previously stored parity bit and, in the event the recovered data parity bit does not match the previously stored parity bit, providing an error notification.

Abstract: A RAID system is provided for detecting and correcting dropped writes in a storage system. Data and a checksum are written to a storage device, such as a RAID array. The state of the data is classified as being in a “new data, unconfirmed” state. The state of written data is periodically checked, such as with a timer. If the data is in the “new data, unconfirmed” state, it is checked for a dropped write. If a dropped write has occurred, the state of the data is changed to a “single dropped write confirmed” state and the dropped write error is preferably corrected. If no dropped write is detected, the state is changed to a “confirmed good” state. If the data was updated through a read-modified-write prior to being checked for a dropped write event, its state is changed to an “unquantifiable” state.

Abstract: A method for writing data to a storage pool includes receiving a write operation to write a logical block of data to the storage pool, determining a number (n?1) of physical blocks required to store the logical block of data, generating a parity block using the logical block of data, allocating n physical blocks in the storage pool, writing the parity block in the first of n allocated physical block, and writing the logical block of data across the remaining n?1 allocated physical blocks, where n is less than a number of disks in the storage pool, and where each of the n allocated physical blocks is located on a different disk in the storage pool.

Abstract: A write validation system that includes a first address signature collector module that generates a first address signature that is indicative of a write address of data when the data is received at a memory control module. A second address signature collector module generates a second address signature that is indicative of the write address of the data when the data is transferred from the memory control module. An address signature validation module receives the first address signature from the first address signature collector module, receives the second address signature from the second address signature collector module, and compares the first address signature to the second address signature.

Abstract: A memory device may include a memory plane including a group of memory cells configured to store a block of bits including data bits and parity bits, and a detector for detecting a fault injection including a reader to read each bit, and a first checker to perform, when reading a block, a parity check based on the read value of each data and parity bit. The memory plane may include reference memory cells arranged between some of the memory cells to create packets of m memory cells. Each reference memory cell may store a reference bit and each packet of m memory cells may store m bits of the associated block, when m is greater than 1, with different parities. The detector may further include a second checker to perform, when reading the block, a check on the value of each reference bit.

Abstract: A wireless communication device including a first CRC coder that generates a first block of CRC parity bits on a transport block and associates the first block of CRC parity bits with the transport block, a segmenting entity that segments the transport block into multiple code blocks after associating, and a second coder that generates a second block of CRC parity bits on each code block and associates a second block of CRC parity bits with each code block. The first and second blocks of CRC parity bits are based on first and second generator polynomials.

Abstract: The present invention relates to a method of operating an electronic device and an electronic device. The electronic device comprises a signal path for transmitting data, an input/output interface connected with the signal path, a masking circuit and an error calculation circuit. The masking circuit is connected with the signal path and the error calculation circuit. The error calculation circuit is connected with the signal path. The signal path is connected with the masking circuit to deliver masking information to the masking circuit. The masking circuit considers the received masking information for masking the data and delivers the masked and non-masked data to the error detection circuit.

Abstract: A memory device electrically connectable to a host circuit receives, from the host circuit, data including a first actual data to be written into the first memory area; acquires first parity data associated with the first actual data; generates second actual data that is a copy of the first actual data, and second parity that is a copy of the first parity data; writes the first actual data and the first parity data into the first memory area, and writes the second actual data and the second parity data into the second memory area; and reads the first actual data, the first parity data, the second actual data, and the second parity data from the data memory section for transmission to the host circuit.

Abstract: A method in a data storage device for storing a plurality of data bits into a non-volatile memory includes transforming a plurality of data bits to be stored in a non-volatile memory device to generate a plurality of transformed data bits. The method further includes generating a parity bit corresponding to the plurality of transformed data bits, transforming the parity bit, and storing the plurality of data bits and the transformed parity bit in the non-volatile memory device. Each of the plurality of data bits and the parity bit form an all-one codeword.

Abstract: A concatenated channel decoding method wherein the bits of a set of N1 bits decoded using a first iterative block decoding algorithm and intended to be decoded using a second block decoding algorithm, are sent in parallel in at least one subset of P bits to a buffer for temporary storage. The decoding method comprises receiving in parallel at least one subset of Q bits belonging to the set of N1 bits sent to the buffer, detecting errors with the help of the second decoding algorithm, based on the bits decoded using the first decoding algorithm, and correcting the bits stored in the buffer as a function of possible errors detected. Detecting errors and/or the correcting the stored bits comprise a parallel processing of the bits of each subset of Q bits received.

Abstract: When a transaction layer circuit detects an error, error information in respect of transmission data is set in a TLP digest. The method includes: a step in which, at an endpoint (3a) that receives a memory read request transmitted by the root complex 1, if an error is detected during transmission of first data corresponding to the requested TLP, error information is set in the TLP digest and a completion with data attached is returned; a step in which the root complex (1) returns a memory read request based on the error information to the endpoint; a step in which the endpoint returns requested second data; and a step in which the root complex terminates the response after overwriting the error location of the first data that was held, with the second data.

Abstract: Cyclic-redundancy-code (“CRC”) information that is received along with a frame from a fiber-channel is stored in an on-chip frame buffer, and later checked to ensure the integrity of the data while in the frame buffer. In various embodiments, data frames, along with their CRC information, are stored into a data-frame buffer, and/or non-data frames along with their CRC information are stored into a receive-non-data-frame buffer. The improved communications channel system includes a channel node having dual ports, each port supporting a fiber-channel arbitrated-loop serial communications channel. The serial communications channels each include CRC on data transmissions on the channel, an on-chip frame memory located on-chip in the channel node that receives a data frame and the frame's associated CRC from the communications channel, and an integrity apparatus that later uses the received associated CRC for data-integrity checking of data in the on-chip frame memory.