Abstract: Methods and apparatus defer correction of an error in a tag entry of a cache tag array. An address of requested data, including an address tag field, can be received by a cache. A first hit indication based at least in part on a comparison of the address tag field and a first tag entry can be generated and result in outputting of a first data entry of a data array. An error in the tag entry can be detected, and the first data entry can be disregard based at least in part on the detected error.

Abstract: An improved integrated circuit area efficient redundancy multiplexer circuit technique provides similar functionality to conventional CMOS transmission, or “pass” gates while concomitantly reducing circuit complexity, the die area necessary to support redundant elements and complementary control signals in memory device ICs and undesired parasitic capacitance. The technique of the present invention effectuates this end by utilizing the on-chip boosted voltage levels (Vpp) which are generally available in integrated circuit memory devices to supply the voltage for the control signal applied to a single N-channel transistor pass gate instead of the conventional supply voltage level of Vcc. The Vpp voltage and circuit ground (“GND”) are then utilized as the logic “high” and “low” signal levels respectively. This use is made possible due to the fact that these control signals operate at a direct current (“DC”) level after device power-up.

Abstract: A method of checking for errors in a set associative cache array, by comparing a requested value to values loaded in the cache blocks and determining, concurrently with this comparison, whether the cache blocks collectively contain at least one error (such as a soft error caused by stray radiation). Separate parity checks are performed on each cache block and if a parity error occurs, an error correction code (ECC) is executed for the entire congruence class, i.e., only one set of ECC bits are used for the combined cache blocks forming the congruence class. The cache operation is retried after ECC execution. The present invention can be applied to a cache directory containing address tags, or to a cache entry array containing the actual instruction and data values. This novel method allows the ECC to perform double-bit error as well, but a smaller number of error checking bits is required as compared with the prior art, due to the provision of a single ECC field for the entire congruence class.

Abstract: The bits of a data block are assigned to a plurality of logical groups such that at most one bit corresponding to a component is assigned to a logical group. This assignment ensures that a component failure may introduce at most one bit error to a logical group. A number of bits in a logical group is selected to reduce the number of check bits for a given number of data bits. Error correction may be performed within each logical group to correct single errors within the logical group. Because each logical group is assigned at most one bit corresponding to a component, component failures may be detected and corrected.

Abstract: Where a recording medium recorded on at a slave side apparatus is reproduced, it has been made possible to perform on cite modification processing identical to that conducted at a master side apparatus, by reproducing, at the master side apparatus, the primary information added with parity symbol for error correction from the recording medium on which the primary information is recorded, correcting the symbol error of primary information reproduced at the reproducing means using the reproduced parity symbol, producing the flag which indicates the production of an uncorrectable symbol error in one unit of a block of a specified amount of information and thus outputting the modification information corresponding to the primary information and the flag and forming, at the slave side, the parity symbol for correction of error of primary information output at the master side apparatus and recording the primary information with the parity symbol and modification information, on the same recording medium.

Abstract: Data integrity is increased on mass-storage devices through a scheme whereby, a frame-based cyclic redundancy code (CRC) for each sector is recorded. A frame-based CRC is generated from the CRCs of the frames that compose a sector of data. In recording data, a CRC is generated from each frame, later, a master CRC is generated from the frame CRCs, then sector and master CRC are recorded on the mass-storage device medium. In retrieving data, the sector composed of frames and a master CRC are read, a plurality of CRCs are generated from each of the frames, a second master CRC is generated from the frame CRCs, and the master CRCs are compared to determine data integrity. In another embodiment, an input/output error detection and correction checksum (IOEDC), an error correction code (ECC) and a CRC are generated from a sector of data, and the IOEDC, ECC and CRC are stored on disc with the data sector.

Abstract: Synchronous dynamic random access memory (SDRAM) method and apparatus are provided for implementing address error detection. Addressing errors are detected on the memory interface independent of data ECC, with reduced memory read access latency and improved processor performance. Addressing errors are detected while allowing differentiation between memory addressing failures that are required to stop the system and memory cell failures that allow continued operation. A predefined pattern is generated for a write burst to the SDRAM. The predefined pattern is dependent on a write address. A bit of the predefined pattern is sequentially stored into the SDRAM on each burst transfer of the write burst to the SDRAM. An expected pattern is generated from a read address for a read burst. The stored predefined pattern is retrieved during a read burst. The retrieved predefined pattern is compared to the generated expected pattern for identifying a type of an addressing error.

Abstract: A memory card adapter and method is provided which can add features or provide functions to a computer system's memory modules without having to replace and discard existing memory modules. An adapter is provided which has electrical contacts that are capable of being plugged into a memory module receiving socket of. a motherboard and a memory module receiving socket capable of receiving and retaining a memory module such as a SIMM. The adapter has logic, circuitry and/or memory chips to add new function to the existing memory module and also has all information and hardware needed for proper interface with the motherboard of the computer system. The present invention can add a variety of function such as parity, error correction code and error correction code on SIMM as well as convert signals which form from the system for use on the SIMM which signals in the form generate by the computer are not compatible with the SIMM.

Abstract: A memory system is disclosed wherein data contents of the memory system are protected via an EDC coding method and wherein, in order to be able to recognize addressing errors, addresses are also involved in such EDC coding.

Abstract: A method for providing specific test programs from a production test program for testing semiconductor devices, in accordance with the present invention, includes providing a semiconductor device to be tested by a tester and initiating a production test program. The production test program includes a plurality of program files and test code sequences. The production test program is held at a test which is to be extracted, and register information and settings are extracted from the tester for the test to be extracted. The register information and settings are stored in a storage file, and the storage file is assembled and translated to provide an executable test program for an extracted test for testing the semiconductor device or other semiconductor devices.

Abstract: An apparatus and method for accessing a cache memory. In a cache memory, an address is received that includes a set field and a partial tag field, the set field and the partial tag field together including fewer bits than necessary to uniquely identify a region of memory equal in size to a cache line of the cache memory. The set field is decoded to select one of a plurality of storage units within the cache memory, each of the plurality of storage units including a plurality of cache lines of the cache memory. The partial tag field is compared to a plurality of previously stored partial tags that correspond to the plurality of cache lines within the selected one of the plurality of storage units to determine if the partial tag field matches one of the plurality of previously stored partial tags. If the one of the previously stored partial tags matches the partial tag field, one of the plurality of cache lines that corresponds to the one of the plurality of previously stored partial tags is output.

Abstract: A ROM including an array, each cell of which is accessible by means of a column address and of a row address, includes a parity memory for storing the expected parity of each row and of each column, an electrically programmable one-time programmable address memory, a testing circuit for, during a test phase, calculating the parity of each row and of each column, comparing the calculated and expected parities for each row and each column, and in case they are not equal, marking the row or column in the address memory, and a correction circuit for, in normal mode, inverting the value read from the array cell, having its row and column marked in the address memory.

Abstract: Upon receiving an access command designated with a parity generation mode from a main controller upon update data transfer from a host apparatus, a cache controller reads out update data from that location in a block in an update data area in a cache memory, which is designated by the command, and writes the readout data in a FIFO memory. The cache controller then reads out data before update from that location in a block in a data before update area, which is present in an identical block column, EX-ORs the readout data and the contents stored in the FIFO memory, and writes the obtained EX-OR in the FIFO memory. The cache controller reads out parity before update from that location in a block in a parity before update area, which is one block ahead of the block in the data before update area, and EX-ORs the readout parity and the contents of the FIFO memory to generate parity data.

Abstract: A device and method for recovery from address errors is described. When an address error is detected on a local channel, such as a local bus, the coherency states of one or more lines of cache memory associated with the local channel are read, and actions are taken in response. Reading of coherency states ranges from a complete and active interrogation of all cache lines, to a selective and passive interrogation, such as in responding to snoop requests. If the data state consistency is unknown, such as when the MESI state is Modified (M) or Exclusive (E), then the corresponding data in main memory is poisoned. Poisoning may be accomplished by writing a detectable but unrecoverable error pattern in the main memory. Alternatively, the same effect may be accomplished by signaling a hard error on the system bus. If the data state consistency of an interrogated cache line is Shared (S) or Invalid (I), the line may be ignored or the line marked invalid.

Abstract: A method for logically rejecting previously recorded track residue from magnetic media is presented. A session ID unique to a given recording session is encoded into track packet error check and error correction codes but is not itself actually written to tape. During a data recovery session, a reference session ID for the original recording session is acquired by reconstructing the packet session ID from the first few track packets and verifying that a predetermined number of consecutive track packets have identical packet session IDs. Once the reference packet session ID is acquired, it is preloaded into error detection and correction hardware. When a residue track encoded with a previously recorded session ID is recovered by the tape drive track packet detection circuitry, it is inherently rejected because the error detection and correction hardware detects an error and it is therefore never allowed into the data buffer.

Abstract: A multicast file transmission method is disclosed, which permits efficient multicast file transmission with high reliability even in the communication system, which uses in the up-link direction a specified transmission circuit, such as a multiple access satellite communication circuit. In the multicast file transmission method, a data file is composed of a plurality of blocks from a sending side to respective receiving destinations. At respective destinations, a test is carried out to find whether or not any transmitted packet is erroneous in the data file composed of a plurality of blocks after the end of said transmission of the data file.

Abstract: An error correction method for data bytes in a memory uses an error correcting block code such as a Hamming code to detect and correct errors, if any, in the data bytes. The error correction method can be performed by relatively simple and inexpensive logic circuitry while improving the speed of error correction to reduce delays in the external data access time.

Abstract: To improve the processing efficiency and throughput by performing only a recovery process in read-accessing to a memory even when an address parity error has occurred in write-accessing to the memory, a selector is provided to select one of write data and a parity-bitted address for writing to the memory. If an address parity error has detected, the selector selects the parity-bitted address, in which the address parity error has occurred, instead of write data to be written to the memory during the write-accessing thereto.

Abstract: An error correcting apparatus includes a storing means for storing product code with n2 rows and n1 columns, an error correcting unit 5 that performs error correction for four code sequences simultaneously in parallel, and a bus control unit 2 for reading codes on four rows from the buffer memory 1 and transferring the codes to the error correcting unit 5. The bus control unit 2 reads and transfers four consecutive codes on each of four rows in order before shifting the reading position by four codes in the row direction.

Abstract: Cyclic-redundancy-code (“CRC”) information that is received along with a frame from a fiber-channel is stored in an on-chip frame buffer, and later checked to ensure the integrity of the data while in the frame buffer. In various embodiments, data frames, along with their CRC information, are stored into a data-frame buffer, and/or non-data frames along with their CRC information are stored into a receive-non-data-frame buffer. The improved communications channel system includes a channel node having dual ports, each port supporting a fiber-channel arbitrated-loop serial communications channel. The serial communications channels each include CRC on data transmissions on the channel, an on-chip frame memory located on-chip in the channel node that receives a data frame and the frame's associated CRC from the communications channel, and an integrity apparatus that later uses the received associated CRC for data-integrity checking of data in the on-chip frame memory.

Abstract: Data read from a recording medium, such as a CD or DVD, is checked for errors and the errors are corrected in a fast and efficient manner. First, an error detection code (EDC) is appended to the data, which is arranged in matrix form, by performing a predetermined checking arithmetic operation. Then, a first checking operation is performed on the data using the EDC to generate a first sample value. The data is then error corrected in a first direction and a first correction value is generated if an error is detected. A second checking operation is performed in the first direction using the first correction value to generate a second sample value. The first and second sample values are compared and a first check value is generated. The data is then error corrected in a second direction and a second correction value is generated if an error is detected. A third checking operation is performed in the first direction using the second correction value to generate a third sample value.

Abstract: A system for storing and retrieving data utilizes a plurality of memory units having memory locations for storing data values. A checksum of a plurality of the data values in a particular checksum set is maintained in one of the memory locations. One of the plurality of data values can be recovered by combining each of the remaining plurality of data values with the checksum. After retrieving one of the plurality of data values during the data recovery process, steps are taken to ensure that any further attempts to access the location of the retrieved data value do not cause an update to the checksum. Therefore, the locations storing the data values of the checksum set may be accessed (e.g., read from or written to) during the data recovery process without causing errors to the data recovery process.

Abstract: A control store unit having a control store address generator able to provide both the normal control store address generation functions, and the BIST/logout address generation functions. In response to a test enable signal, the address generator switches between two modes: a normal mode and a test mode. Under the normal mode, normal control store addresses are generated. Under the test mode, a sequence of BIST/logout addresses are generated that sequentially cycles through the entire control store memory at full CPU speed.

Abstract: Information is transmitted to a network by a system which receives data from a first processor into a first FIFO and from a second processor into a second FIFO. Data exiting the first FIFO is discarded. As data is received into second FIFO, data exiting the FIFO is transferred to the network. When and end-of-message indication is detected in the received data, the contents of the FIFOs are compared. If a miscompare occurs, transferred data from the second FIFO to the network is caused to be in error. Accordingly, a message sent to the network from the second FIFO will be rejected either by the network or by a receiving node.

Abstract: Disclosed is a system for performing an operation, such as a read or write operation, on a data block in a shared disk system. A first adaptor receives a request to perform an operation on a data block maintained in a data storage location. The first adaptor then determines whether the first adaptor controls access to the data block. The first adaptor performs the requested operation on the data block after determining that the first adaptor controls access to the data block. If the first adaptor does not control access to the data block, then the first adaptor transmits a first message to a second adaptor that controls access to the data block and requests control of access to the data block. After receiving the first message, the second adaptor transfers control of access to the data block to the first adaptor. The second adaptor then transmits a second message to the first adaptor that the first adaptor controls access to the data block.

Abstract: A data storage system having a plurality of addressable memories for storing a global variable. Each one of a plurality of controllers is adapted to request an operation on first and second data stored in the addressable memories. Each one of the addressable memories includes: a control logic for receiving the operation request and addresses of the first and second data from one of the controllers; a random access memory; and a buffer memory coupled between the bus and a random access memory. The buffer memory has a write buffer memory adapted to store the first data in response to the control logic and a read buffer memory adapted to store the second data. The second data is read from the random access memory in response to the control logic. The buffer memory includes an operation selection section having a plurality of operation units configured to perform a different predetermined operation on the first and second data fed to a pair of input ports thereof.

Abstract: An integrated circuit multi-bit memory device incorporating an error check and correction (ECC) technique is provided. In the error correction, two or more groups of parity bits corresponding to a data word of the multi-bit memory device are programmed therein. The groups are classified by the number of bits per cell. Error bits in a memory data word are checked sequentially by the group, and the checked error bits are also corrected sequentially by the group, thereby preventing the device failure due to two or more errors in a data word of the multi-bit memory device.

Abstract: The bits of a data block are assigned to a plurality of logical groups such that at most one bit corresponding to a component is assigned to a logical group. This assignment ensures that a component failure may introduce at most one bit error to a logical group. A number of bits in a logical group is selected to reduce the number of check bits for a given number of data bits. Error correction may be performed within each logical group to correct single errors within the logical group. Because each logical group is assigned at most one bit corresponding to a component, component failures may be detected and corrected.

Abstract: To provide a semiconductor memory device having an ECC circuit whereof checker-data inspection of memory cells in the user areas and the ECC areas can be performed at once, the ECC code generation circuit generates the ECC code of six bits whereof logic of each bit has XOR logic of each of six different combinations of 15 bits of the data set of 32 bits, and addresses in every user areas of the bit-columns are arranged in an order of 1, 4, 2, 5, 3, 6, . . . , b, f. When a checkerboard pattern is written, a first data set having 32 bits of logic ‘0’ and a second data set having 32 bits of logic ‘1’ are written alternately, in addresses 4n to 4n+3 and 4(n+1) to 4(n+1)+3 of the user areas on odd-numbered word-lines, and written alternately on even-numbered word-lines in an inverse order of the odd-numbered word-lines, when checker-data inspection of the memory-cell array is performed, n being an integer not less than 0.

Abstract: An ATA-compatible drive interface with error correction and detection capabilities is disclosed. Being fully ATA backward compatible, this interface functions with the same physical cable and connectors as current ATA systems, employs bus drivers that are the same as or backward compatible with those provided by earlier versions of the ATA standard and uses signals with cable signal transitions no faster than those presently seen by current ATA devices. The error detection feature indicates when a data block is erroneously transferred between the device and host; the error correction feature identifies the words transmitted in error and corrects those words on the receiving side of the interface. So that ATA backward compatibility is maintained, the data integrity checking feature does not require additional words in a data transfer, and the data correction feature does not require new data transfer protocols or additional data transfer overhead.

Abstract: An apparatus for controlling addresses of symbol data obtained by demodulating a bit stream read from a disk for an error correction is provided.

Abstract: A system for detecting an initialization flag signal and distinguishing it from a normal flag signal having half the duration of the initialization flag signal. The initialization flag detection system may be included in the command buffer of a packetized DRAM that is used in a computer system. In one embodiment, the initialization flag detection system includes a pair of shift registers receiving the flag signal at their respective data inputs. One of the shift registers is clocked by a signal corresponding to an externally applied to command clock signal, while the other shift register is clocked by a quadrature clock signal. Together, the shift registers store a number of samples taken over a duration that is longer than the duration of the normal flag signal. The outputs of the shift registers are applied to a logic circuit, such as a NAND gate, that generates an initialization signal when all of the samples stored in the shift registers correspond to the logic levels of the flag signal.

Abstract: A network interface device includes a random access transmit buffer and a random access receive buffer for transmission and reception of transmission and receive data frames between a host computer bus and a packet switched network. The network interface device includes a memory management unit having read and write controllers for each of the transmit and receive buffers, where each write controller operates in a clock domain separate from the corresponding read controller. The memory management unit also includes a synchronization circuit that controls arbitration for accessing the random access memories between the read and write controllers. The synchronization circuit asynchronously monitors the amount of data stored in the random access transmit and receive buffer by asynchronously comparing write pointer and read pointer values stored in gray code counters, where each counter is configured for changing a single bit of a counter value in response to an increment signal.

Abstract: A storage subsystem for use in a data processing system having real and extended storage, a vector processor and a store-in cache buffer. Transfers between real and extended storage are performed with a store buffer external to the cache, but comparable in size to the line size of the cache directly associated with the real storage. Hard data errors in the cache are corrected with hardware invert-retry mechanism which operates in response to a machine check and does the correction as a part of the instruction retry. Vector processor storage operations bypass the cache and transfer data directly from storage to the vector processor.

Abstract: A method for counting the number of bits which are set to binary "1" in a word of length 2.sup.n includes generating a first mask of length 2.sup.n having alternating sequences of "1"'s and "0"'s, each sequence having a length "x" (the length "x" initially having a value of 1), and generating a second mask of length 2.sup.n by forming the complement of the first mask. Logical AND operations using the word and each of the first and second masks are performed to generate first and second intermediate words, respectively. That one of the first and second intermediate words having been ANDed with one of the first and second masks having a "0" in its least significant bit position, is shifted "x" number of bit positions to generate a shifted intermediate word. The shifted intermediate word and the other of the first and second intermediate words are arithmetically added to generate a bit-counted word of 2.sup.n length representing the number of bits in the word set to binary "1" from the bit-counted word.

Abstract: A method, circuit and apparatus is provided for preserving and/or correcting product engineering information. Non-volatile storage devices reserved for receiving product engineering bits can either be contained in at least three separate storage locations spaced from each other across the integrated circuit or, alternatively, be contained in a single storage location area with error correction bits and/or words added to that location. In the first instance, redundant product engineering bits are written to each storage location. Product engineering bits read from a majority of those locations which have identical values are deemed valid. The addition of extra bits and/or words can be combined with the possibly defective product engineering bits to correct errors in those bits.

Abstract: A recording apparatus provided on, for example, a digital audio tape recorder or on a data storage device for correctly and reliably recording data. An ECC unit 23 appends the parity for error correction to recording data and transmits the resulting data to recording heads Hw1, Hw2, while recording the parity in a RAM 61. The recording data and the parity are reproduced from a magnetic tape 32 by magnetic heads Hr1, Hr2 and supplied to a subcode separation unit 45. A syndrome detection unit 62 detects the number of error corrections performed by parity by an error correction unit 46. A system controller 63 compares the number of times of error corrections to a threshold value and compares the parity read out from the RAM 61 to the parity from the sub-code separation unit 45 in order to detect if the recording data has been recorded correctly. If the recording data has not been recorded correctly, the system controller controls a recording/reproducing unit 30 for re-recording the same recording data.

Abstract: The bits of a data block are logically partitioned into an array that includes a number of columns equal to a number of memory devices and a number of rows equal to a number of bits of the data block stored in each memory device. Each memory device contributes one bit to each row. In one embodiment, the bits from a memory device are stored in the same column position of all the rows. One check bit is associated with each row. The check bit is computed by taking the parity of the row associated with the check bit and zero or one column. Each column is assigned to at least four check bits. If a check bit has a column assigned to it, then the check bit is generated by computing the parity of the associated row and the column assigned to the check bit. Alternatively, if the check bit does not have a column assigned to it, the check bit is generated by computing the parity of the row assigned to the check bit only. Each column is assigned to at least four check bits and is assigned to an even number of check bits.

Abstract: A system and method for updating data. A first processing unit, such as an adaptor, receives a data update to a data block in a first storage device, such as a hard disk drive. Parity data for the data block is maintained in a second storage device, e.g., another hard disk drive. A parity group is comprised of the data block and corresponding parity data. The first processing unit determines whether the first processing unit controls access to the parity group, i.e., the state of lock ownership. The first processing unit transmits the data update to a second processing unit after determining that the first processing unit does not control access to the parity group. The second processing unit, another adaptor, performs an update after receiving the data update from the first processing unit. The first processing unit performs an update after determining that the first processing unit controls access to the parity group.

Abstract: A disc recording medium is provided for enhancing a capability of correcting a burst error caused by small dust left on the surface of a disc substrate. The data of two-dimensionally arrayed ECC blocks consisting of 172 words.times.192 rows contains the PI parity and the PO parity added in the two error-correcting systems. The PI parity is intended for error correction for data arranged to go down by one row with advance of one word in the direction of a bit stream. The PI parity is intended for going back to the first row when the data being interleaved exceeds 192 rows. The PO parity is intended for error correction for data arranged to interleave the data perpendicularly to the bit stream.

Abstract: A hard disk drive replaces a defective sector with a spare sector. When accessing a track having the defective sector, all normal sectors except for the defective sector are formerly accessed and then, a re-allocation sector which has replaced the defective sector is later accessed. In this manner, the number of searches is reduced during reading/writing (accessing) a track having defectives, thereby improving a data transmission of a hard disk drive.

Abstract: A memory system constructed in accordance with the invention receives data blocks and associated host LBAs from a host processor. The memory subsystem initially associates a check value with each received data block, each check value dependent upon a host LBA that is associated with the respectively received data block. The memory subsystem stores each received data block and associated check value as an "extended" data block. Thereafter, the memory subsystem, in response to a host processor request to access data corresponding to the associated host LBA, recovers the stored extended data block and determines from the check value stored therewith, if the address of the corresponding data and that provided by the host processor correspond. If the addresses correspond, the data block is transmitted to the host processor. If not, an error message is generated.

Abstract: In a transmission system or recording system, a detector (16,30) using quality measures indicating the quality of the received signal is applied.In contradistinction with the prior art system the quality measure comprises the deviation of the position of transitions in the input signal from the nominal positions of said transitions. The advantage of using this type of quality measure is that the required information for determining it, is already available within the PLL (34) needed for clock recovery.

Abstract: There is provided a disc array control method and apparatus for controlling access to a disc drive consisting of a plurality of second data obtained by dividing a first data and a plurality of discs for storing the error correction data for the second data. Particularly, the disc array control method and apparatus of the present invention determines the information consisting of disc storing a plurality of the second data and address on the disc, data size of a plurality of second data and disc storing the error correction data and address on the disc to make equal the time required for access to a plurality of second data and error correction data and executes the access to the disc drive on the basis of the determined information. Thereby, the time required for access to the error correction data and sub-blocks can be set to equal time and the real-time property can be assured while maintaining high reliability.

Abstract: A technique for encoding failing bit addresses in a memory array with redundant portions such as column slices. The address or other identification of a column slice or other portion of a memory array is identified to test logic using a wired-OR bus configuration. The technique assigns a code consisting of predetermined number of asserted bits to each portion of the memory. If a failure condition is detected, the code associated with that portion is asserted onto the bus. Because the code for each memory portion always has a given number of asserted bits, a multi-bit failure situation can be distinguished from a single bit failure situation by counting the number of bits asserted.

Abstract: The present invention relates to a disc array apparatus assuring that even if contradiction is detected in matching of parity data during a read parity check, correct host data is Restructured and can always be transferred to the host. The disc array apparatus of the present invention is particularly applicable to disc drives in the RAID configuration. For example, in a disc array apparatus of the present invention implementing RAID level 3, the disc array apparatus adds CRC data to data transferred from a host computer, divides the data, generates parity from the divided data, and stores the data and the parity data into the disc drives. During a read operation, the disc array apparatus of the present invention executes a read parity check.

Abstract: A remote monitoring system automatically communicates system diagnostic information from a monitored computer system to a remote service center at regular intervals. The remote monitoring system includes a plurality of monitored computers at a first location coupled together by a network. One of the monitored computers is a master and others of the monitored computers are slaves coupled to the master. The monitored computers store system diagnostic information resulting from execution of diagnostic programs. The diagnostic information from the slaves is collected at a memory location accessible by the master before the diagnostic information from all of the monitored computers is communicated to the remote monitoring computer at the second location. The remote monitoring computer receives the diagnostic information at predetermined intervals. The received diagnostic information is incorporated into a searchable database.

Abstract: A method and apparatus are described for providing error correcting code (ECC) which may be incorporated into a computer system which includes one of a plurality of memory configurations and which may include a pre-existing error control feature. A data store operation causes the receipt of a word including data bits and check bits generated by a pre-existing error control feature. The data and check bits of the received word are used to generate additional check bits based upon the configuration of the computer system memory. The additionally generated check bits are stored in the memory along with the received word. Upon a subsequent data fetch operation which retrieves the word and check bits the check bits are decoded thereby providing error detection and correction in the retrieved word for single and multiple bit errors including the failure of an entire memory chip.

Abstract: The present invention pertains to a method for determining if data read from a storage medium has been read from physical block address (PBA) other than the expected PBA. Data that is stored on the data storage medium is encoded in accordance with a protocol that includes randomizing the data and combining the first k.times.2t bytes of the data with a PBA string, where t is the error correction capacity associated with the error correction technique used in the data storage system and k is the number of bytes of the PBA that are used in the PBA string. In addition, the data is k-way interleaved with parity data appended to it. When the data is read from the data storage medium, the data is decoded using a scheme corresponding to the encoding protocol. If errors are present in the data and exceed the error correction capacity, the first 2t bytes of each interleave are marked as erasures and a second correction is performed by an error correction unit.

Abstract: A method and apparatus are described for providing error correcting code (ECC) which may be incorporated into a computer system which includes one of a plurality of memory configurations and which may include a pre-existing error control feature. A data store operation causes the receipt of a word including data bits and check bits generated by a pre-existing error control feature. The data and check bits of the received word are used to generate additional check bits based upon the configuration of the computer system memory. The additionally generated check bits are stored in the memory along with the received word. Upon a subsequent data fetch operation which retrieves the word and check bits the check bits are decoded thereby providing error detection and correction in the retrieved word for single and multiple bit errors including the failure of an entire memory chip.