Abstract: Provided is a memory system and wear-leveling method. A memory system includes a flash memory device and a memory controller. The flash memory device includes a plurality of memory blocks, each including a plurality of memory cells. The memory controller is configured to control the flash memory device based on erase event information and error checking and correction (ECC) event information of each of the memory blocks such that use of the memory blocks is distributed more uniformly.

Abstract: An electronic system includes a counter and a first component. The first component includes a reset input configured to receive a reset event, an interface to a communications interface coupleable to a second component, an error detection module configured to initiate the counter in response to detecting an error in a first communication from the second component, and an event logging module. The event logging module is configured to store a first indicator representative of the counter value of the counter in response to receiving the reset event via the reset input and configured to store a second indicator representative of the error at the communications interface. The counter is initiated at the first component in response to detecting an error in a first communication from the second component. A counter value of the counter is determined in response to detecting a reset event at the first component subsequent to detecting the error in the first communication.

Abstract: A system and method of identifying and storing memory error locations is disclosed. In one form, a method of using a memory is disclosed. The method can include detecting a memory error during execution of a run time environment within an information handling system, and determining if the memory error is a correctable memory error. The method can also include identifying a first memory location within a first memory device causing the memory error, and storing a first reference to the first memory location within a persistent memory. The method can further include disabling use of the first memory location during use of the run time environment.

Abstract: Methods and system for exception detecting and alerting are described. An exception indicating an occurrence of an error in an application and a path to the exception in an application space may be received. The received exception may be compared to a stored exception in a prior version of an exception data structure to determine whether the received exception is a new exception. The exception data structure may include a plurality of stored exceptions. The results of the comparison may be provided.

Abstract: A method and apparatus for implementing static random access memory (SRAM) cell write performance evaluation, and a design structure on which the subject circuit resides are provided. ASRAM core includes each wordline connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state machine controls operations for the SRAM cell write performance evaluation circuit including the ring oscillator circuit and the SRAM core. A control signal is applied to the state machine to select a first write operation, where the circuit simultaneously writes all the cells to a known state with wide wordlines to ensure all cells are written. Then a second write operation is selected, and all the wordlines are launched simultaneously to write the cells to the opposite state. From these write operations, a required wordline pulse width to write the cell is identified.

Abstract: One or more switches are interposed between a controller portion and a storage device. When transmission of a command to a certain storage device fails, a command is transmitted starting from an upstream side to a downstream side of a path between the controller portion and the switch to which the certain storage device is connected, and when command transmission fails while transmitting a command from a kth switch (k is an integer of 0 or more) which is connected to a (k+1)th switch and is one level upstream of the (k+1)th switch or from any port of the controller portion, it is determined that a failure has occurred in a power source that supplies power to the (k+1)th switch.

Abstract: A method for detecting word line leakage in a memory device includes coupling a first plurality of word lines in the memory device to a voltage source while grounding a second plurality of word lines. Each of the second plurality of word lines is adjacent to a corresponding one of the first plurality of word lines. The method includes waiting for a period of time to allow the word lines to reach a predetermined read voltage level. The method also includes decoupling the first plurality of word lines from the voltage source and waiting for a second predetermined period of time to allow the first plurality of word lines to discharge. The method further includes sensing a current associated with the word lines, and comparing the current with a predetermined reference current which is selected for identifying a word line leakage condition associated with the first plurality of word lines.

Abstract: An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to functional circuits (702) on the integrated circuit and receive response test data from the functional circuits. A scan distributor circuit (800) receives serial test data from a peripheral bond pad (802) and distributes it to each parallel scan path. A scan collector circuit (844) collects test data from the parallel scan paths and applies it to a peripheral bond pad (866). This enables more parallel scan paths of shorter length to connect to the functional circuits. The scan distributor and collector circuits can be respectively connected in series to provide parallel connections to more parallel scan paths. Additionally multiplexer circuits (886,890) can selectively connect pairs of scan distributor and collector circuits together.

Abstract: Disclosed are embodiments that provide near real-time monitoring of a control application in a manufacturing environment to detect and determine the root cause of faults within the control application. The embodiments monitor the flow of data within the control application during events (i.e., transactions, stages, process steps, etc.). By comparing a dataflow path for a near real-time event with historical dataflow path records, dataflow interruptions (i.e., fails) within the control application can be detected. By determining the location of such a dataflow interruption, the root cause of the control application fail can be determined. Additionally, the invention can generate summary reports indicating the status of the control application. For example, the summary reports can quantify the performance and/or the effectiveness of the control application. These summary reports can further be generated with drill downs to provide a user with direct access to the records upon which the reports were based.

Abstract: A specific-equipment management system is equipped with a question generator, a display unit and an input unit and manages a water heater. The water heater is equipment that requires human operation in the vicinity when used. The question generator generates question information. The question information is information regarding a question for specifying a specific-error. The “specific-error” is an error regarding the water heater and includes an error regarding the human operation. The display unit displays the question information. Response information is then inputted to the input unit by the user based on the question information displayed at the display unit. The response information is information regarding the state of the water heater or the state of the human operation. The question generator generates next question information based on the response information. The display unit then displays the next question information.

Abstract: A method, system, and computer program product for fault data correlation in a diagnostic system are provided. The method includes receiving the fault data including a plurality of faults collected over a period of time, and identifying a plurality of episodes within the fault data, where each episode includes a sequence of the faults. The method further includes calculating a frequency of the episodes within the fault data, calculating a correlation confidence of the faults relative to the episodes as a function of the frequency of the episodes, and outputting a report of the faults with the correlation confidence.

Abstract: A defect management method for a storage medium is provided. An initial check is performed on the storage medium, and then diving the storage medium into blocks, which at least include a using data area with endurance blocks. Each endurance block is given an initial endurance value. Then, an endurance table is established in the storage medium for recording endurance blocks and the initial endurance values. According to the endurance table, data is written to the storage medium based on its importance. When the writing cycles reach a predetermined times, the endurance values are recalculated and the table is updated accordingly. Data is then moved according to the new endurance values.

Abstract: In one embodiment, an integrated circuit comprises first circuitry; a first clock generator coupled to supply a first clock to the first circuitry, and a control unit coupled to the first clock generator. The first clock generator is coupled to receive an input clock to the integrated circuit and is configured to generate the first clock. The control unit is also coupled to receive a trigger input to the integrated circuit. During a test of the integrated circuit, the control unit is configured to cause the first clock generator to generate the first clock at a first clock frequency, The control unit is configured to cause the first clock generator to generate the first clock at a second frequency greater than the first clock frequency for at least one clock cycle responsive to an assertion of the trigger input.

Abstract: Methods, apparatus, and products are disclosed for link failure detection in a parallel computer including compute nodes connected in a rectangular mesh network, each pair of adjacent compute nodes in the rectangular mesh network connected together using a pair of links, that includes: assigning each compute node to either a first group or a second group such that adjacent compute nodes in the rectangular mesh network are assigned to different groups; sending, by each of the compute nodes assigned to the first group, a first test message to each adjacent compute node assigned to the second group; determining, by each of the compute nodes assigned to the second group, whether the first test message was received from each adjacent compute node assigned to the first group; and notifying a user, by each of the compute nodes assigned to the second group, whether the first test message was received.

Abstract: A method and apparatus are provided for diagnosing faults in a monitored system. Estimates of parameter data are generated from the system with reference parameter data characteristic of known behavior of the system. The generated estimates of the parameter data are compared with measured parameter data. A residual is determined for each of the parameters based on a relationship between the estimates of the parameter data and the measured parameter data. A fuzzy classification rule is implemented to determine a likelihood that a predetermined fault exists by using residuals for parameters used to indicate the existence of the predetermined fault.

Abstract: An information handling system includes first and second input/output (I/O) controllers, a detector for detecting an I/O controller failure, and an I/O recovery unit. The first I/O controller adaptively controls a first and a second I/O slot. The second I/O controller adaptively controls a third and a fourth I/O slot. Lastly, the I/O recovery unit, responsive to a detected I/O controller failure, operatively couples/decouples the first and second I/O slot to/from the first I/O controller, operatively couples/decouples the third and fourth I/O slot to/from the second I/O controller, and operatively decouples/couples the first and second I/O slot from/to the third and fourth I/O slot according to an I/O failure recovery protocol, the I/O failure recovery protocol provided for adapting one of either the first and second I/O controllers to operatively couple to the first, second, third and fourth I/O slots as a function of the detected I/O controller failure.

Abstract: A mechanism is provided for discovering and isolating failure of high speed traces in a manufacturing environment. The mechanism utilizes transmit pre-emphasis and receiver equalization in combination with attenuated wrap plugs to enhance discovery and isolation of manufacturing defects in the manufacturing environment. The mechanism adjusts pre-emphasis and equalization in real time in high speed devices, allowing for much greater variation to compensate for design margins and specification variances. While the card is under test with wrap-backs installed, the pre-emphasis and receiver equalization are brought to the limits while logging the bit error rate to a non-volatile memory element. The mechanism then compares the bit error rate information to empirically derived signatures for failure isolation.

Abstract: For realizing an optimum failover in NAS, this invention provides a computer system including: a first computer; a second computer; a third computer; and a storage device coupled to the plurality of computers via a network, in which: the first computer executes, upon reception of an access request to the storage device from a client computer coupled to the plurality of computers, the requested access; and transmits to the client computer a response to the access request; the second computer judges whether a failure has occurred in the first computer; obtains load information of the second computer; obtains load information of the third computer from the third computer; and transmits a change request to the third computer when the obtained load information satisfies a predetermined condition; and the third computer judges whether a failure has occurred in the first computer when the change request is received from the second computer.

Abstract: An invention is provided for ensuring data integrity in a non-volatile memory system, including boot block data integrity during Power On Reset. The invention includes loading data into a buffer, such as a flash buffer, and generating an error detection code for the data utilizing a check code generator located in the memory controller. The error detection code is compared to a previously stored error detection code associated with the data. Then, when the error detection code is different from the previously stored error detection code, a correction pattern is calculated and applied to the data directly in the buffer for the non-volatile memory.

Abstract: Methods and devices operate to apply and provide differing levels of error correction within a multi-level, non-volatile memory. In an example, the differing level of error correction is provided within one page of a row of multi-level cells relative to other pages stored within the same row of multi-level cells.

Abstract: Apparatus for passively tracking expired data in a dynamic memory includes a time stamp memory configurable for storing information relating to a refresh status of one or more corresponding data entries in the dynamic memory. The apparatus further includes a timer configurable for defining a desired window of time in which a refresh operation of data in the dynamic memory is to occur in order to ensure that the data is valid. Control circuitry is coupled to the time stamp memory and to the timer. The control circuitry is operative to manage the information stored in the time stamp memory relating to the refresh status of the one or more corresponding data entries in the dynamic memory.

Abstract: A memory device (memory module) having one or a plurality of memory chips is disclosed. By including in a memory chip an error generation part to generate an error, an error is generated in a specific area of a memory in accordance with an address specification, thereby confirmation of an ECC function is facilitated. The error generation part includes an error code generation part that generates an error code. The memory chip is configured by one or a plurality of memory matrixes.

Abstract: Systems, controllers and methods are disclosed, such as an initialization system including a controller that receives patterns of read data coupled from a memory device through a plurality of read data lanes. The controller is operable to detect any lane-to-lane skew in the patterns of read data received through the read data lanes. The controller then adjusts the manner in which the read data received through the read data lanes during normal operation are divided into frames. The controller can also couple patterns of command/address bits to the memory device through a plurality of command/address lanes. The memory device can send the received command/address bits back to the controller through the read data lanes. The controller is operable to detect any lane-to-lane skew in the patterns of command/address bits received through the read data lanes to adjust the manner in which the command/address bits coupled through the command/address lanes during normal operation are divided into frames.

Abstract: It is possible to save storage resources. A loss compensation device for compensating a loss in periodical signals when the loss occurs in an arbitrary section of the periodical signals which are divided into predetermined sections and received in time series, includes: a periodical signal storage which stores one or more sections of newly received periodical signals for a predetermined period of time; a loss detector which detects a loss of each section of the periodical signals; and an element periodical signal generator which generates a plurality of element periodical signals for interpolation having different waveforms, in accordance with the periodical signals stored in the periodical signal storage, at time of detection of the loss if the loss is detected by the loss detector. The plurality of element periodical signals generated by the element periodical signal generator are synthesized, and a result of the synthesizing is arranged at the section where the loss in the periodical signals has occurred.

Abstract: An apparatus and method for processing a data signal is provided. An acquisition unit of a test instrument acquires a data signal for a predetermined time. The data signal is stored in a memory of the test instrument and a clock recovery unit recovers a clock signal from the stored data signal. The stored data signal is sliced by a processor into a plurality of data segments of a predetermined length in accordance with the recovered clock signal.

Abstract: Disclosed is a reconfigurable device including at least a bus that mutually connects functional blocks, a configuration information memory disposed corresponding to each of the functional blocks, an error detection circuit that detects an error in the configuration information memory, and a buffer which is on-off controlled based on information stored in the configuration information memory and each of which controls connection between each of the functional blocks and each bus. When an error in the configuration information memory is detected by the error detection circuit, the buffer with an output thereof connected to the bus is set to an off-state, based on a result of error detection.

Abstract: Embodiments of the invention relate to methods and systems for error detection and recovery from errors during pipelined execution of data. A cascaded, delayed execution pipeline may be implemented to maintain a precise machine state. In some embodiments, a delay of one or more clock cycles may be inserted prior to a write back stage of each pipeline to facilitate error detection and recovery. Because a precise machine state is maintained error detection and recovery mechanisms may be built directly into register files of the system. If an error is detected execution of the instruction associated with the error and all subsequent instructions may be restarted.

Abstract: Disclosed are a method and system for detecting errors in a computer system including a processing unit to perform tasks to change items. The method comprises the steps of assigning a task control block to the processing unit, and using the task control block to keep track of items being changed by the processing unit. The method comprises the further steps of at defined times, checking the task control block to identify items being changed by the processing unit, and checking the states of said identified items to determine if those states are correct. The preferred embodiment of the invention detects an error when it arises (where possible), and utilizes an infrastructure that allows simple and periodic consistency checks (for example, at designated code points) that detect the error before it causes follow-on problems.

Abstract: A method is described for debugging reconfigurable hardware. In one example embodiment, debugging information is written for each configuration cycle into a memory which is then evaluated by a debugger.

Abstract: The embodiments generally relate to systems and methods for determining changes in a directory schema. In embodiments, directory changes are recorded in a change log. The change log may have one or more entries. A determination is made as to which change log entries should be retrieved. Once retrieved, the directory schema changes are determined. In embodiments, the directory changes are then interpreted for presentation to a user.

Abstract: A method and a device for performing switchover operations and for comparing data in a computer system having at least three processing units are provided, in which switchover unit is provided, a switchover operations being carried out between at least two operating modes, and a comparison unit is provided. A first operating mode corresponding to a comparison mode, and a second operating mode corresponding to a performance mode are provided. Provision is made in the comparison mode for a voting, at least as a two-out-of-three weighting, and a control unit is provided which may be used to set the voting.

Abstract: The present invention provide a debug circuit which has a structure in which a conversion block latches plural internal signals which are supposed to be effective in finding a cause of a malfunction and are outputted from a selection block, using a signal that is outputted from a timing generation block, converts these signals into serial data, and outputs the serial data to an output block, thereby observing plural signals in the LSI using fewer external pins, and performing analysis of the malfunction of the LSI speedy and reliably.

Abstract: In one embodiment a computer system comprises a processor, a memory controller, one or more memory modules coupled to the memory controller via a communication link, and a memory agent coupled to the communication link between the memory controller and the one or more memory modules, wherein the memory agent provides services to the memory controller.

Abstract: Applications that utilize a database are managed through the use of meta-metadata. The database contains multiple database objects. Each database object has metadata that describes one or more operational characteristics of that database object. Each metadata has an associated meta-metadata, which describes a variance to the metadata. An application program is provided access to one or more database objects. If a change in behavior occurs for the application program that has accessed the database objects, the meta-metadata for the accessed database objects is correlated with the application program accessing the database objects.

Abstract: In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.

Abstract: A scan including data and shift inputs, and input selection circuitry for selecting between the data and shift inputs during normal, capture, and shift modes in response to only a first control signal and a second control signal. The input selection circuitry includes a first storage element for storing a bit representing a state of the first control signal in response to a change in state of the second control signals and multiplexing circuitry. The multiplexing circuitry is operable in the normal mode to select the data input in response to a first state of the second control signal, in the capture mode to select the data input when the bit stored in the first storage element represents a first state of the first control signal, and in the shift mode to select the shift input when the bit stored in the first storage element represents a second state of the first control signal.

Abstract: Techniques are provided for automatically tracking errors encountered by a software system. An occurrence of an error that affects performance of an operation being performed by a database server is detected. In response to detecting the occurrence, error information about the error is automatically recorded in a storage space within a database that is managed by the database server. The error information is automatically recorded by executing one or more computer instructions in a first code path of the database server, where the first code path is a separate code path than a second code path of the database server that performs the operation whose performance is affected by the error.

Abstract: A system automates the process of isolating incorrect, corrupt, or sensitive data and skipping duplicate records caused by violations of application business rules during report generation, for example. A data processor provides data for processing for incorporation in a report by, processing received report data to identify data objects in the report data likely to generate errors in preparation of a report based on the report data and providing validated report data by collating received report data and omitting identified data objects likely to generate errors. The data processor communicates the validated report data for storage in a repository for use in preparation of a report. An error data processor provides information indicating identified data objects in the report data likely to generate errors and a corresponding reason an individual data object is likely to cause an error.

Abstract: A method for efficiently calculating syndromes in Reed-Solomon decoding is adapted to be implemented in a processor having a parallel processing instruction set. The method includes: (a) initializing a syndrome vector; (b) obtaining a symbol from a Reed-Solomon block code; (c) finding a lookup index based on the symbol; (d) using the parallel processing instruction set, obtaining a finite field product vector Corresponding to the lookup index from a finite field vector multiplication table that includes at least one finite field product vector; (e) using the parallel processing instruction set, performing vector finite field addition on the finite field product vector corresponding to the lookup index and the syndrome vector, thereby obtaining an updated syndrome vector; and (f) outputting the updated syndrome vector.

Abstract: The present invention provides a method and apparatus for detecting video data errors, said video data including a plurality of successive frame image data, said method comprising the steps of acquiring the processing sequence information of two frame image data in said video data, said two frame image data being immediately adjacent in the processing sequence, one after the other, determining the processing sequence information difference between two frame image data, comparing said information difference with a reference value and judging, based on said comparison result, whether there is a frame image data miss between said two frame image data. The method and apparatus provided by the invention can, not only judge whether there is a frame image data missing between the two immediate adjacent frames, but also determine the amount of the missing frame image data and performs a restoring and correcting process.

Abstract: A method and apparatus is described for generating a test case for an application or system modelled using a Stochastic Automata Network model. The method contemplates the inclusion of a plurality of automata and including the steps of: (a) setting an initial global state as the current global state, wherein a global state comprises a set of local states each corresponding to one of the automata; (b) creating a record of the initial global state; (c) selecting an event from a set of events that can be applied to the current global state; creating record of the selected event; (e) identifying those of the automata affected by the selected event and updating the current global state by updating the states of the affected automata; (f) creating a record of the current global state; and repeating steps (c) to (f) until a termination condition is satisfied. The invention may also be used for the generation of test scripts.

Abstract: A testing circuit has scan chain segments (62,64,60) defined between parallel inputs (wpi[0] . . . wpi[N?1]) and respective parallel outputs (wpo[0] . . . wpo[N?1]). The scan chain segments comprise a bank (62) of cells of a shift register circuit, a core scan chain portion (62), a first bypass path around the core scan chain portion (62) and a second bypass path around the bank (60) of cells of the shift register circuit. This architecture enables loading of data in parallel into the core scan chain, or into the shift register (WBR). In addition, each scan chain segment also has a series latching element (80), and this provides additional testing capability. In particular, the shifting of data between the latching elements (80) can be used to test the bypass paths while the internal or external mode testing is being carried out. This testing can thus be part of a single ATPG procedure.

Abstract: Systems for providing automated diagnosis of problems for an electronic network include a central diagnosis engine configured to include modules that rank identified policy/configuration changes into potential causes, verify the ranked potential causes and determine whether any of the ranked potential causes is a likely cause or contributor to the problem. An estimator module is configured to calculate distances associated with the ranked potential causes such that a list of potential causes of the problem can be presented in order of likelihood. Other systems and methods are also provided.

Abstract: A digital data recording/reproducing method includes the steps of: interleaving data on a PI code for each PI code of a 208-row ECC block; and converting a short burst error into random errors by dispersing errors on the PI codes. Moreover, the digital data recording/reproducing method increases correction capability against several bytes to several tens bytes of errors generated at random without changing burst error correction length by performing this processing for respective PI codes by using interleave rules that are different as much as possible from one another.

Abstract: A digital data recording/reproducing method includes the steps of: interleaving data on a PI code for each PI code of a 208-row ECC block; and converting a short burst error into random errors by dispersing errors on the PI codes. Moreover, the digital data recording/reproducing method increases correction capability against several bytes to several tens bytes of errors generated at random without changing burst error correction length by performing this processing for respective PI codes by using interleave rules that are different as much as possible from one another.

Abstract: A digital data recording/reproducing method includes the steps of: interleaving data on a PI code for each PI code of a 208-row ECC block; and converting a short burst error into random errors by dispersing errors on the PI codes. Moreover, the digital data recording/reproducing method increases correction capability against several bytes to several tens bytes of errors generated at random without changing burst error correction length by performing this processing for respective PI codes by using interleave rules that are different as much as possible from one another.

Abstract: The systems and methods describe a self healing framework (SHF) that can monitor errors in a computing system and can resolve the errors and/or suggest methods for resolving the errors to a user based on a heuristic approach. In addition, the SHF can analyze errors that occurred in the past and can predict such occurrences in the future to help users take proactive actions against possible errors.

Abstract: A method for easily detecting a memory error that may occur when a memory is accessed or an allocated memory is freed in the process of developing software is disclosed. The memory error detecting method includes: (a) generating an original block indication variable for indicating a starting memory block of a memory region allocated with respect to a variable included in a computer program; (b) detecting a memory error that may occur when the allocated memory region is accessed, by performing a certain operation (computing or arithmetic operation), before the allocated memory region is accessed, using a target block indication variable indicating memory block to be accessed in the allocated memory region and/or the original block indication variable; and (c) outputting information about a detected memory error.

Abstract: A data communication arrangement permits efficient data transfer between a controller module and multiple target modules using a two-phase protocol. The controller module and the target modules can each reside in separate clock domains. Consistent with one example embodiment, a data communication arrangement includes a plurality of target modules, and a first XOR tree arranged to provide a first data integrity-indicating signal and to respond to a respective second data integrity-indicating signal from each of the target modules. A second XOR tree is arranged to provide a first data bus and to respond to a respective second data bus from each of the target modules. Also, a controller module used to determine availability of data on the first data bus in response to the first data integrity-indicating signal.

Abstract: An apparatus, program product and method checks for nodal faults in a group of nodes comprising a center node and all adjacent nodes. The center node concurrently communicates with the immediately adjacent nodes in three dimensions. The communications are analyzed to determine a presence of a faulty node or connection.