Abstract: A method for detecting microprocessor hardware faults includes sending at least one input signal to a logic block within the microprocessor, collecting an output response to the input signal from the logic block, and determining whether the output response matches an expected output response of the logic block.

Abstract: Apparatus and methods provide at least redundant control information such as control symbols and control data over respective channels, such as differential lanes, and skew at least the redundant control information in time between the plurality of transmission circuits. Non-control information such as video and/or audio data may also be skewed. Corresponding receiver circuits and methods are also disclosed.

Abstract: Embodiments relate to systems and methods for generating a machine state verification using a number of installed package objects. A physical or virtual client machine can host a set of installed software packages, including operating system, application, and/or other software. A package manager installed on the client machine can track the installed package complement, and updates available for those packages. To verify that a target of a package update is prepared and in the correct state to receive the update, the package manager inventory the set of package objects installed on the client machine. The resulting sum can be reported to a remote management platform, such as a package server. The counted package objects can be the packages themselves, and/or their set of component files. Machines having a package sum that does not match an expected target number can have a package re-installation performed, and/or other diagnostics carried out.

Abstract: Apparatus, systems, and methods may operate to authenticate a desktop client to an identity service (IS), to receive a request, from an application, at the IS via the desktop client for a virtual service internet protocol (IP) address associated with a service. The IS may operate to build a routing token that includes an original physical IP address associated with the service when a policy associated with the IS permits access to the service by a user identity associated with the desktop client. After the routing token is validated, the application may be connected to the service via the desktop client. The application may comprise an e-mail application or a remote control application, such as a virtual network computing (VNC) application. Additional apparatus, systems, and methods are disclosed.

Abstract: The present invention relates to a new error control paradigm in a packet switched network that is particularly advantageous for multicast transmission. A transmission Status Vector TSV (T) is updated at the sender side whenever a new outgoing data packet (Dj?1) is scheduled for transmission. A corresponding Reception status Vector RSV (R) is similarly updated at the receive side whenever a new incoming and correctly indexed data packet (Dj?1) is validly received. As soon as a missing or corrupted data packet (Dj) is detected, the update of the RSV is suspended. A request is then sent to the sender to get the current Tsv's value, or a part thereof. The erroneous data packet is then recovered from the current TSV's value (Sk,m), from the lastly updated RSV's value (Sj-1), and from otherwise validly received data packets (Dj+1, . . . , Dk).

Abstract: The embodiments described herein provide a method and controller for performing a copy-back command. In one embodiment, a controller receives the data and error correction code associated with a copy-back operation from at least one flash memory device. The controller determines if the error correction code indicates there is an error in the data. If the error correction code does not indicate there is an error in the data, the controller sends a destination address and copy-back program command received from a host to the at least one flash memory device. If the error correction code indicates there is an error in the data, the controller corrects the data and sends the destination address, the corrected data, and a program command to the at least one flash memory device. Additional embodiments relate to modifying data during the copy-back operation.

Abstract: An error controlling system includes a plurality of error generation target circuits, a plurality of pseudo error generating devices each having a pseudo error content holding register that holds directed pseudo error content, each plurality of pseudo error generating device generates a pseudo error corresponding to a pseudo error content held in a respective pseudo error content holding register in at least one of data to be written to one of the plurality of error generation target circuits and data to be read from one of the plurality of error generation target circuits upon being directed to generate the pseudo error, and a pseudo error controlling device that directs the plurality of pseudo error generating devices to generate a pseudo error corresponding to a respective pseudo error content held in each of the pseudo error content holding register provided in each of the plurality of pseudo error generating devices.

Abstract: A system and method for detecting hold path faults in an integrated circuit is provided in exemplary embodiments. These exemplary embodiments introduce a method of identifying data paths within an integrated circuit with statistically the highest timing slack among the data paths within the integrated circuit that cover the entire process space of the circuit. By identifying these paths (i.e., shortest data paths), a robust test pattern can be generated that directly tests for hold path faults on short data paths within the integrated circuit using one functional clock pulse.

Abstract: An apparatus and method are provided for performing verification tests for a design of a data processing system. The apparatus comprises a system under verification representing at least part of the design of the data processing system, and a transactor for connecting to an interface of the system under verification, and for generating signals for input to the system under verification via the interface during performance of the verification tests. Profile storage stores a profile providing a statistical representation of desired traffic flow at the interface, the statistical representation providing statistical information for a plurality of traffic attributes and also identifying at least one dependency between such traffic attributes. The transactor then references the profile in order to determine the signals to be generated, such that the signals generated take account of the specified dependencies identified in the profile.

Abstract: A flash memory device comprises a plurality of memory cells each configured to store k-bit data, where k is a natural number greater than one. The device is programmed by a method comprising reading (i?1)-th order data from a selected memory cell connected to a selected wordline before programming i-th order data in one or more adjacent memory cells connected to an adjacent wordline, wherein i is a natural number between two and k, storing as read data the (i?1)-th order data read from the selected memory cell, and programming i-th order data in the selected memory cell based on the stored read data.

Abstract: A set of log entries is automatically inspected to determine a bug. A training set is utilized to determine clustering of log identifications. Log entries are examined in real-time or retroactively and matched to clusters. Timeframe may also be matched to a cluster based on log entries associated with the timeframe. Error indications may be outputted to a user of the system in respect to a log entry or a timeframe.

Abstract: A method implemented in a test system comprises a test debug system and a target system, said target system comprising a test access port that functions according to a plurality of states and also comprising an adapter. The method comprises the adapter transferring data to the test debug system while the test access port remains in a predefined state. The predefined state comprises a state in which no scans occur.

Abstract: A SRAM (Static Random Access Memory) macro test flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a master latch circuit and a slave latch circuit. The master latch circuit includes a master feed-back circuit including a master storage node and a master feed-forward circuit. The slave latch circuit includes a slave feed-back circuit including a slave storage node and a slave feed-forward circuit driven from the master latch. The scan control circuit includes a scan slave feed-forward circuit, a scan latch circuit, and a scan driver circuit driven by the scan feed-back circuit. The scan latch circuit includes a scan feed-back circuit comprising a scan storage node and a scan feed-forward circuit driven from the slave latch. The output buffer circuit includes a master driver driven from master latch circuit and a slave driver driven from slave latch circuit.

Abstract: An improvement to an integrated circuit of a type having a test enable line for enabling an electrical test of the integrated circuit only when the test enable line is at a logical high value, and output lines that are only used during the electrical test of the integrated circuit, where the improvement is a switch circuit for disabling a state change in the output lines when the test enable line is at a logical low value. In this manner, the output lines do not switch during functional use of the integrated circuit, and cannot be aggressors on the data signals that are carried by the data lines that are used during the functional use of the integrated circuit. In addition, these non-switching output lines can act as guard traces that run between the data lines, further electrically isolating the data lines from one another. Further, because they do not switch during functional use of the integrated circuit, the overall power consumption of the integrated circuit is reduced.

Abstract: A method and system to increase the throughput of a HARQ protocol in a wireless network. When a station receives a downlink HARQ sub-burst that has an incorrect cyclic redundancy check, it determines if there is an overflow event of its buffer. If so, the station reduces the size of the HARQ sub-burst to be stored in the buffer and stores the resized HARQ sub-burst in the buffer. When the station transmits an uplink HARQ sub-burst, the station can reduce the size of the transmitted HARQ sub-burst if it exceeds the size of the buffer. The amount of buffer required in the station can also be reduced by representing each log likelihood ratio (LLR) value of each of one or more bits of each symbol of a HARQ burst with a number of quantization bits based on a metric sensitivity to noise of each bit of each symbol.

Abstract: Errors induced by noise pulses in digital electronic circuits clocked with a clock signal are detected by providing at least one additional clock signal offset in time with respect to the clock signal by a given interval, and performing for at least one component of the circuit a comparison of correspondence between two versions of one and the same signal. The comparison is clocked by the additional clock signal and the absence of correspondence between the two versions of said signal identifies an error induced in the circuit by a noise pulse.

Abstract: A motherboard error detection system includes a pluggable error detection board and a motherboard having a boot management chip. When the motherboard enters a device-driven status from a standby status, the boot management chip is used to manage power-on timings of different voltage sources; to collect a plurality of sets of status information; and to check whether the sets of status information and the power-on timings have errors. The pluggable error detection board includes an interpreting unit, a message-reading interface and a connector which is pluggably disposed on the motherboard. When the boot management chip notifies the pluggable error detection board to read an error message, the interpreting unit converts the error message to human-readable information, and the human-readable information is outputted through the message-reading interface.

Abstract: A method and system for detecting errors in stored pattern definitions. The method describes structuring a pattern definition into a specified format and creating a pattern definition file. The structured pattern definition contents are hashed to generate a filename for the pattern definition file. This filename, along with a corresponding identifier, is added to an identifier document. Each filename in the identifier document is compared with all other filenames to determine a degree of overlap. A potential error is indicated if a filename substantially matches any of the other filenames in the identifier document.

Abstract: An integrated circuit including a logic analyzer with enhanced analyzing and debugging capabilities and a method therefor. In one embodiment of the present invention, an embedded logic analyzer (ELA) receives a plurality of signals from a plurality of buses within an integrated circuit (IC). The ELA includes an interconnect module to select a trigger signal and/or a sampled signal from the plurality of received signals. A trigger module sets at least one trigger condition and detects if the trigger signal satisfies the at least one trigger condition. When the trigger condition is satisfied, an output module performs at least one task based upon the satisfied at least one trigger condition. If a sampling process is initiated by the output module, the plurality of sampled signals is sampled and may be stored in a memory. The capability of the output module to perform multiple user-defined tasks enhances the debugging capability of the ELA and makes it more versatile.

Abstract: A system and method for management of jobs in the clustered environment is provided. Each node in the cluster executes a job manager that interfaces with a replicated database to enable cluster wide management of jobs within the cluster. Jobs are queued in the replicated database and retrieved by a job manager for execution. Each job manager ensures that jobs are processed through completion or, failing that, are requeued on another storage system for execution.

Abstract: A system and method are provided for planning and controlling a plurality of machines. A mission is assigned to each machine of the plurality of machines. A plurality of system capabilities is computed in each machine and, from the plurality of computed system capabilities, a machine mission capability is computed for each machine. The mission of one or more of the machines may be selectively reassigned based on the computed machine mission capability of each machine.

Abstract: A network communication device includes a host interface, which is coupled to communicate with a host processor, having a memory, so as to receive a work request to convey one or more data blocks over a network. The work request specifies a memory region of a given data size, and at least one data integrity field (DIF), having a given field size, is associated with the data blocks. Network interface circuitry is configured to execute an input/output (I/O) data transfer operation responsively to the work request so as to transfer to or from the memory a quantity of data that differs from the data size of the memory region by a multiple of the field size, while adding the at least one DIF to the transferred data or removing the at least one DIF from the transferred data.

Abstract: A portable executable file can be repaired by identifying an invalid field of a portable executable file. A likelihood of repairing the invalid field of the portable executable file is determined. A repair model for repairing the invalid field of the portable executable file is generated, and the invalid field of the portable executable file is repaired based upon, at least in part, the repair model.

Abstract: A method, device, and system are disclosed. In one embodiment method includes determining a left edge and right edge of a valid data eye for a memory. The method continues by periodically checking the left and right edges for movement during operation of the memory. If movement is detected, the method retrains the valid data eye with an updated left edge and right edge.

Abstract: An aspect of the present disclosure relates to scanning reassigned data storage locations. In one example, a reassignment table is accessed to identify a deallocated data storage location and scan the deallocated data storage location for media defects.

Abstract: Provided are methods, systems, and apparatus for error detection of bits of a data packet received at a receiver unit by detecting corrupted data bits.

Abstract: In an integer partitioning process S701, an integer partitioning unit 110 inputs an order p of a finite group G and an integer e, and calculates an integer e1 and an integer e2 that satisfy e1·e?e2(mod p) based on the order p of the finite group G and the integer e which are input. In a verification value calculation process S702, a verification value calculation unit 130 inputs an element s of the finite group G and an element h of the finite group G, and calculates an element a (=e1·h?e2·s) of the finite group G based on the element s and the element h which are input and the integer e1 and the integer e2 which are calculated by the integer partitioning unit 110 in the integer partitioning process S701. In a verification judging process S703, a verification judging unit 150 judges, based on the element a calculated by the verification value calculation unit 130, whether or not the element a is an identity element O of the finite group G. Hence, whether or not h=e·s is established is judged at high speed.

Abstract: An apparatus, system and method for a go/no go tester that uses various data patterns to assure that equipments, systems and networks using data links, receivers and transmitters are working within the range of predetermined requirements of standards, specifications and protocols. The apparatus, system and methods can be used in at least one of SAS/SATA and Fibre Channel systems based on integrated circuit devices used within the apparatus of the invention.

Abstract: A wireless communication method for transmitting information to the designated region with the boundary defined by the sharp cutoff is provided. Receivers outside the designated region are excluded from retrieving the encoded information. The boundary of designated region is adjustable. The wireless communication method can be applied to clearly defining the accepted region and rejection region in satellite communications. The wireless communication method includes steps of providing an information; encoding the information into an encoded data regarding a designated bit-energy-to-noise-ratio; transmitting the encoded data to form a virtual antenna radiation pattern covering a designated region with boundary defined by the sharp cutoff based on the designated bit-energy-to-noise-ratio; receiving the encoded data; and decoding the encoded data into the original information only when receivers within the designated region with bit-energy-to-noise-ratio no less than the designated bit-energy-to-noise-ratio.

Abstract: A system and method for defect analysis are disclosed wherein a defect data set is input into the system. A radius value is selected by a user, which is the maximum number of bits that bit failures can be separated from one another to be considered a bit cluster. When a defect data set is received, the system and method start with a fail bit and search for neighboring fail bits. The specified radius is used to qualify the found fail bits to be part of the bit cluster or not. If a minimum count of fail bits is not met, the system and method will stop searching and move to the next fail bit. If a minimum count of fail bits is met, the search continues for the next fail bit until the maximum fail bit count specified by the user is reached. Aggregation is provided such that once bit clusters have been classified, the number of clusters that have the exact match or partial match to each other is counted. The user may set the partial match as a threshold count to establish a match.

Abstract: An apparatus connected to a first and second buses, the apparatus having a first controller that transforms first form data into second form data, transforms second form data into first form data, and outputs the transformed data, a second controller that transforms first form data into second form data, transforms second form data into first form data, and outputs the transformed data, a first distributing unit connected to the first and second controllers, the first distributing unit distributing first form data to the first and second controllers, respectively, a first selector that selects one of the second form data, and outputs the selected data, a second distributing unit connected to the first and the second controllers, the second distributing unit distributing second form data to the first and second controllers, respectively, and a second selector that selects one of the first form data, and outputs the selected data

Abstract: Systems and methods that identify the Upper Layer Protocol (ULP) message boundaries are provided. In one example, a method that identifies ULP message boundaries is provided. The method may include one or more of the following steps: attaching a framing header of a frame to a data payload to form a packet, the framing header being placed immediately after the byte stream transport protocol header, the framing header comprising a length field comprising a length of a framing protocol data unit (PDU); and inserting a marker in the packet, the marker pointing backwards to the framing header and being inserted at a preset interval.

Abstract: A method and circuit for implementing substantially perfect array access time tracking with Logic Built In Self Test (LBIST) diagnostics of dynamic memory array and random logic, and a design structure on which the subject circuit resides are provided. The dynamic memory array is initialized to a state for the longest read time for each bit and the dynamic memory array is forced into a read only mode. During LBIST diagnostics with the array in the read only mode, the array outputs are combined with the data inputs to provide random switching data on the array outputs to the random logic.

Abstract: Techniques are provided for performing Galois field arithmetic to detect errors in digital data stored on disks. Two 12-bit numbers or two 10-bit numbers are multiplied together in Galois field using tower arithmetic. In the 12-bit embodiment, a base field GF(2) is first extended to GF(23), GF(23) is extended to a first quadratic extension GF(26), and GF(26) is extended to a second quadratic extension GF(212). In the 10-bit embodiment, the base field GF(2) is first extended to GF(25), and GF(25) is extended to a quadratic extension GF(210). Each of the extensions for the 10-bit and 12-bit embodiments is performed using an irreducible polynomial. All of the polynomials used to generate the first and the second quadratic extensions of the Galois field are in the form x2+x+K, where K is an element of the ground field whose absolute trace equals 1.

Abstract: An information processing apparatus includes: a memory in which an apparatus-unique key is stored, the apparatus-unique key being a key that is unique to the information processing apparatus; an input section that inputs user operation information; a communication section that performs data reception processing; a data processor that executes validity determination processing for the apparatus-unique key; and an output section that outputs a result of the validity determination processing executed by the data processor. The data processor receives, via the communication section, key-validity determination data for determining whether the apparatus-unique key is valid or invalid. The data processor also executes the apparatus-unique-key validity determination processing by using the key-validity determination data in response to a user instruction input via the input section, and outputs a result of the validity determination processing to the output section.

Abstract: Systems and methodologies are described that facilitate mitigating intercarrier and intersymbol interference in symbol transmissions over wireless communications where transmitter and receiver may not be time synchronized. Symbol periods can be extended for transmitting symbols such that an original symbol can be transmitted with one or more duplicated symbols keeping phase continuous, blank symbols, and/or the like. In this regard, multiple receiver windows can be required to receive the symbol such that at least one window has a non-interfered symbol even though timing can be misaligned (e.g., in asynchronous communications channels). Alternatively, the receiver windows can be divided to allow similar receipt of symbols over multiple windows such that one window has a non-interfered symbol. Also, timing misalignment that leads to phase ramping in frequency is accounted for to allow proper demodulation of the symbol.

Abstract: A method and system for generating addresses in a memory card built in self-test (MCBIST) for testing memory devices. The method includes receiving a MCBIST command and determining an addressing mode of the MCBIST command. Sequential addresses are generated and modified in response to the addressing mode being a stress test mode. The modifying includes swapping bits in a sequential address with other bits in the sequential address to target selected portions of a memory. The modified sequential addresses are output to the memory to be utilized in a MCBIST stress test of the memory.

Abstract: A network element disposed at an edge of a connectivity fault management (CFM) domain includes a switch fabric, a central processor (CP) card, and a line card in communication with the CP card through the switch fabric. The line card includes an Ethernet interface for transmitting and receiving Ethernet CFM frames over a network and circuitry configured to generate new continuity check messages (CCMs) periodically, to process CCMs received on each connection supported by the line card, and to detect a loss of continuity for any of the connections supported by the line card. The line card maintains a list of supported connections. A generate timer and an age counter are associated with each connection in the list. The line card generates a CCM for a given connection when the generate timer expires and detects a loss of continuity for the given connection when its age counter exceeds a threshold.

Abstract: One embodiment of the invention relates to a circuit board for testing upsets caused by charged particles delivered under testing conditions. The circuit board comprises a device under test including an internal memory, a memory control unit to generate test patterns for comparison with data read from stored areas within the internal memory of the device under test, and a memory that is configured to only store error data. Other embodiments are described and claimed.

Abstract: Systems, integrated circuits, and methods for protecting data stored in third dimensional vertically stacked memory technology are disclosed. An integrated circuit is configured to perform duplication of data disposed in multi-layered memory that can comprise two-terminal cross-point memory arrays fabricated BEOL on top of a FEOL logic layer that includes active circuitry for performing data operations (e.g., read, write, program, and erase) on the multi-layered memory. For example, the integrated circuit can include a first subset of BEOL memory layers configured to store data, a second subset of the BEOL memory layers configured to store a copy of the data from the first subset of memory layers, a FEOL redundancy circuit coupled to the first subset of the memory layers and the second subset of the memory layers, the redundancy circuit being configured to provide both a portion of the data and a copy of the portion of the data.

Abstract: In one embodiment, the invention is a method and apparatus covering a multilayer process space during at-speed testing. One embodiment of a method for selecting a set of paths with which to test a process space includes determining a number N of paths to be included in the set of paths such that at least number M of paths in N for which testing of the process space will fail, computing a metric that substantially ensures that the set of paths satisfies the requirements of N and M, and outputting the metric for use in selecting the set of paths.

Abstract: One process of a processing environment maintains state on behalf of another process of the processing environment, and uses that state to determine if a problem exists with the another process. The one process is a non-volatile process, while the another process is a volatile process.

Abstract: The process by which a logical simulation model is implemented in a physical device may introduce errors in the resulting implementation. A simulation system enables comparison of a realized physical implementation against the simulation models that produce them, thereby detecting differences between an initial, logical design and the resulting physical embodiment. Errors introduced by an initial design, faulty Intellectual Property blocks, faulty programmable logic device silicon, faulty synthesis algorithms and software, and faulty place and route algorithms and software may be detected. As a result, the simulation system reflects both the accuracy of the actual implemented device with the capacity and performance of a purpose built hardware-assisted solution.

Abstract: To provide a logic verification apparatus capable of preventing, when an indeterminate value is generated in logic verification, the indeterminate value from being unintentionally erased. A simulation part performs a simulation based on a description of the logic function described in a hardware description language. A second symbol replacing part replaces an indeterminate value generated in the simulation by the simulation part with a symbol. The simulation part generates a symbol expression and propagates it to an element at a later stage when the symbol replaced by the second symbol replacing part reaches an element being processed. Therefore, unintentional erasing of the indeterminate value generated during the simulation can be prevented.

Abstract: In an example embodiment, a method is provided for scheduling a check to detect anomalies in a computing system. An average time between the anomalies that are detectable by the check is identified and additionally, a runtime of the check is identified. A frequency of the check is then calculated based on the average time between the anomalies and the runtime of the check, and execution of the check may be scheduled based on the calculated frequency.

Abstract: A standard input for a regression test is processed in a printing system in a first (standard) configuration to generate a standard output. The standard output may include a standard PDL output and a standard bitmap. The standard input is processed in the printing system in a second configuration to be tested to generate regression test output. The regression test output may include a test PDL output and test bitmap. The regression test output and the standard output are compared to determine if changes included in the second configuration of the printing system produce an undesirable effect. Each standard input and corresponding standard output is identified by a unique test identifier and is stored.

Abstract: A system and method for assessing and remedying accessibility of websites is provided. The method includes receiving a website address for assessment, an accessibility guideline and level of assessment to be performed from the user. The method further includes crawling the website for extracting information. The information comprises HTML tags used in designing a webpage. Thereafter, the website is scanned for checking conformance to one or more accessibility parameters. Finally, one or more assessment reports are provided to the user.

Abstract: The present invention relates to a method and system for automatic test data generation for lookup tables. In one embodiment, the present invention is a method for generating test data for an automotive lookup table including the steps of dividing the automotive lookup table into categories, generating a list of assertions corresponding in a one-to-one relationship with the categories such that each of the categories has an assertion corresponding to it, generating an execution trace for each assertion using a constraint solver, and generating test data for each execution trace.

Abstract: The present invention relates to page automation testing method and apparatus. According to one aspect of the invention, there is provided a method for automatically testing a page, comprising: determining based on a predetermined policy a setting value of wait time regarding whether the page is opened successfully; and conducting the page testing based on the setting value of wait time as determined.

Abstract: Provided is an environment that storage device configuration management can be efficiently done in a data center having a virtualization device. A SAN manager acquires configuration information from a device constituting a SAN and prepares a correspondence relationship between a host computer and a virtual volume in the SAN, and a corresponding relationship between the host computer and a real volume, depending upon the acquired information. Based on the corresponding relationship, the SAN manager outputs a correspondence relationship of between virtual and real volumes. Meanwhile, by interpreting a failure-notification message received from the devices of the SAN, detected and outputted is an influence upon an access to a real or virtual volume as to the failure.