Abstract: Various embodiments automatically back annotate an electronic design representation by inserting complex model instances in the representation and interconnecting the model instances with one or more interconnect models. Identifications of ports in a first representation may be associated or updated with identifications of corresponding ports in a second representation. Annotating the first representation may also include associating or stitching parasitic information from the second representation with or in the first representation. A model is used to represent a vectored net by splitting a vectored net with a vectored net identification into multiple scalared net segments each having its own scalared net identification. Some aspects automatically generate a display for visualizing results of annotating an electronic design with complex models. Some of these aspects may further include parasitic information and analysis results in the display.

Abstract: In one embodiment, a non-transitory computer-readable medium stores instructions for implementing an application dataflow aware property and bindings system that implements two-way binding via a unidirectional directed acyclic graph and propagates data through the graph based on the connections between the graph nodes. In one embodiment, properties in a binding relationship are arranged in an upstream and downstream manner. Each property has an upstream node and a downstream node to send and receive messages from other properties. Where a first property is arranged upstream of a second property in the binding graph, the first property is more authoritative than the second property. The most upstream property is the truth for the binding. Requests to update the value of the property are propagated upstream via the upstream nodes and notifications of changes in the value of the property are propagated downstream via the downstream nodes.

Abstract: Computer-implemented methods can transform a corpus of meaningful text sequences into a generalized computer-usable repository of neurolinguistic information that can be applied by one or more computer systems. The computer system(s) can use the neurolinguistic information to neurolinguistically analyze meaningful text sequences to derive statistical information and identify dominant cognitive motivation orientations expressed in those text sequences. The identified dominant cognitive motivation orientations can be used to improve the efficacy of both human-generated and machine-generated communications. The computer system(s) thereby transform a meaningful text sequence into actionable information about the dominant cognitive motivation orientation(s) of the author of that text sequence within the context in which the text sequence was composed. Computer systems and computer-program products for implementing the methods are also described.

Abstract: Computer-implemented methods can transform a corpus of meaningful text sequences into a generalized computer-usable repository of neurolinguistic information that can be applied by one or more computer systems. The computer system(s) can use the neurolinguistic information to neurolinguistically analyze meaningful text sequences to derive statistical information and identify dominant cognitive motivation orientations expressed in those text sequences. The identified dominant cognitive motivation orientations can be used to improve the efficacy of both human-generated and machine-generated communications. The computer system(s) thereby transform a meaningful text sequence into actionable information about the dominant cognitive motivation orientation(s) of the author of that text sequence within the context in which the text sequence was composed. Computer systems and computer-program products for implementing the methods are also described.

Abstract: A system, method, and computer program product are provided for compiling a computer program comprising arithmetic operations having different requirements with respect to numeric dynamic range, numeric resolution, or any combination thereof. The method comprises generating a transformed graph representation of the computer program by applying propagation rules that provide for relaxed numeric requirements, where applicable, and generating output code based on the transformed graph representation. Relaxing numeric requirements, such as dynamic range and resolution requirements, may advantageously lower power consumption during execution of the computer program.

Abstract: Mechanisms for selecting a pipeline of a question and answer (QA) system to process an input question are provided. An input question is received and analyzed to identify at least one feature of the input question. Clustering of the input question, with one or more previously generated clusters of questions, is performed based on the at least one feature of the input question. Based on results of the clustering, a matching cluster, of the one or more previously generated clusters, is identified with which the input question is associated. A QA system pipeline associated with the matching cluster is identified and the input question is processed using the identified QA system pipeline to generate one or more candidate answers for the input question. Each cluster in the one or more previously generated clusters has an associated QA system pipeline.

Abstract: Described are apparatus and method for simulating spintronic integrated circuit (SPINIC), the method comprising: generating a spin netlist indicating connections of spin nodes of spin circuits and nodes of general circuits; and modifying a modified nodal analysis (MNA) matrix for general circuits to generate a spin MNA matrix for solving spin circuits and general circuits of the spin netlist.

Abstract: Embodiments of the present disclosure may include receiving, at one or more computing devices, the electronic circuit design, wherein the electronic circuit design includes at least one Unified Power Format file. Embodiments may further include generating, using the one or more computing devices, a schematic of a power supply network, based upon, at least in part, the at least one Unified Power Format file, the schematic including one or more power supply network components.

Abstract: A method of processing a circuit design in a circuit design tool includes: identifying selection of a parameterized core to be instantiated in a description of the circuit design managed by the circuit design tool and configured for implementation in target hardware; processing a configuration file for the parameterized core to select a set of parameter values from a plurality of sets of parameter values dynamically based at least in part on the target hardware; creating an instance of the parameterized core in the circuit design having the selected set of parameter values; and implementing the circuit design for the target hardware.

Abstract: In one embodiment, a method of designing an integrated circuit is disclosed, including receiving a first partition block for a top level of a hierarchical design of an integrated circuit; analyzing each pin of the first partition block for an attribute associated with the pin indicating a timing exception; and if a timing exception other than false path is indicated then generating an internal timing pin in a first timing graph model of the first partition block for each timing exception, and adding a timing arc and a dummy arc coupled to the internal timing pin in the first timing graph model of the first partition block. The internal timing pin adds a timing exception constraint for each timing exception. Timing of the top level may then be analyzed with the first timing graph model to determine if timing constraints, including the added timing exception constraints, are met.

Abstract: A method is provided to automatically correct an original source code. An abstract syntax tree (AST) is created from the original source code where the AST includes AST nodes. AST node filter queries are evaluated on the AST to filter out AST nodes with defect patterns. Automatic fixes are applied to the filtered AST nodes to transform the AST. A modified source code is created by deserializing the transformed AST.

Abstract: A multi-tier scheduling approach includes a first tier comprising virtual cluster allocators that receive scheduling requests from processes and aggregate those requests and provide them to a second tier, namely a single resource distributor for the entire set of computing devices. The resource distributor, based on the requests from virtual cluster allocators, and also from information received from the computing devices themselves, generates a flow graph to identify an optimal scheduling of the assignment of resources to specific ones of the virtual clusters. Each virtual cluster allocator then, based on the assignment of resources assigned to it by the resource distributor, solves its own flow graph to identify an optimal scheduling of processes on the resources assigned.

Abstract: A method performed by an information handling system for on-the-fly technical support is described. In an exemplary method, an error message is read to obtain an error code therefrom. A project directory is searched to obtain a report; where the report indicates a failed module of a plurality of executable modules, and where the report is associated with the error message. A source of an error is identified from the error message. A failed stage of the failed module is identified from the report. A case inquiry for the error message is prepared for searching a document for resolution of the error, where the case inquiry identifies the failed stage. A network is accessed, and the case inquiry is sent over the network.

Abstract: A design apparatus generates an optimal design condition by design space exploration. The apparatus including a source code parsing (301) which parses source code and generates a parse tree, a cluster generation task (302) which generates clusters based on the parse tree, each of the clusters including a group of source codes which can operate independently, a log file task (303) which generates a log file based on a structure of the cluster, and a comparison task (304) which compares a first log file of a previous cluster with a second log file of a current cluster and re-uses previous exploration result based on a comparison result, the first log file being obtained from a previous design space exploration, the second log file being generated from a current operation.

Abstract: In a method for simulating temperature and electrical characteristics within an circuit, a temperature of at least one volume within the circuit as a function of a resistance within the at least one volume is repeatedly calculated and the resistance as a function of the temperature is repeatedly calculated until the temperature is within a predetermined tolerance of a previous temperature result and until the resistance is within a predetermined tolerance of a previous resistance result. Once the temperature is within a predetermined tolerance of the previous temperature result and the resistance is within a predetermined tolerance of the previous resistance, then an output indicative of the temperature is generated.

Abstract: An abstract decision module primitive for placement within a logical representation (i.e., a netlist) of a circuit design is described. The decision module primitive receives as inputs alternative solutions for a given function or segment of a netlist. The alternative solutions include functionally equivalent, but structurally different implementations of the function or segment of the netlist. The decision module primitive alternatively selects between connecting one of the inputs to the netlist to provide a complete functional definition for the netlist based on constraint information. The selected input of the decision module may be updated as additional constraint information is determined throughout the various stages of the design process. In addition, alternative solutions for a given function or segment of the netlist may be added to and/or removed from the inputs of a decision module as additional constraint information is identified.

Abstract: A method for generating a circuit description for a multi-die field-programmable gate array, FPGA, comprising a first FPGA die and at least one further FPGA die is described. The method is performed in an FPGA design tool and comprises automatically evaluating a first and a second partition of a partitioned circuit description, the partitions being associated with respective ones of the FPGA dies. At least one multiplexing element is inserted into the first partition and a corresponding de-multiplexing element is inserted into the second partition based on the automated evaluation.

Abstract: A method for designing a system to be implemented on a target device includes generating a register transfer language (RTL) representation of the system from a description of the system without pipelined delays. The RTL representation of the system includes pipelined delays to facilitate timing of the system as implemented on a target device identified by a designer.

Abstract: Systems and techniques are described for performing circuit synthesis. Some embodiments create a lookup table based on information contained in a cell library. The lookup table is then used during circuit synthesis. Specifically, some embodiments optimize cells in a reverse-levelized cell ordering. For a given cell, a table lookup is performed to obtain a set of optimal cell configurations, and the cell is replaced with a cell configuration selected from the set of optimal cell configurations. Some embodiments concurrently optimize cells for timing, area, and power leakage based on the timing criticality of the cells.

Abstract: A system and method tests for functional equivalence prior to automatically retiming a high-level specification. An Intermediate Representation (IR) includes one or more graphs or trees based on the high-level specification. A functional equivalence (FE) analyzer determines whether one or more components in the graph meet certain value and state conditions and thus is a candidate for retiming. A bounded scheduler then retimes only those components that pass the FE analysis.

Abstract: A verification item extraction apparatus is disclosed that performs a priority determination process. Connection relationships pertinent to input/output are derived for each of logics in a verification subject circuit based on connection information acquired from description data in a storage part. A first priority for verifying the logics is determined based on the connection relationships being derived. Related I/Fs, which are related to inputs to the logics and are interfaces to an outside of the verification subject circuit, are extracted based on the connection information. Second priority for verifying the related I/Fs is determined based on the first priority.

Abstract: A reconfigurable computer architecture is disclosed. The reconfigurable computer architecture has a plurality of logic elements, a plurality of connection switching elements, and a plurality of volatile and/or non-volatile configuration random access memories (RAMs). Each of the configuration RAMs is electrically coupled to at least one of the plurality of logic elements or at least one of the connection switching elements.

Abstract: Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of multiplexers that each has a set of input terminals, a set of output terminals, and a set of select terminals. The set of multiplexers includes a group of multiplexers, where at least one input terminal of each multiplexer in the group is a permanently inverting input terminal. During at least a set of cycles during the operation of the configurable IC, several multiplexers in the group of multiplexers are used to implement a particular function.

Abstract: In one embodiment, a method of designing an integrated circuit is disclosed, including receiving a plurality of top level timing constraints and a description of the integrated circuit design defining a hierarchy of partitions having multiple levels with one or more nested partitions; generating timing models for each partition of the plurality of partitions in response to the description of the integrated circuit design; and concurrently generating timing budgets level by level for all partitions at each level, beginning with the lowest level to each next upper level of the hierarchy of the partitions in response to the description of the integrated circuit design, the timing models, and the plurality of top level timing constraints. Please see the detailed description and claims for other embodiments that are respectively disclosed and claimed.

Abstract: A system and method of designing an integrated circuit capable of deriving timing constraints for individual block-level circuits of an integrated circuit that are derived from the chip-level timing constraints and analysis. The block-level timing constraints are in the form of one or more logical timing constraint points at the input and output ports of block-level circuits. Each logical timing constraint points specifies a clock source used to clock data through the port, a delay parameter specifying data propagation delay backward from an input port and forward from an output port, and any timing exception associated with the data path. Using the logical timing constraint point, the circuit design system performs independent timing analysis and optimization of each block-level circuit. The system then reassembles the block-level circuits into a modified chip-level circuit for which timing closure can be achieved.

Abstract: The invention comprises (i) a compilation method for automatically converting a single-threaded software program into an application-specific supercomputer, and (ii) the supercomputer system structure generated as a result of applying this method. The compilation method comprises: (a) Converting an arbitrary code fragment from the application into customized hardware whose execution is functionally equivalent to the software execution of the code fragment; and (b) Generating interfaces on the hardware and software parts of the application, which (i) Perform a software-to-hardware program state transfer at the entries of the code fragment; (ii) Perform a hardware-to-software program state transfer at the exits of the code fragment; and (iii) Maintain memory coherence between the software and hardware memories. If the resulting hardware design is large, it is divided into partitions such that each partition can fit into a single chip. Then, a single union chip is created which can realize any of the partitions.

Abstract: Technology for finite-state machine (FSM) encoding during design synthesis for a circuit is disclosed. The encoding of the FSM may include determining values of a multi-bit state register that are to represent particular states of the FSM. These values may be determined based on possible states of the FSM, possible transitions between the states, probabilities of particular transitions occurring, amounts of false switching associated with particular transitions, area estimates for logic respectively associated with states of the FSM, and/or the like. The values may also be determined based on power considerations, such as estimated power consumption for the circuit. The design synthesis may include generation of a structural description of the encoded FSM.

Abstract: In one embodiment of the invention, a physical layout wire-load algorithm is used to generate a wire-load model based on physical data including aspect ratio and wire definitions defined in a physical library. The physical layout estimator is utilized to dynamically produce the physical layout wire-load model and to calculate net length and delay for each optimization iteration.

Abstract: An emulation system integrates multiple custom prototyping boards for emulating a circuit design. A first custom prototyping board including at least one FPGA and an interface connected to a first set of wires coupling to the at least one FPGA. A second custom prototyping board includes at least one second FPGA and an interface connected to a second set of wires coupling to the at least second FPGA. An adaptor board connects to the first custom prototyping board and the second custom prototyping board through the first interface and the second interface. The adapter board controls emulation of the circuit design and controls communication through the partitioned circuit using at least one of the first set of wires and at least one the second set of wires.

Abstract: In one embodiment of the invention, a method includes partitioning an integrated circuit design into a hierarchy of a top level and a plurality of partitions, wherein the top level includes a top level netlist and each partition includes a partition netlist; receiving data path timing budgets and clock path timing budgets for each of the plurality of partitions of the integrated circuit design; and generating a timing budget model of each partition in response to the respective data path timing budgets and clock path timing budgets, wherein each timing budget model includes an intra-partition clock timing constraint for each respective partition for independent implementation of the top level.

Abstract: An embodiment of the present invention includes a partitioner, a synthesizer, and an optimizer. The partitioner partitions a design into a hierarchy of partitions having a top-level partition and lower partitions. The lower partitions include a bottom-level partition. The top-level partition has top-level constraints. The synthesizer synthesizes the lower partitions hierarchically from the bottom-level partition to create lower partition netlists based on the top-level constraints. The optimizer optimizes a top-level netlist corresponding to the top-level partition from the lower partition netlists to satisfy the top-level constraints.

Abstract: A method and apparatus to cluster nodes of a hypergraph is described. The method improves the clustering by placing the hypergraph into an N-dimensional space. The method receives a design represented by a hypergraph with a plurality of nodes. The method places the plurality of nodes of the hypergraph into the N-dimensional space, where N is greater than or equal to 2. The method clusters nodes of the hypergraph based on locations of the plurality of nodes in the N-dimensional space.

Abstract: This disclosure relates generally to field-programmable gate arrays (FPGAs). Some implementations relate to methods and systems for partitioning FPGA circuit designs to facilitate certification. In one aspect, a method includes generating a hardware description language (HDL) implementation of a circuit design. The method additionally includes partitioning the design into a first portion and a second portion. In some implementations, the second portion corresponds to a safety-critical portion of the design while the first portion corresponds to a non-safety-critical portion. The method additionally includes generating first configuration settings for the first portion and generating second configuration settings for the second portion. The method additionally includes verifying, or providing to a third-party certification body for verification, the first configuration settings for the first portion and the second configuration settings for the second portion.

Abstract: A hierarchical interface module includes an assessment unit configured to identify a hierarchical implementation incompatibility of an integrated circuit (IC) partitioned block. Additionally, the hierarchical interface module includes an interface unit configured to substitute a directly registered hierarchical interface structure for the hierarchical implementation incompatibility of the IC partitioned block. A method of interfacing hierarchically and a hierarchical implementation system are also included.

Abstract: A method of mapping threshold gate cells into a Boolean network is disclosed. In one embodiment, cuts are enumerated within the Boolean network. Next, a subset of the cuts within the Boolean network that are threshold is identified. To minimize power, cuts in the subset of the cuts are selected.

Abstract: A method of designing a circuit is described. In an embodiment, a physical design implementation for the circuit is created using a plurality of entities. These entities are named “genomes”. Each entity includes a portion of a functional description of the circuit that has been synthesized into a gate-level implementation. An entity is selected to facilitate the physical design implementation meeting a plurality of design constraints. Several steps (e.g., beginning with selection of an entity) of this method are repeated several times to meet the design constraints. As a consequence, the physical design implementation provides more accurate information for use in a final physical design implementation. Moreover, the physical design implementation can be created faster than prior techniques while still allowing a global view of the physical design implementation in meeting design constraints.

Abstract: A method for designing a system on a target device is disclosed. The system is synthesized. The system is partitioned into a plurality of logical sections utilizing information derived from synthesizing the system and prior to performing placement of the system on the target device. Other embodiments are described and claimed.

Abstract: A circuit diagram includes a plurality of components. Each component corresponds to a module number and a component number. The components corresponding to a same module number are classified into a same function module. Each function module corresponds to a component module file. The component module file of each function module is generated according to the classified function modules. The component module file includes the module number of the function module and the component numbers of the components which are included in the function module. The component module files of the circuit diagram can be imported in a printed circuit board (PCB) drawing software.

Abstract: The present invention discloses methods and apparatuses to design an integrated circuit. According to one aspect, the present invention circuit design discloses an iterative process of synthesis and placement where each iteration provides incremental changes on the design of the integrated circuit. The synthesis transform is then made with accurate timing information from the placement, and the process is incrementally iterative toward the final timing enclosure of the design. The incrementally iterative approach of the present invention provides a continuous advancement from synthesis to placement and vice versa, with the incremental improvements on synthesis made with knowledge of current instance placement, and the incremental improvements on placement made with knowledge of current circuit logic.

Abstract: A method for use in electronic design software efficiently and optimally produces minimized or reduced register flip flop area or number of registers/flip flops in a VLSI circuit design without changing circuit timing or functionality. The method dynamically generates constraints; maintains the generated constraints as a regular tree; and incrementally relocates registers/flip flops and/or the number of registers/flip flops in the circuit design.

Abstract: In one embodiment of the invention, a method for electronic circuit design is disclosed. The method includes analyzing a netlist of a subcircuit to determine one or more input pins and one or more output pins; forming an arc graph of the subcircuit including one or more timing arcs between the one or more input pins and the one or more output pins; and reducing the number of transistors to perturb to perform a sensitivity analysis for within die process variations over the one or more timing arcs to reduce the number of simulations to characterize the subcircuit.

Abstract: In an LSI design method of designing a clock tree that supplies a clock signal to a plurality of leaves from a clock supply point, when a high level clock tree is constituted by H-tree and a low level clock tree is formed by CTS, the number of stages of a high level clock tree is optimized without giving any constraint on the placement of a low level clock tree. The leaves are divided into a plurality of groups to form a low level local tree. A clock-supplied region including all leaves to be supplied with a clock is uniformly divided and for each divided region, a skew when a clock signal is supplied from an end of an H-tree to start points of a plurality of local trees included in that region is estimated. The clock-supplied region is more finely equally-divided to increase the number of stages of H-tree.

Abstract: A method for designing a system to be implemented on a field programmable gate array (FPGA) includes identifying an adder from an intermediate representation of the system. Components on the target device are designated to support and implement the adder as a partitioned adder having a plurality of sub-adders each registering an intermediate result.

Abstract: Method, apparatus and system for finding instances of a pattern in a main netlist include reading in the main netlist and the pattern that is used for finding pattern matches in the main netlist. The main netlist and the pattern include a plurality of vertices. Each of the vertices is a device or a net. Labels for the vertices are computed in both the pattern and the main netlist up to a depth appropriate for the pattern. A vertex of the pattern is identified and used in matching with one or more vertices in the main netlist at the depth appropriate for the pattern using the computed labels. The computed labels for each of the vertices of the main netlist are stored for possible reuse in subsequent pattern matches.

Abstract: A system and method are disclosed for waveform based variational static timing analysis. A circuit is divided into its linear circuit parts and non-linear circuit parts and modeled together, by a combination of linear modeling techniques, into linear equations that may be represented by matrices. The linear equations in matrix form may be readily solved by a computer such that an input waveform to an input pin of the circuit can be sequentially “pushed” through the various interconnects and logic networks of the circuit to an output pin. Output voltage waveforms are obtained at each stage of the waveform pushing and may be used to perform static timing analysis.

Abstract: An algorithm and architecture are disclosed for performing multi-argument associative operations. The algorithm and architecture can be used to schedule operations on multiple facilities for computations or can be used in the development of a model in a modeling environment. The algorithm and architecture resulting from the algorithm use the latency of the components that are used to process the associative operations. The algorithm minimizes the number of components necessary to produce an output of multi-argument associative operations and also can minimize the number of inputs each component receives.

Abstract: This disclosure relates generally to field-programmable gate arrays (FPGAs). Some implementations relate to methods and systems for partitioning FPGA circuit designs to facilitate certification. In one aspect, a method includes generating a hardware description language (HDL) implementation of a circuit design. The method additionally includes partitioning the design into a first portion and a second portion. In some implementations, the second portion corresponds to a safety-critical portion of the design while the first portion corresponds to a non-safety-critical portion. The method additionally includes generating first configuration settings for the first portion and generating second configuration settings for the second portion. The method additionally includes verifying, or providing to a third-party certification body for verification, the first configuration settings for the first portion and the second configuration settings for the second portion.

Abstract: A method for implementing a hardware design that includes using a computer for receiving structured data that includes a representation of a basic hardware structure and a complex hardware structure that includes the basic hardware structure, parsing the structured data and generating, based on a result of the parsing, commands of a hardware design environment.

Abstract: A design partitioning method and apparatus includes an RTL reader module configured to receive, process, and parse hardware descriptive language of a circuit design; an expression graph module configured to trace identified signal dependencies to determine dependent elements along selected paths within the circuit design; a hierarchy flattener module configured to remove existing circuit design hierarchies based on the identified signal dependencies and determined dependent elements; a partition specification reader module that defines selected paths within the circuit design into a partition specification; a design partitioner module configured to separate the flattened circuit design hierarchy according to the partition specification; a re-partitioner module configured to create a second hierarchical circuit design structure based on the separated, flattened circuit design hierarchy that is behaviorally identical to the circuit design; and an RTL design write-out module configured to output the second hiera

Abstract: An emulation system integrates multiple custom prototyping boards for emulating a circuit design. A first custom prototyping board including at least one FPGA and an interface connected to a first set of wires coupling to the at least one FPGA. A second custom prototyping board includes at least one second FPGA and an interface connected to a second set of wires coupling to the at least second FPGA. An adaptor board connects to the first custom prototyping board and the second custom prototyping board through the first interface and the second interface. The adapter board controls emulation of the circuit design and controls communication through the partitioned circuit using at least one of the first set of wires and at least one the second set of wires.