Abstract: A system and method for generating test patterns for a pattern sensitive algorithm. The method comprises the steps extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout design that covers a feature sample from each cluster; and saving each pattern layout covered by the at least one area as test patterns.

Abstract: A method for single event transient filtering in an integrated circuit device is described. The device comprises three sequential elements, each having a data input and a data output with each of the three data outputs coupled to one of three inputs of a voting gate. The method comprises generating first and second nominally equivalent logic signals in first and second SET domains, converting the first and second nominally equivalent logic signals into first, second and third nominally equivalent data channels, and transmitting the first, second and third nominally equivalent data channels to the data inputs of the first, second and third sequential elements. Provision is made for applying the method to logic designs implemented in programmable logic integrated circuit devices.

Abstract: A method for designing a system on a target device is disclosed. Domains and sub-domains in the system are identified. A sub-domain is divided into a plurality of chunks. Slacks for the chunks are computed in parallel. Other embodiments are described and claimed.

Abstract: A simulation environment is disclosed wherein both analog and RF signals are simulated in a single flow by a mixed-domain simulator. The simulator includes a simulator kernel with an analog solver and an RF solver to allow both analog- and RF-type of signals to be solved in an interrelated fashion. The simulator may also include a partitioner that divides the circuit into various RF and analog modules to be solved. User input may control the partitioning process, but the simulator may refine the partitions or generate sub-partitions to provide a higher probability of convergence.

Abstract: A semiconductor device design support apparatus for generating a substrate netlist so as to be able to perform substrate noise analysis with high accuracy in a short time. The semiconductor device design support apparatus comprises a unit that divides a semiconductor device layout into a plurality of segments and generates a macro-model of the segments by using a current waveform of an instance included in the divided segments; a unit that replaces a pattern (termed as “substrate interface”) that is designed to be an interface with a substrate with respect to the segments, by a prescribed substrate interface diagram; and a unit that generates a substrate netlist, based on the substrate interface diagram of the plurality of segments.

Abstract: Methods and apparatuses for incremental circuit partitioning and incremental trace assignment. In one embodiment of the present invention, a cost function based on both the partitioning solution and the trace assignment solution is used for the partitioning of a circuit; in reducing the cost function, blocks of circuits are moved among partitions and the trace assignment are updated accordingly to evaluate the cost function. In one embodiment, the traces and nets are grouped according to the partitions they connect for trace assignment. In one embodiment, a flow diagram is constructed for assigning nets to traces; and, maximum flow algorithms are used. In one embodiment, a flow diagram includes feedthrough solutions, in which flow conservation is not preserved at certain nodes. In one embodiment, integer linear programming techniques are used for assigning nets to traces.

Abstract: Apparatuses and processes for distributing signals in an integrated circuit are disclosed. An embodiment to use a custom layer together with a base layer on an integrated circuit for testing the integrated circuit includes having a structured network on the base layer. The custom layer connects the network to logic elements on the integrated circuit. The network may be evenly distributed across the base layer of the integrated circuit. Even distribution of the network may reduce skew of the test signals. Buffers are also placed along the structured network. The buffers may be placed to ensure a deterministic test signals distribution. Unused buffers in the base layer may be tied off to reduce current leakage.

Abstract: Techniques for statistical formal activity analysis with consideration of temporal and/or spatial correlations are described herein. According to one embodiment, a sequential circuit having a feedback loop is unrolled into multiple unrolled circuits, where the sequential circuit is represented by a finite state machine (FSM). A temporal correlation is introduced to each of the unrolled circuits via a correlation network for an activity analysis of the sequential circuit. The temporal correlation represents a dependency relationship between a current logic state of a signal and a previous logic state of the signal. Other methods and apparatuses are also described.

Abstract: An embodiment of the present invention includes a partitioner, a synthesizer, and an optimizer. The partitioner partitions a design into a hierarchy of partitions having a top-level partition and lower partitions. The lower partitions include a bottom-level partition. The top-level partition has top-level constraints. The synthesizer synthesizes the lower partitions hierarchically from the bottom-level partition to create lower partition netlists based on the top-level constraints. The optimizer optimizes a top-level netlist corresponding to the top-level partition from the lower partition netlists to satisfy the top-level constraints.

Abstract: Embodiments that create parent-child relationships for reuse of 1×N building blocks in a closed-loop 1×N system are disclosed. Some methods comprise generating a representation of an IC design, inserting a first 1×N building block into the representation, and creating an association between the first 1×N building block and a second 1×N building block. The association enables the first 1×N building block to inherit alterations of attributes of the second 1×N building block and enables unique alterations of attributes of the first 1×N building block which differ from the second 1×N building block. Further embodiments comprise an apparatus having an equivalency determiner to determine a logical equivalence between a two 1×N building blocks, an attribute creator that creates a set of attributes and enables one of the 1×N building blocks to inherit parent attributes and comprise child attributes.

Abstract: A method for generating and evaluating a table model for circuit simulation in N dimensions employing mathematical expressions for modeling a device. The table model uses an unstructured N-dimensional grid for approximating the expressions.

Abstract: An integrated prototyping system (IPS) is proposed for verifying and validating an electronic system design (ESD) with hierarchical design elements (HDEs). The IPS has: a) A reprogrammable logic device (RPLD) having an emulation timing base and an RPLD-interface for programming and simulating HDEs under validation while transacting exchanging vectors. The RPLD is also switchably coupled to numerous external peripheral electronic devices (PED), b) An EDA simulator for simulating then verifying selected HDEs while transacting exchanging vectors. The EDA simulator also has a simulator interface; and c) An IPS controller bridging the RPLD and the EDA simulator. The IPS controller has an IPS executive for progressively verifying and validating the ESD. The IPS executive further includes a co-emulation software for jointly and simultaneously running the RPLD and the EDA simulator with an event-based synchronization scheme for interchanging exchanging vectors on demand between the RPLD and the EDA simulator.

Abstract: A data processor which includes: a circuit data providing section which provides circuit data including a character string; a replacement section which bijectively maps the character string of the provided circuit data to integer values; and a data developer which executes data processing including hierarchical development with respect to the circuit data of the integer values obtained by the replacement section.

Abstract: A method for optimizing a design for a device is disclosed. Such an optimization is performed with respect to a predetermined metric, e.g. device speed, area, power consumption or yield. In one aspect, the method comprises obtaining a design for a device. The design comprises design components. The method also comprises determining from the design components at least one group of first design components that has a higher sensitivity to the predetermined metric than second design components. The first design components may be on the critical path in the design. The method further comprises tuning the first design components and the technology for manufacturing the first design components thus reducing the variability of the first design components and obtaining an optimized design with respect to the predetermined metric.

Abstract: A circuit board analyzing method and a circuit board analyzer are provided which can greatly reduce analyzing time. The circuit board analyzer includes a computing unit 110, a memory unit 140 connected to the computing unit 110, and an input unit 160 connected to the computing unit 110. The computing unit 110 includes a wiring data acquiring section 310 acquiring data of wirings formed on a circuit board, a basic circuit diagram forming section 320 dividing the wirings into meshes and setting cells and branches connecting the adjacent cells, and an interference analysis setting section 330 setting an element ignoring range of elements set in the cells and the branches.

Abstract: Computer-implemented techniques are disclosed for defining an environment for formal verification of a design-under-test. Initially there is extraction of design inputs by a design analysis module, and presentation of the inputs on a graphical user interface. Behavior options for the design inputs are offered on the graphical user interface for selection by an operator. Environment code that is descriptive of the design inputs and selected behavior options is emitted, typically in a hardware description language, for submission to a formal verification tool. A meta-code file containing the assigned behavior options is generated to aid subsequent sessions.

Abstract: A computer-implemented method of routing a circuit design for a target integrated circuit (IC) can include determining a characterization of routing congestion of the circuit design within the target IC and determining a first order cost component of using routing resources of the target IC according to the characterization. The method can include determining a higher order cost component of using routing resources of the target IC according to the characterization and assigning signals of the circuit design to routing resources according to costs calculated using the first order cost component and the higher order cost component. Signal assignments of the circuit design can be output.

Abstract: A computer-implemented method of performing an equivalence check on a mixed-signal circuit is performed on a server system, and includes responding to a verification request. In the method, the following operations are performed. A static analysis is performed on a first netlist, and a synthesizable section and non-synthesizable section of the first netlist are identified. A functional equivalence is determined between the non-synthesizable section of the first netlist and a corresponding non-synthesizable section of a second netlist, and a logical equivalence is determined between the synthesizable section of the first netlist and a corresponding synthesizable section of a second netlist. An equivalence result is provided based on the determined functional equivalence and the determined logical equivalence.

Abstract: Provided is an integrated circuit layout design supporting device which can reduce the wiring length by avoiding bypass wirings when a plurality of same-type macro blocks are used. The integrated circuit layout design supporting device includes a terminal coordinate calculation control unit and a layout processing control unit. The terminal coordinate calculation control unit considers the plurality of same-type macro blocks included in a plurality of types of macro blocks as each of different types of macro blocks, and calculates the optimum coordinate positions of each macro terminal of each macro block. The layout processing control unit performs various types of wiring layout processing related to each of the macro terminals based on each of the macro terminal positions calculated by the terminal coordinate calculation control unit.

Abstract: A computer-implemented method of identifying timing paths of a circuit block can include representing a circuit block including at least one bypassable component as a block diagram having a plurality of elements linked by nodes. The method can include generating a map file including a text description of each element within the block diagram, wherein the text description of each element specifies a bypass indicator for the element. The method also can include generating a plurality of sub-paths from the map file, determining timing paths from the plurality of sub-paths by selectively combining different ones of the plurality of sub-paths according to commonality of starting points and ending points of the plurality of sub-paths, and outputting the timing paths.

Abstract: Disclosed is a method of implementing controlled equivalent series resistance (ESR) having low equivalent series inductance (ESL) of a multi-layer chip capacitor which includes a plurality of internal electrodes each having first polarity or second polarity which is opposite to the first polarity, and dielectric layers each disposed between the internal electrodes of the first polarity and the second polarity, wherein the internal electrodes having the first polarity and the internal electrodes having the second polarity are alternated at least once to form one or more blocks being stacked.

Abstract: A method includes: before carrying out a timing verification processing of a semiconductor circuit, preliminarily superposing and arranging a dummy pattern template representing an arrangement pattern of dummy metal, onto a layout area defined by layout data while changing an origin position of the dummy pattern template to optimize the origin position of the dummy pattern template; and upon detecting that the result of the timing verification processing has no problem, superposing and arranging the dummy pattern template onto the layout area at the origin position of the dummy pattern template, to generate the layout data after inserting the dummy metal.

Abstract: An electrical resistance determination method. Input to the method includes a description of at least one electrical network within a substrate. The description includes specification of a plurality of first ports on a first side of the substrate, and a plurality of second ports on a second side of the substrate, for each electrical network. All of the first ports are electrically isolated from one another. All of the second ports are electrically connected to a common voltage. A computer readable program code, which is executed by a processor of a computer system computes for a first electrical network of the at least one electrical network an electrical resistance between each first port and a port of the second ports. The computer code may also display a perspective plot of the computed electrical resistances as a bar oriented about normal to each first port.

Abstract: Dynamic power savings and efficient use of resources are achieved in a programmable logic device (PLD) such as a field programmable gate array (FPGA) or complex programmable logic device (CPLD) by receiving a design netlist specifying a circuit including clock signals, clock buffers, clock enable signals and synchronous elements, examining the design netlist to identify synchronous elements coupled to common clock and clock enable signals, cutting the clock signals to the synchronous elements to form a modified design netlist, inserting gated clock buffers into the modified netlist to output gated clock signals to the synchronous elements, responsive to the clock enable signals, and performing placement and routing on the modified netlist. A system for performing the method on an EDA tool is provided. The methods may be provided as executable instructions stored on a computer readable medium which cause a programmable processor to perform the methods.

Abstract: Embodiments of the present invention provide methods and systems for verifying functional equivalence of a power optimized design and its original, unoptimized design (referred to as the golden design) using combinational equivalency checking. Due to some inherent limitations which make combinational equivalency checkers unable to prove equivalency of the two designs in a single step, a series of intermediate design transformations is introduced. These transformations are dependent on the techniques used in generating the power optimized design from the golden design, and may be generically described in a transformation language that provides the necessary constructs to specify an entire set of valid structural modifications.

Abstract: Disclosed are a method, a system, and a computer program product for implementing compact manufacturing model during various stages of electronic circuit designs. In some embodiments, the method loads the full design database information on the master; distributes the tasks to be processed in parallel; loads a full design on a master; spawns a plurality of slave sessions; sends to at least one slave a nutshell representation of the electronic circuit design; identifies a task to perform in parallel and sends the task to be performed in parallel; and receives execution results or processing results from some of the plurality of slaves and updates one or more databases to incorporate the execution or processing results. In some embodiments, the method allows speeding up the applications without major rewrite without a need for design partition, and without memory penalty.

Abstract: In one embodiment, a system model models characteristics of a real-world system. The system model includes a plurality of sub-portions that each correspond to a component of the real-world system. A plurality of test vectors are applied to the system model and coverage achieved by the test vectors on the sub-portions of the system model is measured. In response to a failure of the real world system, a suspected failed component of the real-world system is matched to a particular sub-portion of the system model. A test vector to be applied to the real-world system to test the suspected failed component is selected in response to coverage achieved on the particular sub-portion of the system model.

Abstract: A method of performing a pre-route repeater insertion methodology for at least part of a circuit design may include: partitioning at least part of a circuit design into a plurality of tiles; determining at least one attribute of one or more individual tiles of the plurality of tiles; and determining a repeater solution based at least in part on the determined attributes of the one or more individual tiles. A computer implemented tool for performing a pre-route repeater insertion methodology for at least part of a circuit design may include: a module configured to partition at least part of a circuit design into a plurality of tiles; a module configured to determine at least one attribute of one or more individual tiles of the plurality of tiles; and a module configured to determine a repeater solution based at least in part on the determined attributes of the one or more individual tiles.

Abstract: An embodiment of the present invention includes a partitioner, a synthesizer, and an optimizer. The partitioner partitions a design into a hierarchy of partitions having a top-level partition and lower partitions. The lower partitions include a bottom-level partition. The top-level partition has top-level constraints. The synthesizer synthesizes the lower partitions hierarchically from the bottom-level partition to create lower partition netlists based on the top-level constraints. The optimizer optimizes a top-level netlist corresponding to the top-level partition from the lower partition netlists to satisfy the top-level constraints.

Abstract: An equivalency testing system, for formally comparing an RTLM and HLM, is presented. RTLM and HLM are first converted into DFGs RTLMDFG and HLMDFG. RTLMDFG and HLMDFG are then put into timestep form and are called RTLMts and HLMts. A test bench CSts is selected that couples RTLMts and HLMts. The combination of RTLMts[t], HLMts[t] and CSts[t] can have parts designated as datapath. Parts designated as datapath can be subject to a form of equivalence checking that seeks to prove equivalence by a form of inductive theorem proving that propagates symbolic values indicative of whether a node carries the same data content as another node. The theorem proving starts from initial conditions for HLMts[t] determined by partial execution of the HLM. Propagation to a combinational function output can be determined from equivalence relationships between it and another combinational function. Propagation through a multiplexer can produce a conditional symbolic value.

Abstract: A computer readable storage medium includes executable instructions to receive a specification of a combinational logic circuit. The specification of the combinational logic circuit is converted to a Single-Rail un-encoded circuit and a Dual-Rail encoded circuit, which periodically encodes a null value, a first valid state and a second valid state on two wires. A logic operation of the Single-Rail un-encoded circuit transpires during processing of a null value by the Dual-Rail encoded circuit.

Abstract: The invention relates to multi-planar memory components in a three-dimensional integrated circuit system configuration. A multi-planar memory system consisting of a plurality of memory circuit planes in a three-dimensional system on a chip (3D SoC) comprised of a plurality of memory layers, at least one logic circuit layer and an interface configured to provide access to memory and logic circuit layers.

Abstract: A storage element within a circuit design is identified. The storage element is replaced with both a first storage cell and a second storage cell. The second storage cell operates as a redundant storage cell to the first storage cell. An output of the first storage cell is connected to a first input of a comparator and an output of the second storage cell is connected to a second input of the comparator. The comparator provides an error indicator. Placement of the first storage cell, the second storage cell, the comparator, and one or more intervening cells is determined. The one or more intervening cells are placed between the first storage cell and the second storage cell. An integrated circuit is created using the comparator, the first storage cell, the second storage cell, the one or more intervening cells, and the determined placement.

Abstract: A method for partitioning electronic units and a system for implementing the method are provided. In the method, a plurality of function modules are distributed to the electronic units, for which purpose different inputs are input into an optimizer, which produces a set of comparable distributions.

Abstract: A Hardware Description Language (HDL) processing method is implemented in a computer and processes a HDL file which is written in HDL having a hierarchical structure including three or more hierarchical levels in a Computer-Aided Design (CAD) which supports hardware design. The HDL processing method analyzes the hierarchical structure of the HDL and obtaining an analysis result, and processes the HDL one at a time for each hierarchical level based on the analysis result or, process the HDL one at a time by a parallel distributed processing for each hierarchical level based on the analysis result.

Abstract: Apparatus and method for transaction-based abstraction process can, in an embodiment, include three main phases: first, selecting a set of transaction-processing finite state machines (FSMs) that determine transaction boundaries. Second, extracting the transaction-processing FSMs, composing them, and computing an abstracted FSM corresponding to the composed FSM after abstraction, step 115. Third, abstracting all signals in the design based on the computed abstract FSM.

Abstract: Operating splitting methods for splitting a circuit into two sub circuits and analyzing the two sub circuits with improved computation efficiency and processing speed.

Abstract: The invention relates to a method comprising the following steps: HDL instruction sequences which are to be at the origin of memory elements during the synthesis of the system are automatically localized in the original HDL description files; and so-called SCAN HDL instructions are inserted into at least some of the HDL description files in an automatic sequential manner and without relational or functional analysis of the identified memory elements, ensuring that at least one so-called SCAN channel is obtained during the synthesis of the system, linking the memory elements.

Abstract: A novel logic design method for avoiding wiring congestion. According to the novel logic design method, an original gate having multiple inputs coming from different directions and having multiple outputs coming to different directions can be transformed to a logic block that has an input stage and an output stage. The gates of the input stage receive signals from the multiple inputs of the original gate. The gates of the output stage send signals to the multiple outputs of the original gate. Each gate of the input stage is placed in a vicinity of its inputs. Each gate of the output stage is placed in a vicinity of its outputs. The gates of the input and output stages are functionally equivalent to the original gate.

Abstract: A method for designing a circuit. The method includes (i) providing a netlist of a design and (ii) dividing the netlist into N user logics, N being a positive integer. After said dividing the netlist is performed, the N user logics in N macro test wrappers are instantiated resulting in N instantiated logics. After said instantiating the N user logics is performed, the N instantiated logics are processed. After said processing is performed, a result of said processing is back-annotated to the netlist.

Abstract: Disclosure is made of approaches for mapping an electronic design specification to an implementation. In one approach, quality metrics are associated with functional units of the design, and the functional units are mapped to respective initial implementations. For each functional unit a respective quality indicator is determined based on the mapping. The quality indicator specifies a degree to which the functional unit achieves the associated quality metric. At least one of the functional units is selected for remapping based on the quality indicator of that functional unit or the quality indicator of another functional unit. An alternative implementation to the initial implementation is selected for each selected functional unit to improve the quality indicator. The selected functional unit is remapped to the selected alternative implementation.

Abstract: A hardware verification programming description generation apparatus includes: a behavior synthesis section, for a circuit of hardware that operates in accordance with a multi-phase clock, for dividing the hardware into blocks corresponding to clock systems and performing a behavior synthesis on each of the divided blocks, based on a behavioral description, the behavioral description only describing a process behavior of the hardware but does not describe information regarding a structure of the hardware; and a clock precision model generation section for generating clock precision models using the behavior-synthesized data, the clock precision model capable of verifying the hardware at a cycle precision level.

Abstract: A method and a system for validating clock skews during a hierarchical static timing analysis of a chip or multi-chip package. Each pair of clock inputs of a hierarchical module bounds the allowable clock skew, creating new relative constraints on clock input arrival times propagated to those clock inputs. One embodiment is based on asserted arrival times and a maximum of computed slack values at said clock inputs, while a second embodiment is based on asserted arrival times and a minimum of downstream test slack values. The method further converts module clock assertions into a set of relative timing constraints to allow a hierarchical timing sign-off even in circumstances where absolute timing arrivals are not totally known at the time of module analysis.

Abstract: In random defect yield simulation, a specific defect size interacts with a specific physical design and has a calculated probability of failure associated with it. The failure model is in terms of probability of failure. It provides a solution to the random defect yield simulation problem of chips with a built-in redundancy scheme. The solution first defines the independent failure modes of the chip with a built-in redundancy scheme and efficiently models each mode. Then, it may accumulate the respective probability of failures according to the chip's architecture.

Abstract: Techniques are present for designing of integrated circuits. Both custom design data and synthesized digital design data are received and merged into a design database in an automated process. The design database is then made accessible to layout tools so that the layout tools may operate upon it. These layout tools can include, but are not limited to, custom tools, digitals, or a combinations of these.

Abstract: Embodiments that route 1×N building blocks using higher-level wiring information for a 1×N compiler are disclosed. Some embodiments comprise determining higher-level coordinates for a blockage of a 1×N building block, determining intra-1×N coordinates for a shape of the blockage via the higher-level coordinates, and creating routes of intra-1×N wires of the 1×N building block that avoid the intra-1×N coordinates. Further embodiments comprise an apparatus having a higher-level wiring examiner to examine higher-level wiring of an area near a 1×N building block of a physical design representation. The apparatus may also have a blockage determiner to determine a blockage that affects intra-1×N wiring for the 1×N building block and a coordinate calculator to calculate coordinates of a shape of the blockage, wherein the calculated coordinates may enable a routing tool to avoid the shape when creating intra-1×N wiring for the 1×N building block.

Abstract: In one embodiment of the invention, a method of retiming a circuit is disclosed. The method includes computing an upper bound and a lower bound for a clock period of a clock signal to clock a circuit in response to a netlist of the circuit; selecting a potential clock period for the clock signal to clock registers of the circuit in response to the computed upper bound and the computed lower bound for the clock period; computing an upper bound and a lower bound of a retiming value for each node of the circuit to determine if a retiming of the circuit is achievable with the potential clock period; and computing the retiming value for each node of the circuit to minimize circuit area in response to the computed upper bound and the computed lower bound of the retiming value for each node.

Abstract: A method for on demand functional verification of a software model of an application specific integrated circuit (ASIC), in a low-level programming language, which separately handles the creation of the model and the debugging of the functional verification tests to be applied to the model in order to create a verification platform. In a transmission mode, an autonomous circuit emulator is created by replacing the model in a low level programming language physically describing the circuit to be validated with a high level description generating response data in accordance with the functional specification of the design as a function of stimuli received. A verification mode includes integration of the software model in low level language of the circuit resulting from the design into a verification platform, and creation of a connection of a previously validated autonomous circuit emulator to the interfaces of the software model.

Abstract: A method for performing failure mode and effects analysis (FMEA) on integrated circuits including preparing a FMEA database of an integrated circuit under design and computing FMEA results from the FMEA database. Information is automatically extracted from an integrated circuit description. The extraction of information includes reading integrated circuit information, partitioning the circuit in invariant and elementary sensitive zones (SZ), using the information in the preparation step of a FMEA database. Optionally a FMEA validation stage may be performed with which FMEA computed results are compared with FMEA measured results to obtain FMEA validated results.

Abstract: A system and method of designing an integrated circuit capable of deriving timing constraints for individual block-level circuits of an integrated circuit that are derived from the chip-level timing constraints and analysis. The block-level timing constraints are in the form of one or more logical timing constraint points at the input and output ports of block-level circuits. Each logical timing constraint points specifies a clock source used to clock data through the port, a delay parameter specifying data propagation delay backward from an input port and forward from an output port, and any timing exception associated with the data path. Using the logical timing constraint point, the circuit design system performs independent timing analysis and optimization of each block-level circuit. The system then reassembles the block-level circuits into a modified chip-level circuit for which timing closure can be achieved.