Abstract: The invention provides a method for performing statistical static timing analysis using a novel on-chip variation model, referred to as Sensitivity-based Complex Statistical On-Chip Variation (SCS-OCV). SCS-OCV introduces complex variation concept to resolve the blocking technical issue of combining local random variations, enabling accurate calculation of statistical variations with correlations, such as common-path pessimism removal (CPPR). SCS-OCV proposes practical statistical min/max operations for random variations that can guarantee pessimism at nominal and targeted N-sigma corner, and extends the method to handle complex variations, enabling graph-based full arrival/required time propagation under variable compaction. SCS-OCV provides a statistical corner evaluation method for complex random variables that can transform vector-based parametric timing information to the single-value corner-based timing report, and based on the method derives equations to bridge POCV/SSTA with LOCV.

Abstract: The timing verification method for stochastic networks and circuits is a computerized method that includes a Valued-Sum-of-Products (VSOP) tool as an extension to Zero-suppressed Binary Decision Diagrams (ZBDD) to compute and store paths with their corresponding lengths or statistical parameters. This method starts from source vertices and inductively builds a path database in the topological order of gates. At each node the method builds a set of partial paths that terminated that node using VSOP expressions. Path queries are performed on all paths using VSOP operations, thereby querying the top K-most critical paths in integrated circuit networks.

Abstract: During a pop phase of hierarchical repartitioning of an IC design, all cells within a current hierarchy may be identified, the list of cells may be ungrouped to dissolve the current hierarchy, one or more specified cells may be removed from the list of cells, where the specified one or more cells are to be moved to a different hierarchy, and the new list of cells without the specified one or more cells may be re-grouped, to re-form the previously dissolved hierarchy. During a push phase of the hierarchical repartitioning, all cells within the next lower-level hierarchy may be identified, the identified list of cells may be ungrouped to dissolve that hierarchy, the specified one or more cells may be added to the identified list of cells, and the new list of cells that includes the specified one or more cells may be grouped to reform the previously dissolved hierarchy.

Abstract: Systems and techniques for performing parasitic extraction on a via array are described. If the via array is a single row or column via array, the system identifies a first via and a last via in the via array, and merges a set of vias between the first via and the last via into a center via. If the via array is a M×N (M?2, N?2) via array, the system merges the vias as follows: the first row and the last row of vias in the via array into a first row via and a last row via, respectively; the first column and the last column of vias in the via array into a first column via and a last column via, respectively; and a set of vias between the first and last rows and the first and last columns into a center via.

Abstract: A method co-optimizes a design and a library in such a way to choose the best set of cells to implement the design. The method takes into account the idea of limiting the number of new cells while reducing target costs and respecting design constraints. The method chooses a minimum nearly optimum set of cells to optimize a design. This involves the simultaneous optimization of a cell-based design and a cell library used to implement it. The invention can produce only an optimized library for a specific application, when the circuit is disregarded. The method takes into account a set of new cells described as finalized cells or as virtual cells, possibly having different transistor topologies, different sizes, different logic functions, and/or different cell template than the original library.

Abstract: The present disclosure describes a memory block manager. In some aspects a request is transmitted to a model of an IP block at a randomized time and a response is received from the model of the IP block useful to characterize behavior of the IP block when fabricated. In other aspects a response to a request is transmitted to a model of an IP block at a randomized time and a communication is received from the model of the IP block useful to characterize behavior of the fabricated IP block when fabricated.

Abstract: A method of designing an integrated circuit (IC) includes simulating aging evolution of the IC by providing a standard cells library, and a device activity file of device electrical activity in the standard cells as a function of electrical activity at the pins of the standard cells, taking into account Hot Carrier Injection, Negative Bias Temperature Instability, and gate oxide breakdown. A standard cell evolution file is provided that stores electrical characteristic aging data of standard cells. An instance activity file is provided of simulated electrical activity at the pins of individual instances of the cells in the IC. The instance activity file and the device activity file are used to analyze device activity and consequent aging evolution of the devices, and then generate data for consequent aging evolution of the IC. The IC design can then be modified to account for the aging evolution.

Abstract: Techniques that can improve the efficiency of routing where connections are subject to elongation constraints. The design can be optimized by estimating elongation needed to meet constraints after an initial routing solution has been generated, but before elongation is actually applied to detailed paths. Paths can be re-routed at this earlier stage if it is determined that too much elongation, or too much elongation in crowded areas, will need to be added after the detail routing stage.

Abstract: A method of designing an integrated circuit includes receiving a placement database of logic devices of an electronic device design that includes first and second logic devices. The method further includes determining a first timing window associated with a first state transition of the first logic device, and a second timing window associated with a second state transition of the second logic device. In the event that the first and second timing windows overlap, the placement database is modified, thereby reducing interaction of the first and second logic devices.

Abstract: A timing error sampling generator, a method of performing timing tests and a library of cells are provided. In one embodiment, the timing error sampling generator includes: (1) a hold delay element having an input and an output and configured to provide a hold violation delayed signal at said output by providing a first predetermined delay to a clock signal received at said input, said first predetermined delay corresponding to a hold violation time for a path to be monitored and (2) a hold logic element having a first input coupled to said input of said hold delay element, a second input coupled to said output of said hold delay element and an output at which said hold logic element is configured to respond to said first and second inputs to provide a clock hold signal when logic levels at said first and second inputs are at a same level.

Abstract: A slack-based timing budget apportionment methodology relies not only upon timing analysis-based determinations of slack in the units in an integrated circuit design, but also potential performance optimization opportunities in the logic used to implement such circuits. Logic in various units of an integrated circuit design that is amenable to being replaced with comparatively faster logic may be identified during timing budget apportionment, such that the magnitude of the slack reported for those units can be adjusted to account for such potential performance improvements. Then, when timing budgets are reapportioned using the slack calculated for each unit, additional slack is available to be reapportioned to those units needing larger timing budgets.

Abstract: Implementations of the present disclosure involve an apparatus and/or method for identifying and classify nodes of an electrical circuit design to account for hold time violations occurring within the circuit. The nodes may be ordered based on a criticality of the nodes that may aid in identifying those nodes of the circuit where hold time violations may be corrected. In one embodiment, the criticality may relate to the number of potentially violating paths that utilize the identified nodes such that corrective measures applied at those nodes may correct several hold time violating paths. In addition, criticality may be scaled utilizing an available buffer library and other timing information.

Abstract: A method for designing a system to be implemented on a target device includes generating a register transfer language (RTL) representation of the system from a description of the system without pipelined delays. The RTL representation of the system includes pipelined delays to facilitate timing of the system as implemented on a target device identified by a designer.

Abstract: Techniques for estimating a risk of incorrect timing analysis results for signal paths having cells with inputs tied together are described. Signal paths having cells with tied input pins are identified in a circuit. A timing analysis on the signal paths is run to identify the worst case delay through the signal paths. The risk to the signal paths of incorrect timing analysis results due to the cells with tied input pins is estimated by a tied input pin analysis tool. Metrics that quantify timing failure risk associated with signal paths is provided in the form of a set of equations. These equations are embedded into a process allowing automated multi-modal, multi power voltage temperature analysis for the identification of high risk paths.

Abstract: A method and apparatus to provide a hierarchical timing model with crosstalk consideration is provided. In one embodiment, the method comprises performing block level analysis of a circuit, in one or a plurality of iterations, and storing per iteration data. The method further comprises, in one embodiment, utilizing the per iteration data in performing top level analysis of the circuit.

Abstract: Techniques and systems for optimizing a circuit design are described. In some embodiments, a sequential cell is selected for optimization. Next, the system iterates through a set of candidate sequential cells that are functionally equivalent to the sequential cell that is being optimized. The system evaluates the global timing impact of each candidate sequential cell in a highly efficient manner. For each candidate sequential cell that is evaluated, a non-timing metric and a timing metric for a candidate sequential cell are compared with the corresponding non-timing metric and timing metric for the current best sequential cell. If a candidate sequential cell improves the timing metric, or maintains the timing metric and has better non-timing metric(s), then the candidate sequential cell is stored as the current best sequential cell. Once the process completes, the current best sequential cell is the optimized cell size for the sequential cell.

Abstract: A semiconductor integrated circuit design apparatus for analyzing a delay in a semiconductor integrated circuit. The semiconductor integrated circuit includes a delay analysis unit, a noise generation unit, a voltage fluctuation level analysis unit and a timing verification unit. The noise generation unit generates noise information based on a predetermined noise definition and the voltage fluctuation level analysis unit analyzes a voltage fluctuation level of the semiconductor integrated circuit when the noise is applied based on the generated noise information. Further, the timing verification unit makes the delay analysis unit analyze the static delay based on the analyzed voltage fluctuation level, to verify timing for operation of the semiconductor integrated circuit based on a result of the static delay analysis.

Abstract: Methods and systems for performing automated conversion of synchronous circuit design to asynchronous circuit design representations are described. A synchronous netlist may be generated from a synchronous circuit design. The synchronous netlist may include combinational logic gates and state-holding elements. The synchronous netlist may be converted to an asynchronous circuit design. The converting may include grouping the combinational logic gates by operations into functions.

Abstract: In an embodiment, a system for optimizing a logic circuit is disclosed. The system is configured to identify an input of a logic circuit cell that violates a timing condition. The input of the logic circuit is coupled to a plurality of logic paths having at least one level of logic. The system is also configured to identify a last node along one of the plurality logic path that violates the timing condition, and insert a buffer at least one node before the last node along the one of the plurality of logic paths that violates the timing condition. The buffer also has a delay optimized to fix the timing condition.

Abstract: A circuit designing method designs a circuit by client computers designing blocks forming the circuit in parallel, and a server exchanging information in real-time with each client computer. The method may notify information related to blocks corresponding to a request from each client computer to the server, analyze each block by an analyzing tool based on the acquired information, and when an analysis result includes an error, compute by a modification ease computing tool, a modification ease of an arbitrary block that includes the error, to notify each client computer of an analysis result taking into consideration the modification ease.

Abstract: Methods and apparatuses for approximate functional matching are described including identifying functionally similar subsets of an integrated circuit design or software program, distinguishing control inputs of the subsets from data inputs, and assigning combinations of logic values to the input control signals to capture co-factors for functional matching.

Abstract: Estimating the latency time of the clock tree of an ASIC including: providing a netlist and a placement related to the clock tree of the ASIC; extracting a number of the load timing devices connected by the clock tree according to the netlist related to the clock tree; extracting a physical distribution area of the load timing devices connected by the clock tree according to the placement related to the clock tree; estimating a latency time of the clock tree according to the relationship between the number of the load timing devices, the physical distribution area of the load timing devices and latency time of the clock tree in design data related to the ASIC design.

Abstract: A method for balancing both edges of a signal of an integrated circuit (IC) design includes defining a virtual cell to have the same geometry as that of a port of the IC design. First and second input pins of the virtual cell are defined for detecting rising and falling edges. The first and second input pin geometries are defined to be the same as that of the corresponding pins of the port. The virtual cell is overlapped with the port so the first and second input pins are connected to the corresponding port network. The first and second input pins are configured as sinks for clock and buffer tree synthesis. An EDA tool identifies the first and second input pins as additional parallel sinks on the port network and balances the rising and falling edges of the signal at the port.

Abstract: A method and system for metastability verification of an integrated circuit design are provided. An IC design is received and the source-to-destination paths of the IC design are determined. For each of the determined source-to-destination paths, it is determined whether the corresponding source is synchronized. For each source its respective synchronized or unsynchronized result is stored and a report is generated for each source describing whether it is synchronized or unsynchronized.

Abstract: A method receives an initial circuit design. The circuit design includes at least one path having at least one beginning point comprising a source, at least one ending point comprising a sink, and one or more circuit elements between the source and the sink. The method evaluates timing performance parameter sensitivities to manufacturing variations of each of the elements to identify how much each element will increase or decrease the timing performance parameter of the path for each change in each manufacturing variable associated with manufacturing the elements. Further, the method alters the elements within the path until elements that produce positive changes to the timing performance parameter for a given manufacturing variable change approximately equals (in magnitude) elements that produce negative changes to the timing performance parameter for the given manufacturing variable change, to produce an altered circuit design.

Abstract: A method of test path selection and test program generation for performance testing integrated circuits.

Abstract: A method for recursive hierarchical static timing analysis. The method includes accessing a lower-level netlist representing a lower-level block of a circuit design to be realized in physical form, and accessing constraints for the lower-level block. Static timing analysis is performed on the lower-level block. The method includes accessing an upper-level netlist representing an upper-level block of the circuit design to be realized in physical form, and accessing constraints for the upper-level block. Static timing analysis is performed on the upper-level block while incorporating results from the static timing analysis on the lower-level block.

Abstract: A technique for a delay measurement system to measure the skews in a clock distribution network is presented. It uses the principle of sub-sampling to measure and amplify small clock skews and determine an estimate of clock skew by further manipulation if these sampled measurements. The technique can be applied to measure clock skew on a computer chip, between bit-line of a communication bus, or between elements connected by an electronic or optical interconnect.

Abstract: Various embodiments provide an integrated circuit (IC) design method and design kit for reducing context variations through design rule restrictions. The design method can be applied to components (e.g., analog blocks) with a context variation in an IC design. By drawing a cover layer over such components, context-variation-reduction design rule restrictions can be applied to reduce the context variations.

Abstract: Systems and methods for identifying and managing the relationships between clock domains in an integrated circuit design are disclosed. A computer-implemented method analyzes the behavioral structure of the clock-to-clock logical relationships in a proposed integrated circuit design. In one embodiment, the method comprises receiving as inputs a description of the design (in a synthesizable format or a synthesized gate-level netlist and definitions of the clock waveforms and timing constraints used in the design, and automatically identifying the relationships between the clocks specified in the description and categorizing the relationships into a plurality of behavioral categories. A list of timing exceptions may optionally also be provided as an input. The identified relationships between clocks and the behavioral categories may be used to verify any existing timing exceptions between clock pairs, and/or to create any missing exceptions between the clock pairs.

Abstract: A device comprises a analysis section for detecting hold errors according to data including the values of the input and output nodes of the FF circuit, and identifying the node in which a hold error has occurred, a determining section for determining insertion of the trailing edge FF or the buffer into hold error sections on the basis of the results of the analysis by the analysis section, a FF insertion section for inserting the FF into a hold error section subjected to position determination so as to insert the trailing edge FF, and connecting a clock line to the FF based on the results of the determining section, and a buffer insertion section for inserting the buffer into the hold error section subjected to the position determination so as to insert the FF based on the results of data of the determining section.

Abstract: A timing analysis mechanism allows defining a clock alias that correlates a clock that is not present in an integrated circuit design to a real clock in the integrated circuit design. In a first implementation, when an existing user assertion references a clock alias, the timing analysis mechanism generates a new user assertion that references the real clock specified in the clock alias. The new user assertion is then used in the timing analysis and the existing user assertion is not. In a second implementation, when an existing user assertion references a clock alias, the timing analysis mechanism generates a duplicate clock in the timing database, preserving all its attributes, and then passes the assertion using the alias name as well as any assertions using the corresponding real clock name to the timing engine to be used in the timing analysis.

Abstract: Power balancing techniques are provided for improving power efficiency of pipelined processors. A design-level implementation can be incorporated during synthesis of pipeline clocks in which a register transfer level (RTL) code, operating frequency, and available voltage domains are used to perform cycle time stealing with, and optimize for, power efficiency. A test-level implementation can be incorporated during testing of a chip in which delay and power measurements are used to perform calculations based on cycle time stealing and optimization of power efficiency. The calculations are then used to perform voltage scaling and/or adjust tunable delay buffers. Process variations may also be corrected during test time. A run-time approach can be incorporated for dynamic power balancing in which the operating system keeps track of one or more performance indicators such as a count of floating point instructions and uses a look-up table to provide the appropriate delays.

Abstract: A system and a method are disclosed for performing clock re-convergence pessimism removal (CRPR) during hierarchical static timing analysis (HSTA). A clock network is divided into a plurality of blocks. A top level includes clock components not included in the plurality of blocks. Block level analysis is performed to determine timing information for each of the plurality of blocks. If available, CRPR data from top level analysis is accounted for in block level analysis. Subsequently, similar analysis is performed on components that are included in top level analysis. If available, CRPR data from bottom level analysis is accounted for in top level analysis. CRPR data can be requested during levels of analysis from the other level. These steps are repeated until analysis is complete.

Abstract: Methods, software, and apparatus for providing a netlist for simulation that includes one or more parameters that are determined by one or more pattern dependent effects. One particular embodiment of the present invention receives a layout of a circuit including one or more MOSFET transistors. For one or more of the MOSFET transistors, spacing between transistors is measured using the received layout and a pattern dependent parameter is determined. This parameter modifies the length of the gate that is used in simulation. In other embodiments, other pattern dependent effects can be used to determine the values of one or more parameters. These parameters may be used to modify gate length, emitter size, resistor width, or other device characteristics.

Abstract: The timing cycles in a circuit design are identified and cut such that timing constraint paths in the circuit design are preserved. Timing cycles in the circuit design may be identified by traversing an adjacency list data structure, in which elements of the circuit design are represented as vertices interconnected by edges. Timing constraint paths may be distinguished from false timing paths using timing analysis, such as a greatest common path heuristic. Timing constraint paths may be marked as “constrained” to prevent these paths from being cut. With the cycles and timing constraint paths identified, cuts may be selected that cut the identified timing cycles while preserving the timing constraint paths. The cycle cuts allow the circuit design to be correctly processed within a conventional CAD tool design flow.

Abstract: One embodiment of a method for verifying functional equivalency between a design of an integrated circuit and a corresponding clock-gated design utilizing output-based clock gating includes selecting a first one of a first plurality of internal state elements in the design and a corresponding first one of a second plurality of internal state elements in the clock-gated design, wherein an input to the first one of the first plurality of internal state elements serves as a first comparison point and an input to the corresponding first one of the second plurality of internal state elements serves as a second comparison point, and the design is to be compared against the clock-gated design at the first comparison point and the second comparison point and generating a test bench that identifies the first comparison point and the second comparison point as a set of comparison points.

Abstract: A computer-readable recording medium stores a design support program causing a computer to perform: detecting a data path and a clock path corresponding to the data path making up a partial circuit in a circuit-under-design; selecting an object cell from cells on the data path and the clock path detected in the detecting; replacing the object cell selected in the selecting with a cell having a function substantially identical to and characteristics different from the object cell; acquiring a plurality of types of characteristic information related to the partial circuit based on the data path and the clock path after the object cell is replaced in the replacing; determining whether the types of the characteristic information acquired in the acquiring is in violation of restrictions; and outputting a determination result determined in the determining.

Abstract: Methods, systems, and machine-readable storage medium for logic synthesis that adjust a timing model of a circuit are provided. A first memory element from multiple memory elements of the circuit may be determined, where the first memory element is connected with a first portion of the circuit and is controlled by at least one first control signal. A combinational element within the first portion of the circuit may be determined. The combinational element may include at least one input or output coupled with a second memory element. The second memory element may be controlled by at least one second control signal. The second control signal may be incompatible with the first control signal. A first timing element may be inserted into the circuit at a location connecting the first timing element with the combinational element. A synthesis optimization may be performed utilizing the at least one first timing element.

Abstract: Techniques for generating an emulated logic block are provided. The techniques include identifying a logic block in one integrated circuit (IC) design that needs to be emulated in another IC design. The logic block may be a physical logic block on the IC design and a non-existent logic block on the other IC design. Logic elements are used to form an emulated logic block that shares substantially the same functionality as the actual logic block. The logic elements are connected to perform logic functions associated with the actual logic block and are grouped together to form an emulated logic block based on the actual logic block.

Abstract: The input slew at a selected gate of an integrated circuit design is computed by assigning a default slew rate to the output gate of a previous logic stage which is greater than a median slew rate for the design. This default slew rate is propagated through the logic stage to generate an input slew rate at the selected gate. The default slew rate corresponds to a predetermined percentile applied to a limited sample of preliminary slew rates for randomly selected gates in the design. The default slew rate is adjusted as a function of known characteristics of the wirelength from the output gate to a first gate in the second logic stage. The delay of the selected gate is calculated based on the input slew rate. The input slew rate can be stored during one optimization iteration and used as a default slew rate during a later optimization iteration.

Abstract: A computer readable non-transitory medium storing a design aiding program causes a computer to execute a process of determining worst-case corner candidates for each of a plurality of condition sets. The design aiding program causes the computer to execute a process of mapping the worst-case corner candidates that are within an allowable range. The design aiding program causes a computer to execute a process of determining the worst-case corner candidates that minimize the number of the worst-case corner candidates mapped to the condition sets by handling the worst-case corner candidates thus mapped as a single worst-case corner candidate to be worst-case corners.

Abstract: In one embodiment, the invention is a method and apparatus for performing statistical timing analysis with non-separable statistical and deterministic variations. One embodiment of a method for performing timing analysis of an integrated circuit chip includes computing delays and slews of chip gates and wires, wherein the delays and slews depend on at least a first process parameter that is deterministic and corner-based and a second process parameter that is statistical and non-separable with the first process parameter, and performing a single timing run using the timing quantity, wherein the single timing run produces arrival times, required arrival times, and timing slacks at outputs, latches, and circuit nodes of the integrated circuit chip. The computed arrival times, required arrival times, and timing slacks can be projected to a corner value of deterministic variations in order to obtain a statistical model of the delays and stews at the corresponding corner.

Abstract: Disclosed is a technique for providing minimal sequential overhead in a flip-flop circuit. Equalization of setup times is achieved in one embodiment. In addition, delays in clock to Q can be equalized for both rising data transitions and falling data transitions. Large setup times are not required since optimization techniques equalize setup times for both rising and falling data transitions.

Abstract: A verification system for verifying an integrated circuit design is provided. The verification system includes a functional block finding module configured to identify potential sensitive circuits in the integrated circuit design; and a search module. The search module is configured to find sensitive circuits from the potential sensitive circuits; and verify the sensitive circuits.

Abstract: Circuit behaviors are scaled to different operating conditions by using a generalized nonlinear model. Nonlinear transforms are applied to the operating conditions and/or to the circuit behaviors contained in a library set. The transformed quantities have a more linear relationship between them. Parameters for the linear relationship are estimated based on the data and operating conditions in the library set. These parameters and nonlinear transforms can then be used to scale circuit behaviors to operating points not contained in the library set.

Abstract: A statistical single library that includes on-chip variation (OCV) is created for timing and power analysis of a digital chip design. Initially, library values for all cells of a digital chip design, including ranges for environmental and process parameters, are subject to a statistical model to create statistical timing for the ranges of the parameters. A statistical timing tool is applied across the ranges of the parameters to determine statistical corners for delay and input power to a subset of cells. The statistically determined delay and input power to the subset of cells is entered into the statistical single library. Each delay of each statistical corner for the subset of cells is compared with a chip sign-off statistical delay requirement of a test macro.

Abstract: In an embodiment, a buffer bay is represented with a moveable object that has a location within a unit in a netlist. The location of the moveable object that represents the buffer bay is changed to a new location in the netlist if changing the location improves placement within the unit. In an embodiment, a net weight of a net that connects the moveable object to an artificial pin is considered in determining whether to change the location to the new location. In an embodiment a bounding area that encompasses the location is considered in determining whether to change the location to the new location.

Abstract: A circuit design supporting apparatus includes: an observation portion specifying section configured to specify a first portion with a high improvement effect of analysis easiness in failure analysis of an integrated circuit as an observation portion; and an element substitution performing section configured to substitute an element arranged in the observation portion by an analysis target element to which a failure analysis apparatus can appropriately conduct the failure analysis based on a data of the observation portion.

Abstract: A method of manufacturing an electronic circuit employing a flexible ramptime limit and an electronic circuit are disclosed. In one embodiment, the method includes: (1) physically synthesizing a logical representation of an electronic circuit employing flexible ramptime limits, (2) performing a timing test on the physically synthesized electronic circuit employing the flexible ramptime limits and a processor and (3) determining if there is a violation of the flexible ramptime limits.