Abstract: A method and systems are provided for screening and rapid evaluation of routed nets in a post-layout circuit environment, such as in the design of printed circuit boards. A portion of nets are selected for determination of associated signal quality factors. Signal channels containing one or more selected nets are then built. A reference input stimulus is propagated along each of the signal channels in a frequency based simulation for generating characteristic responses of the selected nets' signal channels. A signal channel quality factor is obtained for each signal channel based upon its characteristic response. The signal channels and their nets are then comparatively analyzed according to corresponding signal channel quality factors to selectively identify any aberrant nets warranting supplemental evaluation for faults.

Abstract: Embodiments of a method for detecting potential areas of inductive coupling in a high density integrated circuit design are described. The inductance mitigation process first converts the inductive analysis into a density problem. The density of wires within a region that may switch within a portion of the system clock are compared to the density of wires will not switch within that same time. Regions of the chip that have a high ratio of density of switching wires versus non-switching wires are determined to have the potential of an inductive coupling problem. Additional grounded metal is added into the problematic regions of the chip to improve the switching versus non-switching wire density.

Abstract: An interconnect structure for an integrated circuit (IC) device includes an elongated, electrically conductive line comprising one or more segments formed at a first width, w1, and one or more segments formed at one or more additional widths, w2 . . . wN, with the first width being narrower than each of the one or more additional widths; wherein the relationship of the total length, L1, of the one or more conductive segments formed at the first width to the total lengths, L2 . . . LN, of the one or more conductive segments formed at the one or more additional widths is selected such that, for a given magnitude of current carried by the conductive line, a critical length with respect to an electromigration short-length effect benefit is maintained such that a total length of the conductive line, L=L1+L2+ . . . +LN, meets a minimum desired design length regardless of the critical length.

Abstract: An iterative method for generating a series of output signal values from a series of input signal values is described. Iterations of the method comprise the steps of obtaining a current input signal value for the current iteration, comparing the current input signal value with an output signal value determined in a previous iteration, updating a counter value determined in the previous iteration based on the result of the comparison between the current input signal value and the previous output signal value such that the updated counter value replaces the counter value determined in the previous iteration, determining a slew value based on the counter value; and adding the slew value to the previously determined output signal value to generate a new current output signal value. Thus different slew values may be added to the previous output signal to obtain a new output signal. The counter value is updated so that its value reflects recent trends in the input signals. E.g.

Abstract: A pin placement determining method includes calculating a waveform deterioration amount of wires from a noise amount of the wires and wiring loss of the wires, the wires being coupled to a connector on a printed board, comparing the calculated waveform deterioration amount of the wires to an evaluation criteria, evaluating the wires in which the waveform deterioration amount exceeds the evaluation criteria, and replacing corresponding pins of the connectors to which the wires that have been evaluated as exceeding the evaluation criteria are coupled with replacement pins of connectors that have a low noise amount.

Abstract: A design structure for reducing coupling between wires of an electronic circuit is proposed, wherein sets of nets are classified according to their coupling characteristics, and spacing between wires assigned to the sets of nets is chosen according to the coupling characteristics.

Abstract: The method comprises a number of simultaneously switching signals calculation step in which the number of simultaneously switching signals is calculated for each set of user setting information for the input and output signal on the basis of pin arrangement information and the user setting information of the pins in a neighboring area of a pin to be executed in the estimation process; and a simultaneous switching noise calculation step in which a difference is calculated between noise corresponding to an initial point and that to a terminal point in a range of the number of simultaneously switching signals calculated for each set of user setting information on the basis of a relationship between the number of simultaneously switching signals and the noise caused by the number of simultaneously switching signals for each set of user setting information.

Abstract: An orthogonal array is formed by performing electromagnetic field analysis only once and determining a range by using the mount position and type of a capacitor and the number of capacitors as parameters to perform circuit analysis a small number of times. An estimation equation is formed by using as an index a result of the absolute value of the calculated power source impedance, and a capacitor is disposed to reduce noises by using the estimation equation.

Abstract: A method of predicting a substrate current in a high voltage device that may accurately predict substrate current components in each of a first region, a second region, and a third region. This may be accomplished by modeling a substrate current component in a third region, in which an inconsistency may occur when a substrate current in a high voltage device is calculated, for example using BSIM3-based modeling. According to embodiments, a substrate current for a third region may be modeled by an expression with a ternary operator, and the modeled substrate current may be added to a substrate current obtained through BSIM3-based modeling.

Abstract: A method for locating electrical shorts in layout designs by either systematically removing subcells in the layout hierarchy or, if the shorts are not found in any of the subcells, iteratively excluding portions of the top level layout from the electrical connectivity analysis and thereby locate the shorting polygons. Shorts existing both in subcells and the top level will be found by applying the method repeatedly until all shorts are located and eliminated.

Abstract: In a timing analysis apparatus for use in a semiconductor integrated circuit, which analyzes operation timing of a semiconductor integrated circuit having a logic gate circuit including a plurality of logic gates, a controller detects at least one of a power supply voltage and a ground voltage of a power supply, decomposes the noise waveform into frequency components, classifies the frequency components into low-frequency components lower than a predetermined threshold frequency and high-frequency components higher than the threshold frequency, calculates a static delay time of each of the logic gates due to the low-frequency components, calculates a dynamic delay time of each of the logic gates due to the high-frequency components, and determines a delay time of each of the logic gates by synthesizing the calculated respective delay times.

Abstract: There is provided a system and method for statistical timing analysis and optimization of an electrical circuit having two or more digital elements. The system includes at least one parameter input and a statistical static timing analyzer and electrical circuit optimizer. The at least one parameter input is for receiving parameters of the electrical circuit. At least one of the parameters has at least one of a non-Gaussian probability distribution and a non-linear delay effect. The statistical static timing analyzer and electrical circuit optimizer is for calculating at least one of a signal arrival time and a signal required time for the electrical circuit using the at least one parameter and for modifying a component size of the electrical circuit to alter gate timing characteristics of the electrical circuit based upon the at least one of the signal arrival time and the signal required time.

Abstract: An IC device and layout having one or more layers having route segments and at least some shield segments that are diagonal in orientation. Shield termination segments enclosing a route segment may be diagonal in orientation. Some embodiments describe a method for providing diagonal shielding for a routed net of an IC layout. A route “bloating” method is used where shield position lines (used to position the shielding) are generated by expanding out the dimensions of routes using a bloating shape. The bloating shape that may be dependent on the preferred wiring direction of the layer on which the shielding is provided. After bloating a route, a resulting bloating geometry is identified comprising the area overlapped during the expanding out of the route. The perimeter of the bloating geometry is identified comprising the shield position lines.

Abstract: A routing method for reducing coupling between wires of an electronic circuit is proposed, wherein sets of nets are classified according to their coupling characteristics, and spacing between wires assigned to the sets of nets is chosen according to the coupling characteristics.

Abstract: A method for optimizing pin selection for an integrated circuit is provided. Pin locations are mapped to a vector. The mutual inductive relationships between pins of the integrated circuit are captured into a matrix. The matrix contains the data of how a signal state of each pin is affected by the toggling of other pins within the I/O bank. The pin locations and the crosstalk matrix are combined to characterize the impact of the crosstalk on the pins for the pin placement. Thereafter, a user may decide to alter the pin placement or alter the sampling interval for the pin to avoid sampling the pin when the crosstalk may affect the signal integrity. The method may be applied for multiple simultaneous switching noise cause mechanisms impacting the signal integrity. In this embodiment, a worst case cause mechanism from the individually quantified cause mechanisms is determined by comparing an impact of each of the cause mechanisms.

Abstract: A computer-implemented method of measuring bridge fault coverage for a test pattern for a circuit design to be implemented within a programmable logic device can include identifying simulation results and stuck at coverage of the circuit design for the test pattern (610, 620). Pairs of nets in the circuit design that are adjacent can be identified (625). Each type of bridge fault for which each pair is tested can be determined according to the simulation results (640, 645, 655, 660). A measure of bridge fault coverage for the test pattern can be calculated according to which types of bridge faults each pair is tested and which net of each pair acts as an aggressor for each type of bridge fault tested (675). The measure of bridge fault coverage can be output (680).

Abstract: An interconnection structure includes: first and second differential signal interconnections provided to transmit a differential signal; and first and second voltage interconnections applied with predetermined voltages. The first voltage interconnection, the first differential signal interconnection, the second differential signal interconnection and the second voltage interconnection are arranged in this order. An interval between the first and second differential signal interconnections is longer than an interval between the first voltage interconnection and the first differential signal interconnection and is longer than an interval between the second differential signal interconnection and the second voltage interconnection.

Abstract: A computer-implemented timing verification method for obtaining delay time for a signal propagated through a signal path and performing timing verification. The method stores a table including a wiring resistance variation amount and a wiring capacitance variation amount that are in accordance with a geometry deviation of a wire from a reference geometry, extracts a wiring structure of the signal path from a storage unit, extracts a wiring resistance variation amount and a wiring capacitance variation amount that correspond to the extracted wiring structure from the table, generates an on-chip-variation coefficient from the extracted wiring resistance variation amount and wiring capacitance variation amount, and calculates delay time for the signal propagated through the signal path based on the generated on-chip-variation coefficient.

Abstract: A computer implemented method, apparatus and program product provide automated processes for determining the most cost-effective use of airgaps in a microchip. The performance gains realized by using airgaps for a given net or layer may be calculated. These improvements may be paired to a monetary cost associated with implementing the applicable airgaps at that net/layer. The paired benefit and cost of the airgap scenario may be compared to other possible airgap uses at other layers/nets to determine which airgaps provide the best improvement for the lowest cost.

Abstract: A method and system for determining electrical parameter data for a layer of an integrated circuit that can include a nominal electrical parameter value, and sensitivity values which represent the sensitivities of the nominal electrical parameter value to variations in the nominal parameter values. A template of the layer geometry is provided from a portion of which a set of linear equations are developed and which equations are solved using a two step method and from which solution the nominal electrical parameter values are determined. An auxiliary set of the original linear equations is developed from the original set using the adjoint method and from the solution of the auxiliary set using the two step method the sensitivity values are calculated.

Abstract: An object is to simplify a power supply noise analysis model of a circuit board. CAD data of the circuit board is obtained from a CAD apparatus, and overlapping power supply islands among power supply islands existing in different layers of the circuit board are extracted as a power supply pair. Nodes are arranged in the extracted power supply pair, and the nodes of the power supply pair are projected on the power supply islands to which the power supply pair belongs. A mesh region which encloses each node is determined for each power supply island, and impedance (L, R, C) between nodes is calculated. Then, a power supply noise analysis model is created based on the impedance between nodes in each layer, and a capacitance between layers.

Abstract: Embodiments of the present invention provide a method of circuit design and circuit simulation. A method for electromagnetic simulation of passive structures of a circuit design is disclosed. The method comprises recognizing one or more geometries of the passive structures having certain geometric properties and electromagnetic properties, converting the one or more geometries to one or more primitives based on the geometric properties and numerically equivalent electromagnetic properties of the passive structures, constructing a physical topology incorporating the converted primitives and unconverted geometries, and simulating the physical topology to generate electromagnetic modeling of the passive structures of the circuit design.

Abstract: A method for simulating operation of a charge trapping memory cell which computes the amount of charge trapped by determining first tunneling current through the tunneling layer, determining second tunneling current out of the charge trapping layer to the gate, determining third tunneling current escaping from traps in the charge trapping layer and tunneling out to the gate, and integrating said tunneling currents over a time interval. A change in threshold voltage can be computed for a transistor including the charge trapping structure. The parameter set can include only physical parameters, including layer thickness, band offsets and dielectric constants.

Abstract: The invention relates to an electromigration analysis method and a system for analyzing one or more nets in a digital integrated circuit design that are at risk of electromigration. The method comprises the steps of providing at least one interconnect between a driver cell and at least one load cell; applying same extracted netlist data for noise and/or timing analysis and for electromigration analysis; modeling the driver cell by a train of trapezoidal voltage pulses transmitted from the driver cell to the one or more load cells through the at least one interconnect; extracting at least a slew rate of a driver voltage signal and/or timing information from a noise and/or timing analysis for the one or more nets; and comparing a locally measured current density in the at least one interconnect to an effective local maximum current density limit of the at least one interconnect.

Abstract: Static timing and/or noise analysis are performed on a netlist of an integrated circuit, to estimate behavior of the netlist and to identify at least one violation by said behavior of a corresponding requirement thereon, such as setup time, hold time or bump height in a quiescent net. Thereafter, effect of engineering change order (ECO) to correct the violation are automatically analyzed, based on the layout, the parasitics, the timing and/or noise behavior, and the violation, followed by generation of a constraint on the behavior (called “ECO” constraint), such as a timing constraint and/or a noise constraint. Next, the ECO constraint is automatically used, e.g. in a place and route tool, to select an ECO repair technique, from several ECO repair techniques that can overcome the violation. The selected ECO repair technique is automatically applied to the layout, to generate a modified layout which does not have the violation.

Abstract: A method for determining a current spectrum for a circuit design is provided. The method includes determining timing characteristics and power consumption characteristics for the circuit design. From the timing characteristics and the power consumption characteristics a time domain current waveform is constructed. The time domain current waveform is then converted to a frequency domain current waveform. With the frequency domain waveform, one skilled in the art can then identify a location and an amount of decoupling capacitors for a printed circuit board housing the circuit design based on the frequency domain current waveform. A computing system configured to perform the method is also provided.

Abstract: A design structure for a computer-aided design system for generating a functional design model of an integrated circuit design (having nets comprising wires) determines critical parameters for coupling noise between the wires of the nets and acceptable limits for the critical parameters. Further, methods herein include designing a ring oscillator to have stages, each of the stages measuring only one of the critical parameters. This ring oscillator is then included within an integrated circuit design and associated design structure. The embodiments herein produce an integrated circuit according to this integrated circuit design and operate the ring oscillator within the integrated circuit to measure the critical parameters of the integrated circuit and produce test results. These test results are output to determine whether the test results are within the acceptable limits.

Abstract: An orthogonal array is formed by performing electromagnetic field analysis only once and determining a range by using the mount position and type of a capacitor and the number of capacitors as parameters to perform circuit analysis a small number of times. An estimation equation is formed by using as an index a result of the absolute value of the calculated power source impedance, and a capacitor is disposed to reduce noises by using the estimation equation.

Abstract: A transmission delay analyzing apparatus includes: a first acquisition section that acquires a noise waveform from among waveforms which propagate in a first transmission line and acquired by a receiving circuit; a first calculation section that calculates a noise peak level which is the peak level of the noise waveform acquired by the first acquisition section; a second acquisition section that acquires a signal waveform free from noise from among the waveforms which propagate in the first transmission line and acquired by the receiving circuit; and a second calculation section that calculates a delay variation of a transmitted signal based on the signal waveform acquired by the second acquisition section, a threshold for determining the level of a signal that the receiving circuit has received from the first transmission line, and the noise peak level calculated by the first calculation section.

Abstract: Structures and a computer program product are provided for implementing enhanced wiring capability for electronic laminate packages. Electronic package physical design data are received. Instances of line width and space limit violations in the electronic package physical design data are identified. The identified instances of line width and space limit violations are evaluated using predefined qualified options and tolerance limitations and the electronic package physical design data are modified to optimize shapes to replace the instances of line width and space limit violations.

Abstract: A design structure integrated circuit (IC) system architectures that allow for the reduction of on-chip or across-chip transient noise budgets by providing a means to avoid simultaneous high current demand events from at least two functional logic blocks, i.e., noise contributors, are disclosed. Embodiments of the IC system architectures include at least one noise event arbiter and at least two noise contributor blocks. A method of scheduling on-chip noise events to avoid simultaneous active transient noise events may include, but is not limited to: the noise event arbiter receiving simultaneously multiple requests-to-operate from multiple noise contributors; the noise event arbiter determining when each noise contributor may execute operations based on a pre-established dI/dt budget; and the noise event arbiter notifying each noise contributor as to when permission is granted to execute its operations.

Abstract: The method comprises a number of simultaneously switching signals calculation step in which the number of simultaneously switching signals is calculated for each set of user setting information for the input and output signal on the basis of pin arrangement information and the user setting information of the pins in a neighboring area of a pin to be executed in the estimation process; and a simultaneous switching noise calculation step in which a difference is calculated between noise corresponding to an initial point and that to a terminal point in a range of the number of simultaneously switching signals calculated for each set of user setting information on the basis of a relationship between the number of simultaneously switching signals and the noise caused by the number of simultaneously switching signals for each set of user setting information.

Abstract: Induced crosstalk is predicted for the input/output pins of a programmable logic device. Signal edge rates for the input/output pin are determined from selected interface protocols for the input/output pins. For each pair of the input/output pins, a first coupling coefficient specifies a coupling between the pair of input/output pins within a package for mounting the programmable logic device to a printed circuit board. A depth is input for each via coupled to an input/output pin by the printed circuit board. From the via depths, a second coupling coefficient is determined for each pair of the input/output pins that satisfy a separation criterion. For each of the input/output pins, a predicted value of an induced crosstalk is determined from the first and second coupling coefficients for each pair that includes the input/output pin and another input/output pin, and from the signal edge rate of this other input/output pin.

Abstract: The invention discloses a method for tuning nano-scale analog-circuit designs in order to reduce random-device mismatches and optimize said design, where nano-scale devices potentially have large-scale process variations. The method includes providing a tunable circuit topology, wherein each nano-scale device comprises a single component or comprises multiple parallel components. Each component is decomposed into multiple discrete sub-components, wherein each said sub-component either operates in parallel with other like components to effectively operate like one bigger component. The sub-components are subjected to a dynamic-programming process to adaptively select the sub-components to be kept operational, while configuring the nonselected sub-components to be nonoperational, based on the measurement of at least one operational parameter.

Abstract: A method, apparatus and computer program product are provided for implementing vertically coupled noise control through a mesh plane in an electronic package design. Electronic package physical design data are received. Instances of vertically coupled noise in the electronic package physical design data are identified. The identified instances of vertically coupled noise are quantified. Then the electronic package physical design data are modified to limit the vertically coupled noise.

Abstract: Methods of designing a backplane, a backplane, and a packet switch using such a backplane are disclosed. The backplane comprises communication channels that connect each of a set of first card slots to each of a set of second card slots. Instead of forcing the backplane to route the communication channels to match a preset card configuration, the backplane communication channels are routed so as to reduce crosstalk and attenuation on at least the most difficult routing pairs. The cards perform logical translation of their backplane traffic to conform to the physical pin assignment for the particular card slot in which they are inserted. Other embodiments are also described and claimed.

Abstract: A method of reducing crosstalk induced noise in a physical circuit wiring design constructs a spatial vector for each interconnect wire segment in the physical circuit wiring design. The method compares the spatial vectors of said physical circuit wiring design and identifies any of the spatial vectors that are parallel to each other and have opposite directions. The method may identify all drivers and receivers in the physical circuit wiring design, and trace each interconnect line, starting with its driver, to determine a routed length from the driver to each segment break point of the interconnect line. The method may construct the spatial vector by defining an origin in the physical circuit wiring design. The method determines a starting point and an ending point of the spatial vector with respect to the origin. The starting point of the spatial vector is the break point of the interconnect wire segment closer to the driver.

Abstract: An improvement to a memory system having a hierarchical bitline structure wherein traces that form global write lines are connected to each other using junctions that include multiple vias to reduce capacitance and increase yield. At least one of a pair of traces connected by the vias includes a widened portion that provides sufficient overlap with the other trace to allow the two or more vias to be formed between the traces at the overlap. Parallel traces for global write lines that carry a write signal and its inverse may be positioned more than one maximum-density grid space apart to allow the widened portions to be formed between the traces. A global read line that is formed in a different metal layer from the global write line traces may be positioned in a grid space between the global write line traces to reduce the capacitance of this line.

Abstract: An approach for performing arbitrary waveform propagation through a logic gate using timing analysis results is described. In one embodiment, there is an arbitrary waveform propagation tool for determining an effect of noise on a digital integrated circuit having at least one logic gate. A timing analysis component is configured to perform a timing analysis on the at least one logic gate and a noise analysis component is configured to perform a noise analysis. A waveform propagation model synthesizer component is configured to dynamically synthesize a waveform propagation model as a function of the timing analysis. The waveform propagation model synthesizer component is further configured to apply an arbitrary voltage waveform comprising one of a noisy waveform or noise glitch waveform and determine an effect of the arbitrary voltage waveform on the at least one logic gate from the dynamically synthesized waveform propagation model.

Abstract: Some embodiments provide a method of providing configurable ICs to a user. The method provides the configurable IC and a set of behavioral descriptions to the user. The behavioral descriptions specify the effects of accesses to a memory by a set of memory ports given a set of parameters chosen by the user.

Abstract: Operations are performed in EDA tools that operate upon partitions or discrete portions of an electronic design, in which the partitions or discrete portions of the design are expanded to account for effects to/from other areas in the design. Identification is made of the portions of the design that are external to the partitions, and depending upon the type of expected effects, would then be considered during optimization and analysis of the partitions. This is implemented by logically expanding the partition to include consideration of the external portions during timing optimization and analysis. By considering an expanded partition for timing optimization and analysis, it is possible to identify unintended problems caused by the timing optimization at an earlier stage of the design process.

Abstract: In one general embodiment, a method is provided. In operation, a first phase noise in a first circuit located on an integrated circuit is determined. Additionally, a second phase noise in a second circuit coupled to the first circuit but which is not located in the integrated circuit is determined, the second circuit being programmable. Furthermore, the first phase noise is compared with the second phase noise. Also, the second circuit is conditionally modified to optimize the performance of the integrated circuit, based on a result of the comparison. Additional methods are also presented.

Abstract: A semiconductor integrated circuit includes a shielded wire line and a shielding wire line provided for the shielded wire line and divided into a plurality of segments in a longitudinal direction of the shielded wire line.

Abstract: A parasitic element extracting system includes: a classifying section configured to classify each of interconnection layers of a layout structure of a semiconductor device into one of an upper interconnection layer and an lower interconnection layer based on a predetermined criterion; and a marker producing section configured to generate a marker to indicate a via-contact connecting the upper interconnection layers and the lower interconnection layers. An upper layer parasitic element list producing section is configured to generate an upper layer parasitic element list by extracting parasitic elements in the upper interconnection layers based on a first criterion, and a lower layer parasitic element list producing section is configured to generate a lower layer parasitic element list by extracting parasitic elements in the lower interconnection layers based on a second criterion which is different from the first criterion.

Abstract: One embodiment of the invention provides a multi-layered ceramic package. The ceramic package includes a signal layer having a plurality of signal lines and a mesh reference layer parallel to the signal layer. The mesh reference layer includes a plurality of intersecting reference lines of varying reference-line width in the plane of the mesh layer. The mesh reference lines may be widened in locations of probable signal cross-talk. Other embodiments of the invention include software for optimizing a ceramic package design by selectively widening mesh lines in regions of probable cross-talk, and systems for designing and manufacturing such a ceramic package.

Abstract: A method, system, and computer program product for coupled noise timing violation avoidance in detailed routing of an integrated circuit design are provided. The method includes calculating a noise induced timing violation sensitivity (NITVS) metric for nets in the integrated circuit design as a measure of sensitivity to a timing violation relative to a coupled noise delay adder, prioritizing routing isolation as a function of the NITVS metric for each of the nets to avoid coupled noise timing violations, and outputting the routing isolation priority.

Abstract: Systems and methods provide improved techniques directed to simultaneous switching output (SSO) noise, which for example may be applied during the programmable logic device design process. For example in accordance with an embodiment, a method of structuring simultaneous switching output (SSO) noise data for an electronic device includes collecting hardware data on SSO noise conditions; generating additional data on SSO noise conditions based on the hardware data; and structuring the hardware data and the additional data to form data tables for SSO noise calculations.

Abstract: The electrical circuit timing method provides accurate nominal delay together with the delay sensitivities with respect to different circuit elements {e.g., cells, interconnects, etc.) and variational parameters (e.g., process variations; environmental variations). All the sensitivity computations are based on closed-form formulas; as a consequence, the method provides rapidly and at low cost high accuracy and high numerical stability.

Abstract: A design support program stored in a recording medium readable by a computer includes acquiring a first analysis result including information about an area included in circuit information of a design target circuit and a second analysis result relating to a path of the circuit information, the temperature of the area being equal to or higher than a certain temperature; determining an arbitrary cell on a non-critical path from among cells arranged in the area as a target cell for decreasing the area temperature; and outputting a result of the determination.

Abstract: Systems and methods for hierarchical noise analysis of digital circuits, wherein analysis of a cell is based on the configuration of the cell itself and also the upstream circuit components that are connected to the inputs of the cell. One embodiment comprises a method for noise analysis in an electronic circuit such as a digital CMOS circuit. The method includes identifying a cell and identifying the inputs of the cell. For each of the inputs of the cell, a corresponding first upstream circuit component is identified. The identified component is the first component upstream from the cell's input and is directly connected to the input. A noise analysis for the cell is performed based upon the configuration of the cell in combination with the identified upstream circuit components. The result of the analysis for the combination of the cell and the upstream circuit components can then be stored.