Abstract: Method of analyzing noise sensitivity of integrated circuits having at least one memory storage device and a noise sensitivity analyzer. In one embodiment, the noise sensitivity analyzer includes a circuit reservoir, a circuit parser and a circuit evaluator. The circuit reservoir is configured to receive and store a model of a circuit having at least one memory storage device to be analyzed. The circuit parser is configured to identify nodes of the model. The circuit evaluator is configured to apply a large test current to each of the nodes for multiple circuit states of the at least one memory storage device and determine which of the nodes are sensitive nodes.

Abstract: Disclosed are embodiments of a system and of an associated method for estimating the leakage current of an electronic circuit. The embodiments analyze a layout of an electronic circuit in order to identify all driven and non-driven nets within the electronic circuit, to identify all of the driven net-bounded partitions within the electronic circuit (based on the driven and non-driven nets), and to identify, for each driven net-bounded partition, all possible states of the electronic circuit that can leak. Then, using this information, the embodiments estimate the leakage current of the electronic circuit. This is accomplished by first determining, for each state of each driven net-bounded partition, a leakage current of the driven net-bounded partition and a probability that the state will occur in the driven net-bounded partition during operation of the electronic circuit.

Abstract: An instantiation of a standard cell is placed at a location of a device design. The standard cell includes a designation identifying a sensitive feature of the standard cell. An instantiation of a filler cell is placed at a selective location of the device design based on the designation.

Abstract: The invention generally relates to systems and methods for modeling I/O simultaneous switching noise, and, more particularly, to systems and methods for modeling I/O simultaneous switching noise in a selected chip window area while accounting for the effect of current sharing among neighbors. A method includes determining a current sharing factor of areas of an integrated circuit (IC) chip package, and determining an offload scaling factor of the IC chip package based upon the current sharing factor and numbers of I/O devices in neighboring areas of the IC chip package.

Abstract: In designing an integrated circuit on a die having a set of die bumps, a method to generate a set of lumped circuit parameter values associated with the set of die bumps, based upon distances between the set of die bumps and the center of the die, the method also based upon a sample-data distribution function of a die bump distance variable and a sample-data distribution function of a lumped circuit parameter variable. Other embodiments are described and claimed.

Abstract: In order to make it possible to automatically execute a wiring process which satisfies not only a design condition but also design quality relating to an electric characteristic, according to the embodiment, an automatic wiring apparatus includes a design condition changing section for changing a design condition in accordance with priority information regarding the design condition where a wiring process which satisfies the design condition cannot be carried out by a first wiring processing section, a quality allowability decision section for deciding whether or not quality of a wiring region can be allowed where a wiring process which satisfies the design condition after the changing can be executed by a second wiring processing section and an outputting section for outputting a result of the wiring process of the wiring region by the second wiring processing section if it is decided that the quality of the wiring region can be allowed.

Abstract: Apportioning unequally contributions of different metal paths of a circuit to electromigration (EM) reliability. In an embodiment, a corresponding parameter value representing a magnitude of excess current flowing in a single direction in each metal path is determined. A desired reliability measure for electromigration (EM) is apportioned among the metal paths based on computed parameter values for the corresponding metal path. A reliability analysis for the circuit is performed based on the apportioning. In an embodiment, metal paths which predominantly carry currents with an average value less than a threshold are excluded from being considered as contributors to EM degradation.

Abstract: A printed circuit board analyzing system for analyzing the whole circuit of a multilayer printed circuit board to perform circuit analysis of noise propagation in the printed circuit board having structure in which the shapes of stacked conductor planes are different or planes are provided side by side in the same layer by quickly providing an adjacent interference part equivalent circuit model representing noise interference parts causing interference between adjacent opposed planes and by coupling the plane pairs to the adjacent interference part equivalent circuit.

Abstract: In a support apparatus for analysis and design of a semiconductor device, a function indicating an impurity concentration distribution in a channel region of a first transistor in a depth direction is set. A structure data indicating a structure of a transistor device and a measurement value of each of electric characteristics of the transistor are related. A Poisson's equation, which is express by using the function, is solved by using a depletion layer width as a variable to calculate a surface potential, and a first calculation value of the electric characteristic of the first transistor is calculated by using the surface potential. A determining section determines the function to indicate the impurity concentration distribution of a first transistor when a measurement value corresponding to a first structure data which indicates a structure of the first transistor, and the first calculation value are substantially coincident with each other.

Abstract: The method comprises a number of simultaneously switching signals calculation step in which the number of simultaneously switching signals is calculated for each set of user setting information for the input and output signal on the basis of pin arrangement information and the user setting information of the pins in a neighboring area of a pin to be executed in the estimation process; and a simultaneous switching noise calculation step in which a difference is calculated between noise corresponding to an initial point and that to a terminal point in a range of the number of simultaneously switching signals calculated for each set of user setting information on the basis of a relationship between the number of simultaneously switching signals and the noise caused by the number of simultaneously switching signals for each set of user setting information.

Abstract: A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.

Abstract: A wiring layout method includes designing a layout of a power wiring for an integrated circuit; designing a layout of plural signal wirings for the integrated circuit; comparing the signal frequency; classifying the signal wirings; calculating an evaluation value of a temperature rise; and modifying the layouts of the integrated circuit.

Abstract: A circuit analysis tool is provided, enabled with software instructions, for minimizing circuit crosstalk. The instructions provide a first circuit connected to an output mode, having a last gate with a plurality of inputs and an output. The instructions calculate a first circuit victim net delay range (timing window) having a minimum delay (Vmin) and a maximum delay (Vmax). A second circuit is provided having an output connected to the output node to supply an aggressor net delay range (A1) having a minimum delay (A1min) and a maximum delay (A1max). The aggressor net delay range at least partially overlaps the victim net delay range. Without increasing the value of Vmax (critical path timing), the first circuit victim net delay range is shrunk, thereby minimizing crosstalk between the first and second circuits without an increase in first circuit maximum signal delay.

Abstract: A printed circuit board with reduced signal distortion, including one or more layers of non-conductive substrate upon which are disposed conductive pathways that conduct signals, the signals characterized by distortion at least partly caused by orientation of the conductive pathways on the layers of the printed circuit board, and a periodically patterned reference plane; each conductive pathway that conducts signals oriented orthogonally or diagonally at forty-five degrees with respect to other conductive pathways that conduct signals on the printed circuit board; the periodically patterned reference plane comprising a conductor having discontinuities arranged in a periodically recurring pattern, the pattern of the discontinuities oriented on a surface of a layer of the printed circuit board at an optimum angle, with respect to the conductive pathways that conduct signals on the printed circuit board, that reduces distortion of the signals.

Abstract: Disclosed is a method of analyzing power supply noise including: extracting power supply and ground information as well as a capacitor and an LSI chip connected to a power supply and ground from electronic circuit design information; creating an analytical model of power supply noise by connecting respective models of the impedance characteristics of the capacitor and LSI chip to mounting positions of a board model; calculating reflected voltage at the LSI chip based on an impedance characteristic between the power supply of the LSI chip and ground; calculating power supply noise from the LSI chip to the electronic circuit board; based on the reflected voltage at the LSI chip.

Abstract: A computer determines a first relationship between a maximum frequency of the semiconductor device and an internal power supply voltage of the semiconductor device. Then, the computer determines a second relationship between the maximum frequency and an amount of noise, based on a number of the input/output signal pins. In addition, the computer estimates a fluctuation of the internal power supply voltage corresponding to a amount of noise of the semiconductor device, based on the first relationship and the second relationship. Then, the computer performs a design change of the semiconductor device based on the estimated fluctuation. And the computer stores the changed design of the semiconductor device to a storage device.

Abstract: An aspect of the present invention validates ESD compliance by examining netlist data generated from a schematic level design of an integrated circuit. Routing and placement may be performed only after confirming that whether each protected circuit (having exposure to ESD current, without the protection circuit) is protected by an appropriate protection circuit. As a result, the design cycle time may be reduced. According to another aspect of the present invention, layout guidelines for each protection circuit is also considered in performing the routing and placement. As a result, the number of iterations in a design cycle may be reduced.

Abstract: A substrate noise checking methodology is disclosed. A tool is provided that aggregates the noise effect of one or more of digital noise injectors on one or more receptors. The tool also provides a propagation macro-model for the noise from the digital noise injectors. With both models combined, full chip substrate noise assessment flow can be achieved.

Abstract: A design assisting apparatus includes a memory configured to store routing information representing first wire line from wire lines of a module belonging to a first layer of a semiconductor circuit having a plurality of layers, the first wire line likely to become either one of an aggressor net and a victim net in a crosstalk noise check performed on wire lines of a module belonging to a second layer hierarchically higher than the first layer, and a processor configured to perform a wire line identifying operation identifying second wire line within the module belonging to the second layer, and likely to become either one of an aggressor net and a victim net in the crosstalk noise check performed on the first wire line represented by the routing information stored on the memory.

Abstract: A semiconductor device design support apparatus for generating a substrate netlist so as to be able to perform substrate noise analysis with high accuracy in a short time. The semiconductor device design support apparatus comprises a unit that divides a semiconductor device layout into a plurality of segments and generates a macro-model of the segments by using a current waveform of an instance included in the divided segments; a unit that replaces a pattern (termed as “substrate interface”) that is designed to be an interface with a substrate with respect to the segments, by a prescribed substrate interface diagram; and a unit that generates a substrate netlist, based on the substrate interface diagram of the plurality of segments.

Abstract: Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed.

Abstract: A method to at least partially isolate a net of a circuit design is provided and includes testing a timing characteristic of a circuit design, identifying from a result of the testing a net of the circuit design to be at least partially isolated from an adjacent net and determining a percentage of the identified net to be partially isolated.

Abstract: Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed.

Abstract: Disclosed is a method for design validity verification of an electronic circuit board with regard to power supply noise, wherein with regard to an i-th LSI (i=1 to n) on the electronic circuit board, an input voltage Vin[i] to the LSI from the printed circuit board is given by Vin[i]=VDD?Zlsi[i]×VDD/(Zlsi[i]+Z11[i]), where Zlsi[i] is an input impedance characteristic and Z11[i] is a reflected impedance characteristic viewed from a position at which the i-th LSI is mounted, being a characteristic with the i-th LSI omitted from the whole of the electronic circuit board and a judgment is made as to whether or not a reflected voltage Vr[i]=Vin[i]×(Zlsi[i]+Z11[i])/(Zlsi[i]?Z11[i]) satisfies |Vr[i]|??V (power supply variation tolerance range).

Abstract: Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed.

Abstract: A logic simulation apparatus includes: a jitter detector generation section 21 that generates information concerning a jitter circuit for determining whether a time variation occurs in signal passing between a first circuit and a second circuit, the first circuit configured to output a signal with a clock output from a predetermined clock source and the second circuit configured to output a signal with a clock output from a clock source different from the above predetermined clock source; and a constraint solver generation section 22 that generates information concerning a solver that is configured to create a signal to be output at an observation point using a logical expression of an output signal of the second circuit and output, based on the logical expression and output signal of the jitter detector circuit, a signal constrained by the output signal of the jitter detector circuit and output signal of the second circuit.

Abstract: A sensitivity analysis system has a memory device in which an interconnect structure data indicating an interconnect structure included in a semiconductor device is stored. The interconnect structure has: a main interconnection; and a contact structure electrically connected to the main interconnection and extending toward a semiconductor substrate. Parameters contribute to parasitic capacitance of the interconnect structure, and variation of each parameter from a design value caused by manufacturing variability is represented within a predetermined range.

Abstract: Methods, computer programs, and systems for designing an electronic component are presented. One method calculates a first Simultaneous Switching Noise (SSN) on Input/Output (IO) pins using a first configuration of the electronic component. A setting or a placement of a chosen IO pin is changed to obtain a second configuration of the electronic component, and a second SSN on IO pins is obtained based on the results of the first SSN and based on new SSN calculations related to the changed setting or placement. The second SSN on an IO pin, other than the chosen IO pin, is calculated by subtracting from the first SSN on the IO pin the SSN caused by the chosen IO pin calculated in the first SSN, and by adding an incremental SSN caused by the chosen IO pin on the pin in the second configuration. The method further includes the operation of creating a design for the electronic component with either the first or the second configuration based on the results of the first and the second SSN.

Abstract: A computer-implemented method of determining parasitic capacitance for transistors within an integrated circuit can include determining a first set of coefficients for a first expression that calculates parasitic capacitance for a transistor structure according to a first plurality of parasitic capacitances derived from a plurality of two-dimensional transistor structures (320). The first set of coefficients can be inserted into the first expression (325). The method further can include determining a second set of coefficients for a second expression that calculates parasitic capacitance for a transistor structure according to a second plurality of parasitic capacitances derived from a plurality of three-dimensional transistor structures (345). The second expression can include the first expression (350). The method can include inserting the second set of coefficients into the second expression and outputting the second expression (355).

Abstract: A method for designing wiring topology for electromigration avoidance, which is composed of multiple sources, multiple sinks and multiple wires, is disclosed. The steps of said method to get an optimal topology includes: 1. calculating the length of all the wires to choose one of the wires with the shortest length as a feasible wire, 2. deciding a capacity of the feasible wire, 3. deciding the capacities of the other wire according to the capacity of the feasible wire, a flow of the source of the feasible wire and a flow of the sink of the feasible wire, 4. comparing the length of the other wires to select another feasible wire, 5. repeating said steps until finding all feasible wires for constructing a feasible topology, 6. creating a flow network according to the feasible topology, 7. iteratively checking if a negative cycle exists in the flow network and removing it until no more negative cycles.

Abstract: A method for accurately determining the shape of currents in a current spectrum for a circuit design is provided. The method includes determining timing characteristics and power consumption characteristics for the circuit design. In one embodiment, the timing characteristics are provided through a electronic design automation tool. The timing characteristics yield a current pulse time width. In another embodiment, the power consumption characteristics are provided by an EDA tool. The power consumption characteristics yield a current pulse amplitude. The shape of the current pulse is obtained by incrementally processing a power analyzer tool over relatively small time increments over one or more clock cycles while capturing the switching nodes of a simulation of the circuit design for each time increment. In one embodiment, the time increments are one nanosecond or less.

Abstract: A semiconductor device has an interconnect structure that includes a main interconnection and a contact structure. Parameters contributing to parasitic capacitance and interconnect resistance of the interconnect structure include: main parameters including width/thickness of the main interconnection; and sub parameter. Variation of each parameter from a design value caused by manufacturing variability is represented within a predetermined range. A method of designing the semiconductor device includes: calculating the maximum capacitance value, the minimum capacitance value, the maximum resistance value and the minimum resistance value of the interconnect structure under a condition that respective variation amplitudes of the main parameters do not simultaneously take maximum values and variation of the sub parameter is fixed to a predetermined value; generating a CR-added netlist; and performing operation verification of the semiconductor device by using the CR-added netlist.

Abstract: Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed.

Abstract: Disclosed is a method of implementing controlled equivalent series resistance (ESR) having low equivalent series inductance (ESL) of a multi-layer chip capacitor which includes a plurality of internal electrodes each having first polarity or second polarity which is opposite to the first polarity, and dielectric layers each disposed between the internal electrodes of the first polarity and the second polarity, wherein the internal electrodes having the first polarity and the internal electrodes having the second polarity are alternated at least once to form one or more blocks being stacked.

Abstract: A structure, apparatus and method for circuits to minimize sensitivity to latch. The method includes, for example, identifying element density of at least one functional circuit block and element attributes of elements associated with the at least one functional circuit block. An element density function parameterized from the element attributes is formed. The placement of the at least one functional circuit block is modified relative to other functional circuit blocks based on the element density function to substantially eliminate latching effects in a circuit.

Abstract: Disclosed is a method including: calculating power supply input impedance of the LSI from the number of output buffers of the LSI, output impedance of an output buffer, signal characteristic impedance and characteristic impedance of power supply/ground of an LSI terminal, a package, and a chip terminal part, characteristic impedance of wiring connected to an LSI output terminal, and output signal damping resistance calculating a reflected voltage of power supply noise at a semiconductor device mounted on an electronic circuit board, based on impedance characteristic between a power supply and ground of the semiconductor device; and analyzing power supply noise of the electronic circuit board, based on the reflected voltage of the power supply noise at the semiconductor device.

Abstract: Disclosed are a method, system, and computer program product for providing customizable information in designing electronic circuits with electrical awareness. The method or the system displays a portion of a physical design of an electronic circuit in a first display area. The method or the system receives or identifies a user's or a system's manipulation of the portion of the physical design of the electronic circuit. The method or the system then determines and displays an in situ response to the manipulation in the first display area. The method or the system may further display, in the first display area or in another display area, result(s) relating to the physical data of a component, electrical parasitic(s) associated with the physical data, electrical characteristic(s) associated with the physical data or the electrical characteristic(s), or other element(s) of the physical design that is impacted by the manipulation.

Abstract: A semiconductor integrated circuit design supporting system has a memory unit which stores cell information containing the number of power supply pads formed at a chip as well as names and the number of a plurality of IO cells, and a drive factor definition file defining a drive factor of each of the plurality of IO cells, a pad laying out section which tentatively lays out the power supply pads and input-output pads corresponding to the IO cells, using the cell information, a package virtual designing section which prepares a package drawing based on coordinates of the power supply pads and the input-output pads, which have been tentatively laid out, an electric characteristics data calculating section which calculates inductance of the power supply pads, using the package drawing, and a noise risk calculating section which calculates noise risk of each of the input-output pads, using the inductance and the drive factor definition file.

Abstract: According to a circuit board creation program presented herein, a simulation assuming a case in which an addition of a bypass capacitor near a another bypass capacitor provided between a pin and via of an LSI part can be performed, simply by adding a bypass capacitor property model and changing the value of a coefficient parameter by which the property value of an element of a line part is to be multiplied or divided.

Abstract: A design structure for a computer-aided design system for generating a functional design model of an integrated circuit design (having nets comprising wires) determines critical parameters for coupling noise between the wires of the nets and acceptable limits for the critical parameters. Further, methods herein include designing a ring oscillator to have stages, each of the stages measuring only one of the critical parameters. This ring oscillator is then included within an integrated circuit design and associated design structure. The embodiments herein produce an integrated circuit according to this integrated circuit design and operate the ring oscillator within the integrated circuit to measure the critical parameters of the integrated circuit and produce test results. These test results are output to determine whether the test results are within the acceptable limits.

Abstract: A method of optimizing the signal propagation speed on a wiring layout is provided. In general, the method accounts for and uses inductance effects caused by the propagation of a high-speed signal on a signal wire surrounded by parallel ground wires. In particular, one of the physical parameters defining the wiring layout may be adjusted to create an rlc relationship in the wiring layout that maximizes the signal propagation speed. The physical parameter that is adjusted may be, for example, the wire separation between the signal wire and the ground wires or the width of the ground wires. The disclosed method may also be applied to a wiring layout having multiple branches, such as a clock tree. In this context, a first branch may be optimized using the disclosed method. Downstream branches may then be adjusted so that the impedances at the junction between the branches are substantially equal.

Abstract: To provide a simulation technology of ending multiphysics analysis on heat, vibration, and EMC within a practical time and with a low-price computation process at an early stage of product designing, in a noise analysis designing method for an electric device, such as an inverter for automobile, this electric device includes one or more energy sources, a propagation path through which energy from the energy source propagates, and a noise occurring part where an electromagnetic radiated noise occurs due to the energy coming from the propagation path, the method has a step of estimating the occurring noise, such as a occurring radiated noise, by analyzing a path specified by a user by using a calculator, and the path specified by the user is a path of the energy flowing through the propagation path.

Abstract: A method for the prediction of simultaneous switching output (SSO) noise that may be generated by one or more signal conduction paths within an electrical system. Electrical disturbance waveforms are first recorded for each signal conduction path that may be affected by the electrical disturbances. Next, principles of superposition are utilized to coherently combine each of the electrical disturbance waveforms in the time domain to generate the predicted SSO noise waveform that is imposed upon the affected signal conduction path. The electrical disturbance waveforms may be produced either by using bench measurements performed on an actual integrated circuit, by simulation, or by a combination of simulation and bench measurements.

Abstract: A method, system, and computer program product are disclosed for performing crosstalk analysis using first-order parameterized analysis modeling. The approach can be used to factor in the effect of process variations within the definition of timing windows. This approach allows one to bypass the simplistic assumptions related to best-case/worst-case analysis using timing windows, and provide a realistic picture of the impact of timing windows on noise analysis. The timing windows can be viewed in terms of the individual process parameter. The process parameters could be real process parameters, or virtual/computed components based on the actual process parameters. The process parameters can be used to compute overlap of timing windows for performing noise analysis.

Abstract: A power noise cycle is obtained from a dynamic IR drop analysis and a delay of a delay pass is a multiple of the noise cycle. Thereby, a delay increment and a delay decrement of a power noise amount (delay time×power noise amplitude) received when an internal signal of the semiconductor integrated circuit passes through a delay pass circuit are approximately the same.

Abstract: In an initial stage of device design, a circuit analysis control unit of an evaluation board stores SSO noise basic characteristic data actually measured by the evaluation board in an SSO noise basic characteristic data storage unit, and an SSO noise calculation unit calculates a rough amount of SSO noise on the basis of the SSO noise basic characteristic data. After a noise check is OR, the design proceeds, and a PCB parameter is determined, a circuit analysis control unit acquires the SSO noise basic characteristic data according to actual device PCB design information, and corrects the SSO noise basic characteristic data in the SSO noise basic characteristic data storage unit. Then, the SSO noise calculation unit performs a detailed analysis of an amount of SSO noise using the corrected SSO noise basic characteristic data.

Abstract: A simulation method, to be implemented in a computer, carries out a simulation of a semiconductor integrated circuit. The simulation method carries out a layout analysis based on layout data of a circuit formed by cells and stores values of layout parameters obtained by the layout analysis. Basic cell characteristics of the cells are read from a net list representing the extracted basic cell characteristics by the layout parameters and the basic cell characteristics represented by the layout parameters are stored. The stored values of the layout parameters are read and substituted into the basic cell characteristics represented by the layout parameters to obtain cell characteristics, and the cell characteristics are stored. An operation of the circuit is analyzed using the cell characteristics that are obtained.

Abstract: Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed.

Abstract: A latch conversion circuit which is to be added to a basic logic circuit to obtain a latch circuit having an extremely small through delay amount is prepared in advance. Moreover, provided is means for obtaining a latch circuit position whereat the shifting of the clock edge, such as skew or jitter, can be absorbed to the maximum extent possible, and for forming a latch circuit by adding the latch conversion circuit to the basic logic circuit located at the obtained point. Accordingly, a latch circuit which is not, to the extent possible, affected by skew or jitter can be designed.

Abstract: An IC designing method includes planning placement of a first isolated-power supplied region operating between common ground and power bus lines during a normal operation, and second/third isolated-power supplied regions each operating between the common ground bus line and first/second isolated power lines and supplied with potentials different from the common power supply, planning placement of first electrostatic protection circuits connected between the common ground power bus lines and between the common ground bus line and the first/second isolated power lines, and second electrostatic protection circuits connected between the first/second isolated power lines and the common power bus lines, judging presence of a signal transmission between non-adjacent regions among the first to third isolated-power supplied regions, and amending the circuit to insert a buffer circuit powered by the common power bus line in a transmission path when the signal transmission is present.