Abstract: A technology specific information to design the integrated circuit is received. A plurality of canonical hierarchical models to capture an integrated circuit capacitance are created. The plurality of canonical hierarchical models includes at least a canonical model to capture a capacitance of a device having a plurality of conductors, and a canonical model to capture a capacitance between at least a portion of the device and one or more other conductors of the integrated circuit. The canonical hierarchical models can be applied to a layout of the integrated circuit. A capacitance for the layout can be determined based on the canonical hierarchical models.

Abstract: A system and method are provided for reducing signal skew. The method includes receiving a netlist having components and connections among the components. Each connection has at least one signal wire. A plurality of net groups is identified, each net group including at least some of the connections and for which equivalent routing is desired. For each net group, the method includes systematically routing connection paths between the components for the connections, each connection path extending between an output of one of the components and an input to at least one other of the components and including at least one path fragment. Routing includes, for at least one of the connections of the net group, routing at least one grounded shielding wire in a routing channel adjacent and parallel to at least one of the path fragments of the connection path.

Abstract: In one embodiment of the invention, a multi-CCC current source model is disclosed to perform statistical timing analysis of an integrated circuit design. The multi-CCC current source model includes a voltage waveform transfer function, a voltage dependent current source, and an output capacitor. The voltage waveform transfer function receives an input voltage waveform and transforms it into an intermediate voltage waveform. The voltage dependent current source generates an output current in response to the intermediate voltage waveform. The output capacitor is coupled in parallel to the voltage dependent current source to generate an output voltage waveform for computation of a timing delay.

Abstract: The invention generally relates to systems and methods for modeling I/O simultaneous switching noise, and, more particularly, to systems and methods for modeling I/O simultaneous switching noise in a selected chip window area while accounting for the effect of current sharing among neighbors. A method includes determining a current sharing factor of areas of an integrated circuit (IC) chip package, and determining an offload scaling factor of the IC chip package based upon the current sharing factor and numbers of I/O devices in neighboring areas of the IC chip package.

Abstract: A technique for determining stress in interconnects of an integrated circuit design includes generating a maximal spanning tree of a directed graph. The directed graph represents an interconnect of an integrated circuit design. The technique also includes locating a first point on the spanning tree that has a lowest stress and a second point on the spanning tree that has a highest stress. The technique further includes determining whether a maximum first stress between the first and second points is less than a critical stress.

Abstract: A multi-transformer LLC (resonant) power converter having at least two transformers including a first T1 and a second transformer T2 in series includes a switch network configured for receiving input power including a first and second switched node. Resonant circuitry is coupled between the first and second switched node including a series combination of an inductor, a capacitor, a primary winding of T1 and a primary winding of a T2. At least one switch is operable for providing a first mode that includes T2 in the resonant circuitry and a second mode that excludes T2 from the resonant circuitry. Secondary windings of T2 and T1 are connected electrically in parallel for driving an output capacitor (Co) through respective rectifiers which provide conversion from AC to DC.

Abstract: A system and method are provided for laying out an integrated circuit design into a plurality of circuit layout cells having gaps therebetween, and inserting into each given one of at least a subset of the gaps, a corresponding filler cell selected from a predefined database in dependence upon a desired effect on a performance parameter of at least one circuit cell adjacent to the given gap. The circuit layout cells may be arranged in rows, and in some embodiments the selection of an appropriate filler cell for a given gap depends upon effects desired on a performance parameter of both circuit cells adjacent to the given gap. The predefined filler cells can include, for example, dummy diffusion regions, dummy poly lines, N-well boundary shifts and etch stop layer boundary shifts. In an embodiment, circuit layout cells can be moved in order to accommodate a selected filler cell.

Abstract: In an example embodiment, the system obtains the mutual inductance (e.g., Mij) between a quiet I/O buffer and each switching I/O buffer on a PLD from an automatic SSN measurement system. The system calculates the corrected mutual inductance between the quiet I/O buffer and each switching I/O buffer by multiplying the mutual inductance by a correction factor (e.g., ?j). The system multiplies each corrected mutual inductance by the rate of current flowing through the switching I/O buffer to obtain an induced voltage resulting from the switching I/O buffer. The system sums the induced voltages for all the switching I/O buffers on the PLD to obtain an estimate of total induced voltage caused in the quiet I/O buffer by all switching I/O buffers. The correction factor is based on bench measurements and depends on the amplitude of the simultaneous switching noise affecting each switching I/O buffer.

Abstract: Aspects of the invention relate to techniques for extracting admittance values associated with through-silicon vias in an integrated circuit system. A function fitting process is performed to generate parameters of a representation for electro-quasi-static potential Green's functions at a plurality of frequencies of interest based on integrated circuit manufacturing process information. Based on the generated parameters, a set of electric potential basis functions, a set of electric displacement basis functions and layout information for a layout design of interest, matrix elements of a matrix for each frequency in the plurality of frequencies of interest may be computed. The matrix is a part of a linear system that formulates a relationship of electric displacement fields and electric potentials in various regions associated with through-silicon vias in the layout design. Based on the matrix, admittance values associated with the through-silicon vias are computed.

Abstract: A method for a power layout of an integrated circuit. The method includes providing at least one unit power cell. The unit power cell includes at least one power grid cell. Each power grid cell has at least one first power layer configured to be coupled to a high power supply voltage and at least one second power layer configured to be coupled to a lower power supply voltage. The first power layer has conductive lines in at least two different directions and the at least one second power layer has conductive lines in at least two different directions. The method further includes filling a target area in the power layout by at least one unit power cell to implement at least one power cell.

Abstract: The electrical circuit timing method provides accurate nominal delay together with the delay sensitivities with respect to different circuit elements (e.g., cells, interconnects, etc.) and variational parameters (e.g., process variations; environmental variations). All the sensitivity computations are based on closed-form formulas; as a consequence, the method provides rapidly and at low cost high accuracy and high numerical stability.

Abstract: Techniques are described for generating asynchronous circuits (e.g., in the form of one or more netlists) for implementation, e.g., in integrated circuitry/chips. Embodiments are directed to asynchronous multi-level domino design template and several variants including a mixture of domino and single-rail data logic. The templates can provide high throughput, low latency, and area efficiency. A multi-level domino template is partitioned into pipeline stages in which each stage consists of potentially multiple-levels of domino logic controlled by a single controller that communicates with other controllers via handshaking. Each stage is composed of two parts: a data path and a control path. The data path implements the computational logic, both combinational and sequential using efficient dual-rail domino logic. The control path implements a unique four-phase handshake to ensure correctness and the preservation of logical dependencies between pipeline stages.

Abstract: Systems and techniques for performing parasitic extraction on a via array are described. If the via array is a single row or column via array, the system identifies a first via and a last via in the via array, and merges a set of vias between the first via and the last via into a center via. If the via array is a M×N (M?2, N?2) via array, the system merges the vias as follows: the first row and the last row of vias in the via array into a first row via and a last row via, respectively; the first column and the last column of vias in the via array into a first column via and a last column via, respectively; and a set of vias between the first and last rows and the first and last columns into a center via.

Abstract: To provide a simulation technology of ending multiphysics analysis on heat, vibration, and EMC within a practical time and with a low-price computation process at an early stage of product designing, in a noise analysis designing method for an electric device, such as an inverter for automobile, this electric device includes one or more energy sources, a propagation path through which energy from the energy source propagates, and a noise occurring part where an electromagnetic radiated noise occurs due to the energy coming from the propagation path, the method has a step of estimating the occurring noise, such as a occurring radiated noise, by analyzing a path specified by a user by using a calculator, and the path specified by the user is a path of the energy flowing through the propagation path.

Abstract: A method of designing an integrated circuit (IC) includes simulating aging evolution of the IC by providing a standard cells library, and a device activity file of device electrical activity in the standard cells as a function of electrical activity at the pins of the standard cells, taking into account Hot Carrier Injection, Negative Bias Temperature Instability, and gate oxide breakdown. A standard cell evolution file is provided that stores electrical characteristic aging data of standard cells. An instance activity file is provided of simulated electrical activity at the pins of individual instances of the cells in the IC. The instance activity file and the device activity file are used to analyze device activity and consequent aging evolution of the devices, and then generate data for consequent aging evolution of the IC. The IC design can then be modified to account for the aging evolution.

Abstract: A method calculates a total source/drain resistance for a field effect transistor (FET) device. The method counts the number (N) of contacts in each source/drain region of the FET device, partitions each source/drain region into N contact regions and calculates a set of resistances of elements and connections to the FET device. The measured dimensions of widths, lengths, and distances of layout shapes forming the FET and the connections to the FET are determined and a set of weights based on relative widths of the contact regions are computed. The total source/drain resistance of the FET device is determined by summing products of the set of resistances and the set of weights for each of a plurality of contacts in series, the summing being performed for all of the plurality of contacts in one of a source region and a drain region of the FET. A netlist is formed based on the total source resistance and total drain resistance of the FET device.

Abstract: Various embodiments include apparatuses and methods to perform noise analysis on a circuit at a selected condition (e.g., process, voltage, and temperature) using a timing model of the circuit in which the timing model is associated with the selected condition.

Abstract: A design method of on-board wiring for a designed circuit includes determining a severity as a crosstalk prevention index for a pair of wires based on a generated noise level of a damaging side wire and a permissible noise level of a damaged side wire. The pair of wires is then assigned a severity class (SC) based on the severity determined. The SC is a pre-defined value range(s) for severity classification. Based on a preset SC specific permissible value list, one or more by-design permissible values belonging to the SC is generated for a design element of the pair of wires. A layout of the pair of wires on a board is constructed based on the by-design permissible value.

Abstract: A method for designing a system on a field programmable gate array (FPGA) includes routing one or more booster wires alongside an interconnect to reduce a delay of a signal being transmitted on the interconnect. According to one aspect of the present invention, the routing of the one or more booster wires is performed in response to determining that a timing requirement of the system has not been met.

Abstract: A method and apparatus to provide a hierarchical timing model with crosstalk consideration is provided. In one embodiment, the method comprises performing block level analysis of a circuit, in one or a plurality of iterations, and storing per iteration data. The method further comprises, in one embodiment, utilizing the per iteration data in performing top level analysis of the circuit.

Abstract: Structures and methods are provided for reducing or eliminating crosstalk in devices. Based on a predetermined compensation schemes, a compensation scheme is selected that minimizes the deviation of the non-aggressed victim signal caused by one or more aggressor signals. Instances of a compensation circuit corresponding to the selected compensation scheme are placed along a victim signal line at locations defined by the compensation scheme.

Abstract: Design information including layout information of a print circuit board associated with an electronic equipment, and component information is acquired, and a verification condition associated with crosstalk noise is input. Information of signal lines which should verify influence of the crosstalk noise are extracted from the design information. Based on the verification condition, a signal line, which crosses or overlaps a signal line other than the signal line corresponding to the extracted information planerly viewed from a laminating direction of layers of the print circuit board, of the signal lines corresponding to the extracted information is detected as a victim wiring.

Abstract: A semiconductor integrated circuit design apparatus for analyzing a delay in a semiconductor integrated circuit. The semiconductor integrated circuit includes a delay analysis unit, a noise generation unit, a voltage fluctuation level analysis unit and a timing verification unit. The noise generation unit generates noise information based on a predetermined noise definition and the voltage fluctuation level analysis unit analyzes a voltage fluctuation level of the semiconductor integrated circuit when the noise is applied based on the generated noise information. Further, the timing verification unit makes the delay analysis unit analyze the static delay based on the analyzed voltage fluctuation level, to verify timing for operation of the semiconductor integrated circuit based on a result of the static delay analysis.

Abstract: An embodiment of an integrated circuit design framework comprises a user interface which automatically initializes a three-dimensional simulation tool for simulating or analyzing the characteristics of a complex metallization system. In some illustrative embodiments the user interface may additionally provide electrically simulated parameter values for an input parameter, such as the channel resistance of a power transistor, thereby enabling a simulation of a portion of interest of the metallization system without actually requiring the provision of the design data of the power transistor.

Abstract: The present disclosure relates to methods and apparatuses for generating a through-silicon via (TSV) model for RC extraction that accurately models an interposer substrate comprising one or more TSVs. In some embodiments, a method is performed by generating an interposer wafer model having a sub-circuit that models a TSV. The sub-circuit can compensate for limitations in resistive and capacitive extraction of traditional TSV models performed by EDA tools. In some embodiments, the sub-circuit is coupled to a floating common node of the model. The floating common node enables the interposer wafer model to take into consideration capacitive coupling within the interposer. The improved interposer wafer model enables accurate RC extraction of an interposer with one or more TSVs, thereby providing for an interposer wafer model that is consistent between GDS and APR flows.

Abstract: An approach is provided for pattern adjusted timing via pattern matching. Embodiments include receiving data corresponding to a problematic layout pattern associated with at least one performance characteristic and data corresponding to an integrated circuit layout design, scanning the integrated circuit layout design for the problematic layout pattern, identifying at least one portion of the integrated circuit layout design substantially matching the problematic layout pattern, and modifying a netlist associated with the integrated circuit layout design, the modification being based on the at least one performance characteristic.

Abstract: Provided is a noise analysis model and a noise analysis method that can analyze effects of substrate noise on each of elements included in a circuit to be analyzed. The noise analysis model includes first to third resistors. The first resistor serves as a substrate resistor in a semiconductor substrate between a first point set in the semiconductor substrate between a noise source and a transistor to which substrate noise from the noise source propagates through the semiconductor substrate and a second point set in the semiconductor substrate just below a back gate of the transistor. The second resistor serves as a substrate resistor in the semiconductor substrate between the second point and a fixed potential region near the transistor. The third resistor serves as a line resistor of a line connecting the fixed potential region and a power pad that supplies a ground potential.

Abstract: A method, system and computer program product are provided for implementing enhanced net routing with improved correlation of pre-buffered and post-buffered routes on a hierarchical design of an integrated circuit chip. In initial wiring steps the nets are routed, and then buffers are add along the net route based upon predetermined electrical parameters. Responsive to adding the buffers, distance based constraints are added to the nets. Then the nets that have been modified are rerouted.

Abstract: Aspects of the invention relate to techniques for extracting impedance values associated with through-silicon vias in an integrated circuit system. A function fitting process is performed to generate parameters of a representation for magneto-quasi-static dyadic vector potential Green's functions at a plurality of frequencies of interest based on integrated circuit manufacturing process information. Based on the generated parameters, a set of electric current basis functions and the layout information for a layout design of interest, matrix elements of a matrix for each frequency in the plurality of frequencies of interest may be computed. The matrix is a part of a linear system that formulates a relationship of electric current and electric potential difference in various regions associated with the through-silicon vias in the layout design. Based on the matrix, impedance values associated with the through-silicon vias are computed.

Abstract: Methods for determining induced noise on a given victim by a set of aggressor signals are presented, and for identifying the worst case aggressor switching time alignment that causes the worst case victim noise. The method removes circuit analysis pessimism related to simultaneous switching noise (SSN) in a circuit design tool by determining physically impossible combinations of victim-aggressor input/output (I/O) pins in a circuit design and culling out the impossible combinations from the list of possible victim-aggressor combinations. The method further performs a switching window SSN analysis of the circuit design with a common uncertainty removal algorithm taking into consideration the list of possible victim-aggressor combinations, and determines the maximum voltage noise induced on I/O pins of the circuit design. The results of the noise analysis are displayed to the user.

Abstract: A computer-based method and a computing device for checking signal transmission lines of a printed circuit board (PCB) layout are provided. The computing device identifies differential pairs in a currently run PCB layout according to an information file for the currently run PCB layout, checks whether any signal transmission line is routed between switching vias of each differential pair according to the information file for the currently run PCB layout, and displays a routing error window to display information of each misrouted signal transmission line.

Abstract: The present disclosure involves a method. The method includes decomposing a layout of a circuit into a plurality of patterns. The method includes generating a plurality of contours to represent the plurality of patterns after the patterns have been subjected to a manufacturing process. The method includes generating a plurality of polygons that approximate geometries of the contours, respectively. The method includes associating each of the polygons with a respective one of a plurality of pattern elements in a pattern library, wherein the pattern elements each include a shape that resembles the associated polygon and electrical parameters extracted from the shape. The method includes calculating electrical performance of the circuit based on the pattern elements associated with the polygons.

Abstract: Methods, systems, computer programs, etc., determine the required number of decoupling capacitors, and approximate locations for the decoupling capacitors, for a region of an integrated circuit. Switching elements of the region are entered into a simulation program running on a computerized device. Also, a power distribution model of the region is entered into the simulation program, and a power-supply voltage compression target is entered into the simulation program. These methods, systems, etc., generate an upper number of decoupling capacitors required to satisfy the compression target when all the switching elements concurrently switch. For each switching element, the methods, systems, etc.

Abstract: Method and apparatus for improving performance of noise analysis using a threshold based combination of noise estimation and simulation. The method includes classifying a circuit into one of four defined groups, determining if an input noise is small enough to skip simulation, estimating an output noise wave, scaling down a generated wave by a scaling factor depending on the circuit type, and determining if the estimated output noise is small enough to propagate or instead requires simulation.

Abstract: A method of method of manufacturing an integrated circuit. The method comprises performing an electromigration reliability rule-check for at least one of via node of an integrated circuit, including: calculating a net effective current density of the via node. Calculating the net effective current density including determining a sum of effective current densities for individual leads that are coupled to the via node. Leads configured to transfer electrons away from said via node are assigned a positive polarity of the effective current density. Leads configured to transfer electrons towards the via node are assigned a negative polarity of the effective current density.

Abstract: A exemplary aspect of the present invention is a simulation method for a semiconductor circuit that includes: a semiconductor resistor; a plurality of contacts arranged at regular intervals in a longitudinal direction and in a width direction of the semiconductor resistor on a terminal region of the semiconductor resistor; and a wiring line formed on the plurality of contacts, the simulation method including: defining a ratio of a parasitic-resistance by the semiconductor resistor between two of the contacts neighboring in the longitudinal direction to a resistance of one of the plurality of contacts as a constant k; and modeling a parasitic-resistance net by using the constant k, the parasitic-resistance net including the terminal region of the semiconductor resistor and the plurality of contacts.

Abstract: Some embodiments provide a method of providing configurable ICs to a user. The method provides the configurable IC and a set of behavioral descriptions to the user. The behavioral descriptions specify the effects of accesses to a memory by a set of memory ports given a set of parameters chosen by the user.

Abstract: An electronic circuit and method for designing an electronic circuit is provided that includes a first source element, a second source element, a first matching network, and a second matching network. The first matching network and the second matching network are designed by means of a method using the Poincaré distance, in which the second source element is designed to output a signal with a center frequency, in which the load has a load impedance, in which the second matching network has line-like series elements that carry the signal. The line-like series elements only have line impedances less than the load impedance or a sum of the electrical lengths of the line-like series elements, each of which has a line impedance greater than the load impedance, is less than one quarter of a wavelength associated with the signal.

Abstract: A process of operating a computer system to create a subcircuit model of an N/P configurable extended drain MOS transistor in which the subcircuit model includes an npn bipolar transistor and a pnp bipolar transistor which correspond to current paths through n-channel drift lanes and p-channel drift lanes during dual mode operation. A process of operating a computer system to simulate the behavior of an electronic circuit including a N/P configurable extended drain MOS transistor in which a subcircuit model of the N/P configurable extended drain MOS transistor includes an npn bipolar transistor and a pnp bipolar transistor which correspond to current paths through n-channel drift lanes and p-channel drift lanes during dual mode operation. A computer readable medium storing an electronic circuit simulation program that generates a simulation output of the behavior of an electronic circuit including a N/P configurable extended drain MOS transistor.

Abstract: A computerized method, data processing system and computer program product reduce noise for a buffered design of an electronic circuit which was already placed and routed. For all areas between a power stripe and a ground stripe (half bay) in the design, the shapes are divided in different criticality levels. The shapes are rearranged based on their criticality level such that shapes with higher criticality level are placed closer to the stripes than those with lower criticality level.

Abstract: A design support program stored in a recording medium readable by a computer includes acquiring a first analysis result including information about an area included in circuit information of a design target circuit and a second analysis result relating to a path of the circuit information, the temperature of the area being equal to or higher than a certain temperature; determining an arbitrary cell on a non-critical path from among cells arranged in the area as a target cell for decreasing the area temperature; and outputting a result of the determination.

Abstract: A method of gridded glyph geometric objects (L3GO) integrated circuit (IC) design, wherein at least one inter-level connect in a L3GO circuit design is represented as a point matrix glyph (PMG) on a L3GO grid. Each PMG connects a pair of conductors on the next adjacent (above and below) layer and includes an array (one or two dimensional) of point glyphs contained within a cage. The point glyphs may have uniform size and may be on minimum pitch. Each PMG may also include a flange on the above and below layer. A default flange insures adequate coverage of cut shapes represented by the point glyphs.

Abstract: Parasitic extraction is a useful tool for analyzing and improving timing and other characteristics of semiconductor chips. Parasitic resistance and capacitance values are determined and stored in arrays. The parasitic values are extracted for multiple corners with a single analysis of the layout. Multi-corner analysis is performed using the parasitic values thereby optimizing the timing across various temperature and process operating points.

Abstract: Predicting simultaneous switching output noise of an IC device is described. User input is obtained. The user input includes: an identification of an input/output bank of an integrated circuit die; an identification of a device package substrate to which the integrated circuit die is to be attached; and an identification of input/output interface to be used by the input/output bank. A noise factor and an impedance are selected responsive to the user input. The noise factor is multiplied with the impedance to provide a result. The result, which is output, is a prediction of the simultaneous switching output noise of the integrated circuit device.

Abstract: Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation.

Abstract: A computing device reads a printed circuit board (PCB) layout file from a storage device. The PCB layout file includes arrangement information of signal lines, power lines, and power through-holes arranged on a PCB. Furthermore, the computing device sets a reference distance between a selected power through-hole and a neighboring signal line, and searches for one or more line segments of one or more signal lines where the a distance between each of the one or more line segment and the selected power through-hole is less than the reference distance.

Abstract: A method, a system and a computer program product for reducing coupling noise in low loss on-module wires used for connecting module components in electrical circuits/devices. During the design stage, an Enhanced Crosstalk Reduction (ECR) utility identifies interconnect wires as driven/aggressor traces or receiver traces. The ECR utility substantially avoids forward crosstalk in a victim trace by specially arranging driver traces adjacent to the receiver victim trace in order to provide a lower level and saturated level of backward crosstalk. In particular, the ECR utility provided a configuration of wire/trace layers based on one or more of: (a) the crosstalk impact of a trace when positioned in a particular location; (b) the crosstalk impact of the trace upon remaining components based on placement in the particular location; and (c) system component specifications.

Abstract: A layout method of a semiconductor integrated circuit includes five steps. The first step is of extracting a wiring crowding place where wiring lines are crowded as compared with a predetermined condition, after carrying out a routing in a region where a placement of circuit elements is carried out. The second step is of generating routing prohibition regions where a routing is prohibited in an area including the wiring crowding place. The third step is of carrying out a routing by bypassing the routing prohibition regions. The fourth step is of deleting the routing prohibition regions. The fifth step is of carrying out a re-routing. The generating step includes: calculating a size and an interval of the routing prohibition regions based on a rate for generating a routing prohibition region in the area in each wiring layer, and generating the routing prohibition regions in the area on the basis of the calculating result.

Abstract: A method for determining simultaneous switching noise for multiple Input/Output (I/O) standards is provided by calculating incremental noise for the multiple I/O standards by considering a cumulative amount of noise contributed by previously assigned pins. In another embodiment, the number of pins being placed is considered rather than the cumulative amount of noise. When considering the cumulative amount of noise the I/O noise from corresponding I/O standards are characterized and a greater contributor is identified so that the I/O standard associated with the greater contributor can be assigned.

Abstract: A method of simulating an electrostatic discharge (ESD) circuit layout is disclosed. A netlist of an electronic circuit is pre-simulated. A circuit layout, including an ESD circuit layout, is accordingly generated. Parasitic is extracted according to the generated circuit layout. The ESD circuit layout is post-simulated according to an ESD waveform and a result of the parasitic extraction.