Abstract: A method, non-transitory computer readable medium, and apparatus for performing single event upset detection and correction are disclosed. For example, the method comprises: setting, by a processor, at least one starting address for each of a plurality of rows of a design for an integrated circuit, setting, by the processor, at least one ending address for each of the plurality of rows of the design, and performing, by the processor, the single event upset detection and correction scan in parallel, from the at least one starting address for each of the plurality of rows to the at least one ending address for each of the plurality of rows.

Abstract: A system and method are provided for automatically converting a hardware abstraction language representation of a single-channel hardware module into a hardware abstraction language representation of a multi-channel module. Initially, a hardware abstraction language representation of a single channel hardware module is provided having an input port, output port, and a register. The method defines a number of channels and establishes a context switching memory. Commands are created for intercepting register communications. Commands are also created for storing the intercepted communications in a context switching memory, cross-referenced to channel. The module is operated using the created commands and stored communications from the context switching memory.

Abstract: An imaging solution that uses a small, adaptable, real-time, scalable, image-processing (SMARTS IP) chip configured to function like any one of a wide range of specialized FPA imaging devices, and a method for configuring and implementing same is provided. Configuration for a wide range of applications and implementations, including ones with or without IDCA assemblies or other types of dewar/cooler structures, is disclosed. A wide range of output data formats, including all SDI-compatible image data formats, may be accomplished. Frame stacking and variable effective resolution and charge well depth levels may be accomplished in output image data based on on-chip image processing techniques. On-chip image processing algorithms may include XR™, DRC, NUC, and other similar or related techniques. Image data output compression through on-chip processing is also disclosed.

Abstract: A method and apparatus for generating user clocks in a prototyping system is disclosed. A prototyping system has a plurality of programmable logic chips that are each programmed with one or more partition of a prototyped circuit design. For a circuit design having multiple user clock signals, each partition uses some or all of the user clocks. A reference clock signal is externally generated, and received by each of the programmable logic chips. Using a phase-locked loop, a plurality of in-phase higher frequency clock signals are generated from the reference clock signal. The user clock signals are then generated from these higher frequency signals using a plurality of divider circuits. Reset circuitry implemented in one of the programmable logic chips transmits a common reset signal to the divider circuits, maintaining the phase relationship of each user clock across the programmable logic chips.

Abstract: Clock distribution circuitry for a structured ASIC device includes a deterministic portion and configurable portions. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal to a plurality of predetermined locations on the device. From each predetermined location, an associated configurable portion of the clock distribution circuitry distributes the clock signal to any clock utilization circuitry needing that clock signal in a predetermined area of the structured ASIC that is served from that predetermined location.

Abstract: The invention relates to methods and devices to define and control the design of a configurable chip module, instrument or systems, for example, for measurement, control and communication systems or any portion thereof. The module may include one or more chip elements. This can be achieved using, for example, a Graphical User interface (GUI), that transforms selections made by the user to a hardware and/or software configuration for the system in a process transparent to the user. This enables implementation of a plurality of devices and larger subsystems on a chip or chip module without specific semiconductor design knowledge from the user. This transformation process is thus accomplished transparently to the user, who operates the GUI to define the measurement or action which needs to be performed thereby resulting in an automatic combination of hardware and/or software elements available to create a specific configuration.

Abstract: Methods and apparatus are described for efficiently performing EDA processing to arrive at a hardware definition for a varying fraction of a large circuit design. EDA processing is conducted targeting a pseudo hardware device with sufficient capacity to embody circuitry for the varying fraction, but substantially less than the true hardware target. The novel methods and apparatus may be beneficially employed to produce reconfiguration information for circuits that include programmable logic, for example.

Abstract: An embodiment includes an integrated circuit (IC) for using direct memory access (DMA) to initialize a programmable logic device (PLD), the IC operably coupled to the PLD. The IC includes an input/output (I/O) interface and a PLD interface. The I/O interface converts a signal format between the IC and the PLD. The PLD interface includes a configuration and status register, a data buffer, and pacing logic. The configuration and status register is adapted to manipulate a control line of the PLD to configure the PLD in a programming mode via the I/O interface. The data buffer temporarily holds PLD programming data received from a DMA control at a DMA speed. The pacing logic controls the speed of transmitting the PLD programming data to a programming port on the PLD via the I/O interface at a PLD programming speed.

Abstract: A reconfigurable logic block has a first circuit that configures an arithmetic circuit and a second circuit that configures a circuit outside of the arithmetic circuit. A plurality of different circuits are configured by changing the settings of predetermined signals in the first and second circuits.

Abstract: A programmable logic device includes logic blocks such as a logic array blocks (LAB) that can be configured as a random access memory (RAM) or as a lookup table (LUT). A mode flag is provided to indicate the mode of operation of configuration logic such as a configuration RAM (CRAM) used during partial reconfiguration of a logic block. An enable read flag is provided to indicate if values stored in the configuration logic are to be read out or a known state is to be read out during a data verification process. Thus, exclusion and inclusion of portions of a region of configuration logic from data verification and correction processes allow a region of configuration logic to store both a design state and a user defined state. Moreover, the region of configuration logic may be dynamically reconfigured from one state to another without causing verification errors.

Abstract: In one embodiment, a method and apparatus for analyzing a design of an integrated circuit (IC) are disclosed. For example, the method parses a netlist file of the IC where a module of the IC is parsed into a plurality of sub-modules in accordance with a hierarchical structure. The method traces through a connectivity of the plurality of sub-modules, and tabulates data associated with the connectivity with a fault cost associated with a structure of the IC.

Abstract: Approaches for dynamically reconfiguring a programmable integrated circuit (IC) are disclosed. In response to user input to a reconfiguration controller while a circuit is operating in programmable resources of the programmable IC, a replacement module and a module to be replaced in the circuit are selected. A process determines whether or not interfaces of the replacement module are compatible with interfaces of the circuit to the module to be replaced. In response to the interfaces of the replacement module and the interfaces of the circuit to the module to be replaced being compatible, the programmable IC is partially reconfigured with a realization of the replacement module in place of a realization of the module to be replaced.

Abstract: A distributable and serializable finite state machine and methods for using the distributable and serializable finite state machine are provided wherein finite state machine instance can be location-shifted, time-shifted or location-shift and time-shifted, for example by serializing and deserializing each instance. Each instance can be located-shifted between agents, and a persistent memory storage location is provided to facilitate both location-shifting and time-shifting. Finite state machine instances and the actions that make up each instance can be run in a distributed fashion among a plurality of agents.

Abstract: A logic chip has a plurality of individually-addressable resource blocks, each comprising logic circuitry. The logic chip also has a bus comprising a plurality of bus information lines. A first of the resource blocks has a coupling between a first strict sub-set of the bus information lines and the logic circuitry of the first resource block. A second of the resource blocks, which is adjacent to the first resource block, has a coupling between a second strict sub-set of the bus information lines and the logic circuitry of the second resource blocks. The first and second sub-sets have different bus lines.

Abstract: Embodiments of an electronic design automation system are generally described herein. In some embodiments, glitch-sensitive nodes in an integrated circuit design are identified. For each glitch-sensitive node, a circuit fanin cone is analyzed to look for circuit structures that can produce glitches. The integrated circuit design can be simulated and modified if the simulation indicates that a glitch would occur in the integrated circuit design.

Abstract: In one embodiment, a method for propagating design constraints between a module and a module instance in a circuit design is provided. A port of the module and a port/pin of the circuit design are determined, between which constraints are to be propagated. The determination of the port/pin includes determining whether or not pin of the module instance corresponding to the port is directly connected to a top-level port of the circuit design. In response to determining that the pin is directly connected to a top-level port, the top-level port is selected as the port/pin. In response to determining that the pin is not directly connected to the top-level port, the pin is selected as the port/pin. Design constraints are propagated between the port and the selected port/pin. The propagated design constraints are stored in a storage device.

Abstract: A die expansion bus efficiently couples a supplemental portion of a processing system to an original portion of the processing system on a die. The die expansion bus couples bus subsystems of the supplemental portion of the processing system to the bus subsystems of the original portion of the processing system. The original portion of the processing system is arranged to control the data resources of the supplemental portion of the processing system by accessing memory mapped control registers associated with the bus subsystems of the supplemental portion of the processing system.

Abstract: A time-multiplexed field programmable gate array (TM-FPGA) includes programmable logic circuitry, programmable interconnect circuitry, and a plurality of context registers. A user's circuit can be mapped to the programmable logic circuitry, the programmable interconnect circuitry, and the plurality of context registers without the user's intervention in mapping the design.

Abstract: A reconfigurable circuit design method includes an input step of inputting design data of a default configuration of a reconfigurable circuit including a plurality of processor elements which perform processing and a first generation step of generating design data obtained by modifying at least one of the processor elements in the reconfigurable circuit with the default configuration.

Abstract: A processing device programming system automatically provides a user interface comprising a selectable list of one or more processing devices based on a system level solution, automatically generates an embedded programmable system solution from the system level solution and a processing device selected from the selectable list of one or more processing devices, and automatically programs the processing device according to the embedded programmable system solution.

Abstract: A microfluidic device is programmable so that a single microarchitecture design can run many assays. Specifically, the programmable microfluidic device includes an execution method to facilitate translating from a programming language to a set of requests that are specified for the device. In addition, the microfluidic device includes a contamination mitigation method that includes a conflict list to mitigate contamination effects within the microfluidic device.

Abstract: A behavioral synthesis device include a profile unit that implements an electronic circuit at a reconfigurable hardware based on a first register transfer level description generated by a behavioral synthesis unit, actuates the implemented electronic circuit, and causes the electric circuit to output profile information from the actuated electronic circuit; and an optimizer that generates optimization information for optimizing a behavioral synthesis carried out by the behavioral synthesis unit based on the profile information that the profile unit causes the electric circuit to output, and outputs the generated optimization information to the behavioral synthesis unit, wherein the behavioral synthesis unit acquires a first behavioral level description, and subjects the acquired first behavioral level description to behavioral synthesis and generates the second register transfer level description based on the optimization information outputted by the optimizer.

Abstract: An improved approach is described for analyzing and estimating products having arrays of uncommitted logic, and matching these products to electronic designs. The approach can be applied to any type of product that include arrays of uncommitted logic, such as gate arrays and field programmable gate arrays. An approach is described for performing memory mapping in the context of selecting an electronic product having an array of uncommitted logic.

Abstract: A method and apparatus for camouflaging an application specific integrated circuit (ASIC), wherein the ASIC comprises a plurality of interconnected functional logic is disclosed. The method adds functionally inert elements to the logical description or provides alternative definitions of standard logical cells to make it difficult for reverse engineering programs to be used to discover the circuit's function. Additionally, post processing may be performed on GDS layers to provide a realistic fill of the empty space so as to resemble structural elements found in a functional circuit.

Abstract: Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.

Abstract: An electric design automation (EDA) tool for generating a design of a system on a field programmable gate array. (FPGA) includes a graphical user interface to create a block based schematic. The EDA tool includes a library that includes a parameterizable filter block selectable by a designer to include in the block based schematic to represent a component in the design that filters data. The EDA tool includes a design adjustment unit to automatically modify previously programmed and selected components and wires in the block based schematic without input from the designer upon determining a change made to the parameterizable filter block by the designer.

Abstract: A system and method are provided for configuring a programmable integrated circuit including a number of function blocks. In one embodiment, the system includes a programmable integrated circuit including a number of function blocks, and a host computing device to configure the number of function blocks to perform a number of functions. The host computing device utilizes a graphical user interface to provide specification of configuration parameters of the function blocks, and the graphical user interface updates a given configuration parameter if a value of the given configuration parameter is affected by a value specified for another configuration parameter. Other embodiments are also provided.

Abstract: A semiconductor die includes at least one flexible interface block. The flexible interface block includes at least one interconnect, and at least one buffer coupled to the at least one interconnect. The flexible interface block further includes a routing interface coupled to circuitry integrated in the semiconductor die, and a controller coupled to provide communication between the routing interface and the at least one buffer.

Abstract: In an embodiment, a methodology for automating the generation of a programmable logic device implementation of at least a portion of an integrated circuit is contemplated. The methodology may operate on one or more hardware description language (HDL) files which describe the integrated circuit as an input. Additionally, one or more user-generated control files may be input to the methodology. The methodology may process the one or more HDL files, generating a bitstream to program one or more programmable logic devices to implement the described design. The methodology may include automated modification of the HDL files to prepare them for programmable logic device implementation, automated pad ring generation, automated pin multiplexing, daughter card definition, partitioning, etc.

Abstract: A method of specifying system level constraints for connecting an interface of an electronic device between first and second fabrics includes specifying one or more first condition relating to a placement of the interface, specifying one or more second condition relating to a connection of a net in the interface between the first and second fabrics, generating one or more first equation expressing the first condition as a function of the location of the connectors, generating one or more second equation expressing the second condition as a function of the location of connectors, generating one or more third equation expressing an optimality criterion for the interface, and outputting the one or more first equation, the one or more second equation and the one or more third equation to a data file in a computer readable format.

Abstract: A method of generating a hardware design for a pipelined parallel stream processor, by defining a hardware processing operation; specifying at least one propagation rule; defining a graph representing the processing operation in the time domain, comprising at least one data path to be implemented as a hardware design and a plurality of parallel branches; each data path having: at least one data path input, output, and discrete object corresponding to a hardware element; each discrete object comprises an input for receiving an input variable, an operator for executing a function on said input variable, and an output variable; optimizing each output from each discrete object in dependence upon the propagation rule to produce an optimised graph; and utilizing the optimised graph to define an optimised hardware design for implementation in said pipelined parallel stream processor.

Abstract: One or more hardware description language (HDL) files describe a plurality of hierarchically arranged design entities defining a digital design to be simulated and a plurality of configuration entities not belonging to the digital design that logically control settings of a plurality of configuration latches in the digital design. The HDL file(s) are compiled to obtain a simulation executable model of the digital design and an associated configuration database. The compiling includes parsing a configuration statement that specifies an association between an instance of a configuration entity and a specified configuration latch, determining whether or not the specified configuration latch is described in the HDL file(s), and if not, creating an indication in the configuration database that the instance of the configuration latch had a specified association to a configuration latch to which it failed to bind.

Abstract: A method of implementing a circuit design within a programmable integrated circuit (IC) can include identifying an implementation directive embedded within a register transfer level (RTL) description of the circuit design and determining components of a sub-circuit of the circuit design, wherein the sub-circuit is specified by a portion of the RTL description associated with the implementation directive. The sub-circuit can be placed for the programmable IC and routed for the programmable IC according to the implementation directive. A programmatic description of the sub-circuit specifying placement and routing information can be output.

Abstract: A reconfigurable device includes an arrangement of a plurality of cells and routing resources for transmitting signals between the cells. The plurality of cells comprises carry-select reuse cells, each of the carry-select reuse cells configured to provide for performing non-arithmetic operations using a reuse arithmetic carry chain interconnecting adjacent cells.

Abstract: System and method for developing an ASIC. A software program may be stored which includes program instructions which implement a function. The software program may be executed on a processing system at a desired system speed and may be validated based on the execution. A first hardware description of at least a portion of the processing system may be stored and may specify implementation of at least a portion of the processing system. A second hardware description may be generated that corresponds to a first portion of the first hardware description. The second hardware description may specify a dedicated hardware implementation of a first portion of the software program executing on the processing system. Generation of the second hardware description may be performed one or more times to fully specify the ASIC. An ASIC may be created which implements the function of the software program.

Abstract: Methods and apparatus are provided for efficiently implementing an application specific processor. An application specific processor includes a data path and a control path. A control path is implemented using processor components to increase resource efficiency. Both the data path and the control path can be implemented using function units that are selected, parameterized, and interconnected. A tool uses the selected function units and interconnection information to provide data for implementing the application specific processor. Missing function units or interconnections can be identified and corrected.

Abstract: Techniques for generating an integrated circuit (IC) design configuration file are provided. The techniques include compiling a design file to generate a compiled IC design. The design file may include multiple constraints that are associated with the design. Status reports are generated based on the compiled IC design and the associated constraints. At least a portion of the generated status reports is encoded. A configuration that includes the encoded portion of the status reports is generated based on the compiled IC design is generated.

Abstract: An electronic automation system performs register retiming on a logic design, which may be a logic design for a programmable logic integrated circuit. Register retiming is a moving or rearranging of registers across combinatorial logic in a design in order to improve a maximum operating frequency or fmax. In one implementation, the system includes machine-readable code, which may be stored on a computer-readable medium such as a disk, executing on a computer. The system balances timing in order to trade off delays between critical and noncritical paths. Register retiming may make changes to a design at a gate level.

Abstract: Provided is a method of managing a configuration memory of reconfigurable hardware which can reconfigure hardware according to hardware configuration information. The method includes: determining at least one slot capable of currently storing the hardware configuration information on the basis of the states of a plurality of slots of the configuration memory; and storing hardware configuration information, which is stored in an external memory, in the determined at least one slot capable of currently storing the hardware configuration information. Accordingly, memory utilization can be improved even in dynamic environment such as data dependent control flow or multi-tasking.

Abstract: Method and apparatus for generating an implementation of a program language circuit description for a programmable logic device (PLD) is described. In one example, the program language circuit description is analyzed to identify constructs indicative of dynamic function re-assignment. A hardware description of the program language circuit description is generated. The hardware description includes a plurality of implementations responsive to the identified constructs. Physical implementation data is generated from the hardware description. The physical implementation includes a plurality of partial configurations for the PLD based on the respective plurality of implementations in the hardware description.

Abstract: An improved approach is described for analyzing and estimating products having arrays of uncommitted logic, and matching these products to electronic designs. The approach can be applied to any type of product that include arrays of uncommitted logic, such as gate arrays and field programmable gate arrays.

Abstract: An apparatus and method may be used for compiling a hardware logic design into data-driven logic programs to be executed on a data-driven chip. The apparatus may include storage with a library for defining a net-list synthesized by a synthesis tool. The apparatus may also include a data-driven logic verification chip comprising a plurality of logic processors. The apparatus may further include a code generator for adopting heuristics to convert the net-list into data driven logic programs and for allocating hardware resources to balance computing and storage loads across the plurality of logic processors of the verification chip.

Abstract: The present invention relates to a flexible analog/digital configuration, preferably on a chip, that can be used for receiving various inputs, processing those inputs, and displaying/communicating the results and/or providing a response thereto. More particularly, the present invention can measure multiple parameters and, when properly programmed, can easily organize the data from multiple sensors or other analog or digital sources. It can present or display different, or similar, pages for setting up each measurement (or each measured parameter) (e.g., by sensor, class of sensors, etc.) to enable an easy to use approach for individuals without needing to know the specifics as to many parameters. This user-friendly approach can be performed using a configurable chip module system.

Abstract: In an embodiment, a method to automatically generate a pad ring for a programmable logic device implementation of an integrated circuit is contemplated. The pad ring that will be used in the integrated circuit itself may include pad logic (e.g. to support boundary scan and other forms of testing), custom driver/receiver circuitry, etc. The pad ring in the programmable logic device, on the other hand, may be predetermined as part of the production of the programmable logic device. The generation may include removing the pad logic and other pad-related circuitry from one or more design files that represent the integrated circuit, as well as mapping the input, output, and input/output signals of the integrated circuit to the available programmable logic device pads.

Abstract: A design information generating equipment is provided. A control component of the design information generating equipment, when a basic function of the plurality of functions constitutes a requested function, and design information that corresponds to the basic function is stored in a second memory area, uses the stored design information, and, when the design information that corresponds to the basic function of the plurality of functions is not stored in the second memory area, uses a source program corresponding to the basic function of the plurality of functions stored in a first memory area, and performs control so as to generate design information corresponding to the basic function of the plurality of functions and stores the generated design information in the second memory area, and, using the generated design information, reconfigures a design configured to execute the requested function, and executes the requested function with the reconfigurable design information.

Abstract: An embodiment of a method for enabling a high level modeling system for implementing a circuit design in an integrated circuit device includes: receiving a high-level characterization of the circuit design; receiving a portable location constraint associated with elements of the circuit design; and generating, by a computer, a low-level characterization of the circuit design based upon the high-level characterization and the portable location constraint.

Abstract: A method is provided for preparing a plurality of systems that include respective programmable integrated circuits (ICs) of the same type. A plurality of circuit designs is partitioned into a base design and respective supplemental designs. The base design includes a set of input/output pins utilized by any of the plurality of circuit designs. A supplemental bitstream is generated for each of the supplemental designs. A first bitstream is generated for implementing the base circuit design, a communication module, and a reconfiguration module in a first portion of programmable resources of the programmable IC. The reconfiguration module is configured to program, in response to each respective one of the supplemental bitstreams received via the communication module, a second portion of the programmable resources with the supplemental bitstream to implement a corresponding one of the plurality of circuit designs.

Abstract: Disclosed is a method of simulating partial reconfiguration of a programmable logic device (PLD). A wrapper module is incorporated into a logic description that may be implemented in a PLD. The wrapper module represents a first logic design. In response to receiving a parameter, the wrapper module changes to represent a second logic design. According to various embodiments, the logic description is a simulatable source file. The simulatable source file is a source file that is used by a simulation program to simulate partial reconfiguration of the logic design. The wrapper module of the simulatable source file receives a run-time parameter. In various embodiments, the logic description is a synthesizable source file. The synthesizable source file is a source file that is used by a synthesis tool to compile the source file into hardware. The wrapper module of the synthesizable source receives a compile-time parameter.

Abstract: The invention relates to a method and a tool for generating a parameterized configuration for a Field Programmable Gate Array from a Boolean function, the Boolean function comprising at least one parameter argument, comprising the steps generating at least one tunable logic block from the Boolean function and from at least one parameter argument, and mapping the at least one tunable logic block to the Field Programmable Gate Array. This is advantageous since a parameterized configuration can be generated faster than with conventional tools.

Abstract: Some embodiments provide an IC with configuration context switchers. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration data sets for each of the configurable circuits. The IC also includes a context switching interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets. The context switcher includes one or more stages for re-timing the data coming from the configuration storage elements. The stages can include interconnect circuitry or storage circuitry. Some embodiments build one of the stages in the configuration data storage elements. Some embodiments encode the configuration data bits and hence utilize a decoder in the context switcher to decode the encoded configuration data.