Abstract: A mechanism is provided for performing a detailed routing of a net joining ports in an integrated circuit. Extended port regions are created for the ports of the net of the integrated circuit, the extended port regions being shaped in such a way as to guarantee routing access to the ports. A wire corresponding to the net is then placed and the extended port regions of the ports are trimmed, thus identifying essential port regions required for connecting the wire to the ports and dispensable port regions not required for connecting the wire to the ports. The wiring resources are then updated by releasing the dispensable port regions so that the dispensable port regions no longer constitute parts of the ports.

Abstract: Embodiments that route 1×N building blocks using higher-level wiring information for a 1×N compiler are disclosed. Some embodiments comprise determining higher-level coordinates for a blockage of a 1×N building block, determining intra-1×N coordinates for a shape of the blockage via the higher-level coordinates, and creating routes of intra-1×N wires of the 1×N building block that avoid the intra-1×N coordinates. Further embodiments comprise an apparatus having a higher-level wiring examiner to examine higher-level wiring of an area near a 1×N building block of a physical design representation. The apparatus may also have a blockage determiner to determine a blockage that affects intra-1×N wiring for the 1×N building block and a coordinate calculator to calculate coordinates of a shape of the blockage, wherein the calculated coordinates may enable a routing tool to avoid the shape when creating intra-1×N wiring for the 1×N building block.

Abstract: The invention relates to a method and a system for routing electric circuits in integrated circuit chip design. Specifically, the invention encompasses the steps of performing a congestion analysis for a given routed placement of cells containing said electric circuits on a chip; defining a critical area on said chip based on congestion information; analyzing actual wiring quality within said critical area; comparing an actual wiring quality of said critical area with a reference wiring quality of said critical area; and rerouting said critical area based on a comparison between the actual wiring quality and the reference wiring quality.

Abstract: A semiconductor apparatus and a design method for the semiconductor apparatus allow debugging or repairs by using a spare cell. The semiconductor apparatus includes a plurality of metal layers. At least one repair block performs a predetermined function. A spare block is capable of substituting for a function of the repair block. And at least one of the plurality of metal layers is predetermined to be a repair layer for error revision. At least one pin of the repair block is connected to the repair layer through a first pin extension, and at least one pin of the spare block is capable of extending to the repair layer. When the repair block is to be repaired, the pin extension of the repair layer and the repair block is disconnected, and at least one pin of the spare block is connected to the repair layer through a second pin extension.

Abstract: A method to reduce the problem complexity maintains a relatively high quality port assignment by abstracting local connections in the macro when performing the port assignment. This is done for netlength, congestion as well as timing. The internal netlist of the macro is abstracted in such a way that the optimization of the external interconnect can be done in an efficient manner. Three levels of abstractions are described. A first level optimizes the top level interconnect, a second level optimizes the top level and macro interconnects, while a third level optimizes the top level timing.

Abstract: A method for minimizing coupling capacitance between wires in a bus comprising shifting by rearranging the order of said wires in said bus so that, aside from said first and last wires in said arrangement, the coupling capacitance across said bus is uniform and minimized relative to the original arrangement. Alternatively, a method for minimizing coupling capacitance between wires in a bus comprising shifting by rearranging the order of said wires in said bus so that, aside from said first and last wires in said arrangement, one of said wires incurs the smallest possible amount of coupling capacitance and then the coupling capacitance across the rest of said wires in said bus gets progressively worse relative to the original arrangement.

Abstract: A method for configuring an integrated circuit including configuring a plurality cells to form a cell library, wherein configuring each cell includes defining intracell wiring in at least one layer positioned above a substrate, the intracell wiring connecting to structures below the at least one layer and forming one or more terminals, and defining one or more candidate wires for at least one terminal to use as pre-defined intercell wiring for connection to the at least one terminal. The method further includes arranging selected cells from the cell library to form a desired layout of an integrated circuit, and routing intercell wiring so as to interconnect the selected cells to achieve a desired function of the integrated circuit including using only selected candidate wires for intercell wiring within borders of each of the selected cells.

Abstract: Method and apparatus for approximating the average critical area of a layout or layout region, involving summing, over all the object segments of interest, respective critical area contribution values that are dependent upon particular layout parameters of the objects, each of the contribution values being representative of a plurality of defect sizes, and being defined such that for each defect size in the plurality of defect sizes, and for a particular defect type, the contribution values collectively count all critical areas arising due to the object segments of interest only once.

Abstract: A method for indentifying instances of a smaller circuit in a larger circuit is disclosed. Both the smaller circuit and the larger circuit have a plurality of vertices. A vertex is one of a device or a net. The device, such a transistor, includes a Gate, a Drain, and a Source. The net is a wired connection between devices. In this method, one initial unique label is assigned to each of the plurality of vertices, each of a plurality of connection-types, power connection, and ground connection. A zero label is assigned to each of an input/output ports and a same initial unique label is assigned to same types of circuit components. Then each net is relabeled using labels of neighboring vertices. The neighboring vertices of a vertex are vertices that are directly connected to the vertex. Then, each device in the plurality of vertices is relabeled using labels of neighboring vertices excluding a label of a vertex that is connected to the Gate of the each device.

Abstract: A resistor device structure and method of manufacture therefore, wherein the resistor device structure invention includes a plurality of alternating conductive film and insulative film layers, at least two of the conductive film layers being electrically connected in parallel to provide for high current flow through the resistor device at high frequencies with increased temperature and mechanical stability. The alternating conductive film and insulative film layers may be of a planar or non-planar geometric spatial orientation. The alternating conductive film and insulative film layers may include lateral and vertical portions designed to enable a uniform current density flow within the structure itself through a self-ballasting effect within the physical resistor.

Abstract: A method, system, and related computer program products for computer simulation of a photolithographic process is described. In one embodiment, a method for designing an integrated circuit is provided. The geometrical design intent and process condition values are received for at least one process variation associated with a photolithographic process to be used in fabricating the integrated circuit. The photolithographic process is simulated at the process condition values using one or more models characterizing the photolithographic process and the geometrical design intent to generate simulation results.

Abstract: A method and system that converges on a global solution to a PCB routing problem using iterations of topology-based routing is described. In some embodiments, the geometric design space is abstracted into a topological graph representing the routing problem. Then, each net is allowed to find its optimal solution path independent of the solution paths for all other nets. The electrical and physical constraints of the system are initially ignored or greatly relaxed. Over each design iteration, the constraints are tightened until a complete, global, topological solution is found. Once a topological solution is found, it is converted into a geometric solution. In the event that no geometric solution exists for that topological solution, then the iteration process is resumed taking into consideration this additional information. The result is the ability to quickly autoroute highly-constrained PCB designs with minimal operator input.

Abstract: A method for simplifying metal shapes in an integrated circuit including receiving an incoming wire layout for at least one metal layer of an integrated circuit, the incoming wire layout for the at least one layer including a plurality of wires running in a preferred direction and a plurality of vias connected thereto.

Abstract: Methods of placing and routing a logic design are provided. The logic design includes logic elements and nets connecting the logic elements. A first placement and a partial routing of the logic elements and the nets of the logic design are generated. The partial routing leaves some of the nets unsuccessfully routed. An initial area associated with each of the logic elements is expanded for the logic elements that are connected to the unsuccessfully routed nets. Positions for the logic elements are determined from a linear system that reduces a total length of the nets connecting the logic elements and inhibits overlap of the areas of the logic elements. A second placement of the logic elements is generated from the positions. A complete routing of all of the nets is generated for the second placement. A specification of the second placement and the complete routing is output.

Abstract: A method and system for pattern-driven routing are disclosed. Embodiments of pattern-driven routing are disclosed for creating a representation for at least a portion of an initial routing solution, comparing the representation for at least the portion of the initial routing solution with a pattern, and determining whether the initial routing solution has lithographic issues based on the comparison.

Abstract: A method for preprocessing tie net routing data organizes the data into a plurality of tie nets each based on an optimal connection path between a pin or set of pins and the power grid. The router then routs the data embodying the thusly-simplified plurality of tie nets. Once the routing is complete, post processor takes the routed design and returns it to its original net list state while keeping the routing solution.

Abstract: Standard cell libraries and methods of designing semiconductor integrated circuits are provided. At least one of delay-adjusting cell data and load-capacitor cell data is stored in the cell library for a specified type standard cell in addition to the standard cell data. The specified type standard cell may be utilized as a delay-adjusting cell or a load-capacitor cell. Accordingly, precise adjustment of delay times during designing a semiconductor integrated circuit is enabled without requiring registering a new standard cell in the cell library. Semiconductor integrated circuits are also provided that are configured to allow precise adjustment of delay times in the semiconductor integrated circuits.

Abstract: An automatic system for providing printed circuit board (PCB) layout of a PCB includes an input device, a data processing device, and a storage device. The data processing device includes an invoking module, a calculating module, and a determining module. The invoking module is to read a name and a thickness of each layer of the PCB from the storage device. The calculating module is to calculate an actual length of a via stub of each layer according to the name and thickness of each layer, and calculate an ideal length of the via stub of the PCB according to input information from the input device, and a preset formula. The determining module is to compare the ideal length and the actual length of the via stub of each layer to determine whether the layer can be used as a high-speed signal layout layer or not.

Abstract: One embodiment of the present invention provides a system that routes a set of pairs of points during the design of an integrated circuit (IC) chip. The system comprises a routing engine which is configured to search for a path to connect a current pair of points in the set of pairs of points, wherein the path comprises a set of rectangles and vertices. The routing engine uses a routing database, which keeps track of previously routed nets that can obstruct the routing of the current pair of points. The system further comprises a satisfiability (SAT) solver which is capable of solving a set of constraints, wherein the set of constraints are associated with the routability of the set of pairs of points. The SAT solver additionally comprises a SAT database which maintains the set of constraints and a current partial solution to the set of constraints. The SAT database is used to update the routing database if the current partial solution changes.

Abstract: One embodiment of the present invention provides a system that routes connections in an integrated circuit (IC) chip design. The system includes a representation mechanism which is configured to represent routing resources in the IC chip design as a 3-dimensional (3D) grid. This 3D grid further includes: static grid lines which do not change while the system routes the connections; and dynamic grid lines which are created for routing a connection that includes pins which are not located on a static grid line. Note that the dynamic grid lines can be removed after the connection is routed. The system also includes a search engine which is configured to search for a path in the 3D grid between a first set of vertices and a second set of vertices.

Abstract: Some embodiments provide techniques and systems for routing nets in a circuit design in parallel. During operation, the system can receive a first set of partitions for a circuit design, wherein each partition in the first set of partitions extends across the circuit design along a first direction. Next, the system can perform, in parallel, track assignment in the first direction on non-overlapping partitions in the first set of partitions. The system can then receive a second set of partitions for the circuit design, wherein each partition in the second set of partitions extends across the circuit design along a second direction which is different from the first direction. Next, the system can perform, in parallel, track assignment in the second direction on non-overlapping partitions in the second set of partitions. In some embodiments, each track assignment process being performed in parallel performs track assignment on a different net.

Abstract: Some embodiments provide techniques and systems for routing nets in a circuit design in parallel. During operation, the system can receive a set of partitions for a circuit design, wherein each partition has zero or more overlapping partitions along four directions, e.g., up, down, left, and right. Next, the system can perform, in parallel, detailed routing on non-overlapping partitions in the set of partitions, wherein detailed routing is performed on a partition after detailed routing is completed on adjacent or overlapping partitions that located along two perpendicular directions. In some embodiments, each detailed routing thread that is executing in parallel performs detailed routing on a different net.

Abstract: Some embodiments provide a system for generating a centerline connectivity representation for a set of routing shapes. During operation, the system can represent the set of routing shapes using a set of centerlines with endcap extensions. Note that an intersection between two centerlines represents an electrical connection between the two routing shapes associated with the two centerlines. Next, the system can detect two routing shapes which overlap, but whose centerlines do not intersect. The system can then create a virtual shape whose centerline intersects with the centerlines of the two routing shapes. In some embodiments, the system can modify a dimension of at least one of the two routing shapes. Next, the system can create a new routing shape which overlaps with the two routing shapes, and create virtual shapes which connect the centerline of the new shape with the centerlines of the two routing shapes.

Abstract: Some embodiments provide a system for generating a memory-efficient representation of a sequence of electrically connected routing shapes. The memory-efficient representation represents the sequence of electrically connected routing shapes using a sequence of points, such that two consecutive points represent a routing shape. At least some of the points can be represented using a compact representation, thereby reducing the memory required for storing the sequence of points. A full representation specifies a point's location using the point's two-dimensional coordinates, and a compact representation specifies a point's location using one of the point's two-dimensional coordinates and an orientation indicator which indicates the routing shape's orientation. The missing coordinate in a compact representation can be determined from the preceding points. The system can represent a via that joins two routing shapes by assigning different metal layers to the points associated with the two routing shapes.

Abstract: A design support program executed by a computer includes operations of: locating at least one via hole for coupling target wiring in a first layer in circuit information to wiring in a second layer being different form the first layer; calculating an area of the target wiring based on a length and a width of the target wiring; setting a division condition based on the area and a number of the via hole; dividing the target wiring into divided wirings at a position other than a position where the via hole is provided based on the division condition; generating connection information indicating a connection relationship between the divided wirings and limitation information for coupling the divided wirings via a wiring in a third layer being different from the first layer; and outputting the connection information, the limitation information and circuit information obtained after dividing.

Abstract: A method and system for designing a circuit board designs wiring of the circuit board, and determines electronic rules and physical rules of the wiring design. The method and system creates a board file by designating a file name, outputs the electronic rules into the board file, and outputs the physical rules into the board file according to a preset output format. The method and system further generates a circuit diagram according to preset initial parameters, and applies the electronic rules and the physical rules to the circuit diagram according to the board file.

Abstract: State retention cells of a test circuit embedded in an electrical circuit are interconnected to form one or more scan chains. The scan chains are interconnected so that unknown states, or X-states, are shifted through the scan chains in an order other than the order in which the states were captured by the state retention cells of the scan chain. Such reordering of response states in individual scan chains may be used to align the X-states across multiple scan chains to achieve higher test compression scan register circuit testing.

Abstract: Methods, circuits and systems for converting of a non-predicated asynchronous netlist to a predicated asynchronous netlist are described. These may operate to identify one or more portions of an asynchronous netlist corresponding to a partially utilized portion of an asynchronous circuit. The asynchronous netlist may be modified to control the partially utilized portion. Additional methods, circuits, and systems are disclosed.

Abstract: Methods and apparatuses for routing traces in a layout design, such as for example a layout design for an integrated circuit, are disclosed. In various implementations, a group of netlines within a layout design and a freeform sketch are identified. Subsequently, the netlines are routed as traces according to the freeform sketch. More particularly, the geometry of the traces is determined by approximating the geometry of the freeform sketch. Various implementations of the invention provide for the netlines to be routed by an automated trace routing engine. With further implementations of the invention, ball grid array escapes and trace fanouts are additionally routed. For example, ball grid array escapes may be routed prior to netlines being routed according to the freeform sketch. In further implementations of the invention, the freeform sketch is deleted after the traces have been routed.

Abstract: Some embodiments of the present invention provide a system that routes nets over circuit blocks in a hierarchical circuit design. During operation, the system can receive a set of circuit blocks. At least some terminals of the circuit blocks may be desired to be electrically linked together using a net which is expected to be routed over one or more circuit blocks. The system may divide an area associated with a block (e.g., an area in a metal layer which is situated above the block) into a set of tiles. Next, the system may assign costs to at least some of the tiles in the set of tiles. The system can then use the costs during routing. Note that using the costs of the tiles during routing makes it more likely that buffers can be used wherever required to meet slew and timing requirements.