Abstract: A method, system, and computer program product are disclosed for performing RC extraction from the perspective of the block level. A translation mechanism is employed to convert from a full-chip design domain to a block-level design domain. This allows model-based prediction results to be used in the early design implementation flow when parasitic RC and timing extractions are performed, where the model-based prediction results relate to predictions of manufacturing variations such as thickness and topography.

Abstract: A computer program generates a wire routing pattern that connects one driver with a plurality of receivers. The overlapping length of each vector pair, which consists of any two vectors headed from the driver to the receivers, is calculated. One vector pair that has the greatest overlapping length is selected. For the selected vector pair, three kinds of common nodes are created, each of which is used to make a common path part of the way to the receivers, to generate three kinds of renewed vector patterns. The operations are repeated and plural candidate routing patters are acquired. One candidate routing pattern having the smallest total wiring length is selected as the optimum routing pattern. If there exist plural patterns that have the same smallest total wiring length, one pattern can be selected that has the smallest one of the greatest D-R path lengths.

Abstract: Configuration of reconfigurable multidimensional fields are described. Information is provided for handling feedback, among other things.

Abstract: Methods, computer program products, and systems for interactively configuring the display of connectivity of a schematic diagram based on an integrated circuit (“IC”) design are provided. Using a set of criteria, the schematic diagram can be configured to reduce visual congestion caused by interconnections among circuit elements in the IC design. The criteria include interconnections having a specific number of fan-outs, interconnections connecting ports of specific types, interconnections connecting selected types of circuit elements, and interconnections connecting circuit elements with specific names. The amount of clutter caused by individual nets can also be reduced based on the total congestion score associated with each net. The total congestion score is calculated based on the number of bends that a net makes, the number of crossovers that a net makes, and the number of pixels required to draw the net.

Abstract: A method is provided for assigning signals to input pins of a component subject to asymmetric delays. A latency is determined for each signal-pin combination of the plurality of signals and plurality of input pins. The latency is determined as a function of an arrival time of the signal, a time to route the signal from to the input pin, and a time attributable to processing by the component. A latency threshold is selected. Signal to pin assignments using only signal-pin combinations having latencies less than or equal to the latency threshold are analyzed to determine if a one-to-one signal-to-pin assignment exists that includes all signals. The latency threshold is increased and the analysis is repeated until a valid one-to-one signal-to-pin assignment is found.

Abstract: Disclosed is a method, system, and computer program product for routing, modeling routes, and measuring congestion. In some embodiments, Gcells are implemented with reduced number of nodes to facilitate route modeling and congestion measurement. Some embodiments are particularly suitable for direct congestion and routing analysis of diagonal routing paths. In this way, congestion analysis can be directly performed along diagonal boundaries for diagonal routes, without requiring association with Gcell boundaries on Manhattan routing layers.

Abstract: In one embodiment, a method is provided for incremental routing of a circuit design having modified and unmodified signals. Critical routed signals of the partially routed circuit design are determined. For each critical routed signal, a first set of routing constraints is applied to prevent rerouting of the signal. The partially routed circuit design is routed according to the first set of routing constraints to produce a non-conflicting routing solution. In response to the non-conflicting routing solution not meeting timing requirements, the first set of routing constraints is removed and post-routing optimization processes are performed on the non-conflicting routing solution to reduce propagation delay of one or more signals.

Abstract: A storage medium recording a cell library having one or more cells that may be readable by a computer and may be used by the computer to design an integrated circuit. The one or more cells may have a physical dimension parameter and a channel width parameter. The physical dimension parameter may be a footprint of the one or more cells. The channel width parameter may have a minimum driver size and a maximum driver size. The channel width parameter may define a range within which a tool varies the channel width between the maximum driver size and the minimum driver size during a design flow of the integrated circuit based upon one or more power criteria without changing the footprint.

Abstract: Local constraints on placement of routing objects for direct connections between terminals in a circuit layout are determined from global constraints on the placement of the routing objects in a process referred to as global constraint budgeting. An autorouter finds paths in the layout to satisfy the local constraints and ignores the global constraints. The local constraints are updated before each routing pass to ensure that routes are completed on individual direct connections while also satisfying the global constraint.

Abstract: Techniques and mechanisms provide numerous representations and/or control of component interconnections in a digital design. For example, aspects of the invention provide a connection panel where connections can be presented in different modes. The different modes can run concurrently with each other or separately from each other. The different modes can also be manually or automatically selected to switch from one mode to another mode. For instance, the modes can be manually selected using an on-screen button or automatically selected by examining the location of the mouse pointer on the connection panel. Based on the different modes, component interconnections can be easily and efficiently handled and presented. Further, components can be automatically organized to minimize the number of crossing interconnects between them and/or maximize the amount of interconnection information presented.

Abstract: A computer program for generating an H-tree for an integrated circuit design stored on a computer readable medium includes code to receive from a user a set of parameters to configure the H-tree. The parameters include a starting segment length and an ending segment length. The computer program also includes code to select a starting location in the integrated circuit design. The computer program further includes code to place an anchor H at the starting location. The computer program further includes code to recursively place child Hs on the H-tree based on the starting segment length and the ending segment length to create a fan-out with equal weight on each child H. The number of levels of the H-tree is calculated according to a rounded down integer equal to a binary logarithm of a quotient of the starting segment length divided by the ending length.

Abstract: Creating and detecting crossings of conductive traces on different layers of an integrated circuit or a conducting trace over a device contact in a system. Values are stored by a system simulator corresponding to a galvanic potential or same “net”. According to a set of rule based instructions vias are automatically displayed, correct-by-construction, and via connections between the traces, or the trace and device contact, to short circuit the paths. The via structure will not be created if it will short-circuit a conducting trace not associated with the net in question. By connecting traces on different layers using automatically created via structures so as not to short circuit other net traces, errors are eliminated and design cycles reduced when compared to a manual design scheme of inserting via connections. There is an interactive mode which allows the via to be easily resized by the use of familiar control handles.

Abstract: A method, algorithm, software, architecture and/or system for routing signal paths or connections between circuit blocks in a circuit design is disclosed. In one embodiment, a method of routing can include: (i) determining a signal path between at least three circuit blocks; (ii) placing a routing guide; and (iii) routing the signal path through the routing guide such that a timing of a signal along the signal path at two or more the circuit blocks is substantially matched. The circuit blocks can include standard cells configured to implement a logic or timing function, other components, and/or integrated circuits, for example. The routing guide can include a splitter configured to branch the signal path into at least two associated segments. Embodiments of the present invention can advantageously improve signal timing for high fanout signal paths between circuit blocks in an automated place-and-route flow.

Abstract: Some embodiments provide a system for generating a memory-efficient representation of a sequence of electrically connected routing shapes. The memory-efficient representation represents the sequence of electrically connected routing shapes using a sequence of points, such that two consecutive points represent a routing shape. At least some of the points can be represented using a compact representation, thereby reducing the memory required for storing the sequence of points. A full representation specifies a point's location using the point's two-dimensional coordinates, and a compact representation specifies a point's location using one of the point's two-dimensional coordinates and an orientation indicator which indicates the routing shape's orientation. The missing coordinate in a compact representation can be determined from the preceding points. The system can represent a via that joins two routing shapes by assigning different metal layers to the points associated with the two routing shapes.

Abstract: A method of generating a circuit design comprising a T-coil network includes determining inductance for inductors and a parasitic bridge capacitance of the T-coil network. The parasitic bridge capacitance is compared with a load capacitance metric that depends upon parasitic capacitance of a load coupled to an output of the T-coil network. An amount of electrostatic discharge (ESD) protection of the circuit design that is coupled to the output of the T-coil network and/or a parameter of the inductors of the T-coil network is selectively adjusted according to the comparison. The circuit design, which can specify inductance of the inductors, the amount of ESD protection, and/or the width of windings of the inductors, is outputted.

Abstract: A behavioral synthesis apparatus includes a acquisition unit, a scheduling unit and a generation unit. The acquisition unit acquires a behavioral level description describing an operation of a semiconductor integrated circuit. The scheduling unit separates the acquired behavioral level description into N stage descriptions, and makes a schedule in such a way that input/output operations and computations among the N stage descriptions are pipelined. The generation unit generates a register transfer level description based on the N stage descriptions and a result of scheduling performed by the scheduling unit in such a way as to form stage circuits respectively corresponding to the N stage descriptions and a state control circuit which controls possible 2N?1 stage control states of the semiconductor integrated circuit. The generation unit generates the register transfer level description in such a way as to inhibit the operation of a stage circuit which need not be operated.

Abstract: Methods and apparatuses for incremental circuit partitioning and incremental trace assignment. In one embodiment of the present invention, a cost function based on both the partitioning solution and the trace assignment solution is used for the partitioning of a circuit; in reducing the cost function, blocks of circuits are moved among partitions and the trace assignment are updated accordingly to evaluate the cost function. In one embodiment, the traces and nets are grouped according to the partitions they connect for trace assignment. In one embodiment, a flow diagram is constructed for assigning nets to traces; and, maximum flow algorithms are used. In one embodiment, a flow diagram includes feedthrough solutions, in which flow conservation is not preserved at certain nodes. In one embodiment, integer linear programming techniques are used for assigning nets to traces.

Abstract: A technique will automatically route interconnect of an integrated circuit and adjust spacing between tracks or interconnect in order to improve performance or reduce electromigration effects. By increasing spacing between certain tracks or moving tracks, performance can improve because a track will be more noise immunity from nearby tracks on the same layer or on different layers. The automatic router will adjust spacing between tracks depending on one or more factors. These factors may include current associated with a track, width of a track, capacitance, inductance, and electromigration. In a specific implementation, the technique uses a shape-based approach where a grid is not used. The technique may further vary the width of the tracks.

Abstract: Homogenous dual-rail logic for DPA attack resistive secure circuit design is disclosed. According to one embodiment, an HDRL circuit comprises a primary cell and a complementary cell, wherein the complementary cell is an identical duplicate of the primary cell. The HDRL circuit comprises a first set of inputs and a second set of inputs, wherein the second set of inputs are a negation of the first set of inputs. The HDRL circuit has a differential power at a level that is resistive to DPA attacks.

Abstract: A technique will automatically route interconnect of an integrated circuit while taking into consideration current density rules. In an implementation, the technique uses a shape-based approach where a grid is not used. Based on data input including current density and a frequency of each net, the technique will determine the current requirements for each net. In an implementation, the technique forms a Steiner tree for a net, and routs using the Steiner tree. The technique widens nets having greater current requirements; adjacent wiring may be pushed aside to create sufficient space for wider nets.

Abstract: Computer-aided-design tools are provided that support real-time phase-locked loop reconfiguration with a single design compilation. Each design compilation may involve operations such as logic synthesis and place and route operations. A circuit designer who is designing an integrated circuit may supply circuit design data. The circuit design data may include design data for multiple configurations of a phase-locked loop. By using a phase-locked loop scan chain initialization file generator engine located in a CAD tool design input wizard, the computer-aided-design tools may produce multiple phase-locked loop initialization files without performing a design compilation. The CAD tools may process one or more initialization files and the circuit design data to produce output data. The output data may include configuration data to implement the circuit design.

Abstract: According an aspect of the invention, there is provided a design support system of a semiconductor integrated circuit includes: a first unit configured to determine a wiring path by calculating wiring resource consuming information for carrying out a connection through a multi-cut via in case that the connection is carried out through the multi-cut via in a wiring region having a plurality of layers; and a second unit configured to replacing a single-cut via into the multi-cut via.

Abstract: A layout design support apparatus divides a first module obtained by dividing a semiconductor integrated circuit into a plurality of second modules in order to support a layout design for determining the disposition of each cell constituting the semiconductor integrated circuit and wiring, and makes the detailed design of a layout for determining the disposition of each cell in the second module and wiring for each second module.

Abstract: Some embodiments of the invention provide a Local Preferred Direction (LPD) wiring model for use with one or more EDA tools (such as placing, routing, etc). An LPD wiring model allows at least one wiring layer to have a set of regions that each have a different preferred direction than the particular wiring layer. In addition, each region has a local preferred direction that differs from the local preferred direction of at least one other region in the set. Furthermore, at least two regions have two different polygonal shapes and no region in the set encompasses another region in the set. Some embodiments also provide a Graphical User Interface (GUI) that facilitates a visual presentation of an LPD design layout and provides tools to create and manipulate LPD regions in a design layout.

Abstract: A technique for implementing an engineering change order includes determining spares that are available to implement a modification to a circuit design. One of the available spares is then selected to implement the modification to the circuit design based on performance criteria associated with each of the available spares.

Abstract: A method for designing an integrated circuit is disclosed. The method generally comprises the steps of (A) splitting a design layout of the integrated circuit into a plurality of tiles, (B) adding a plurality of tie-to cells to the design layout, wherein at least one of the tie-to cells generating a tie-to signal at a particular logical level is added into each of the tiles having at least one gate with an input fixed to the particular logical level and (C) routing the tie-to signal to each of the inputs within each of the tiles.

Abstract: A system and method of connecting a macro cell to a system power supply network is disclosed. In a particular embodiment, the method includes determining a distance of an edge of the macro cell from a power line or a ground line of the system power supply network. The method further includes selectively adding at least one line to the system power supply network.

Abstract: A method of designing an integrated circuit (IC) having multiple dies can include identifying a unified design library having a first process node specific (PNS) library for a first IC process technology and a second PNS library for a second IC process technology. The first PNS library can be correlated with a first die of the IC. The second PNS library can be correlated with the second die of the IC. Via a processor, a circuit element can be defined within a circuit design implemented within the IC according to the PNS library correlated to the die in which the circuit element is located.

Abstract: In a layout process of a semiconductor integrated circuit, a power supply is initially formed in an arrangement in which the current threshold value is not exceeded. In a case where the excess over the current threshold value occurs after the power supply is formed, the power supply arrangement is changed according to the current threshold value, design rule data base, and power supply wiring density so as not to exceed the current threshold value.

Abstract: The present invention is directed to methods for disabling unused IO resources in a platform-based integrated circuit. A slice is received from a vendor. The slice includes an IO circuit unused by a customer. The IO circuit is disabled. For example, when the IO circuit is desired to be tied to a power source, a primary input/output pin of the IO circuit is shorted to a power bus of the IO circuit. When the IO circuit is desired to be tied to a ground source, a primary input/output pin of the IO circuit is shorted to a ground bus of the IO circuit. When the IO circuit is desired to be left floated, a primary input/output pin of the IO circuit is not connected to any bonding pad cell of the slice. Next, the IO circuit is removed from the customer's logic design netlist. The IO circuit is inserted in the vendor's physical design database.

Abstract: Overloaded regions in the routing space of a physical network are resolved via a routing procedure composed of a topological routing phase and a geometric routing phase. The overloads are resolved in the topological routing phase where the constraints of routing are less prohibitive. Multiple topological transformations directed toward resolving the overloads are executed in the topological routing phase prior to a geometric arrangement being realized. The topological transformations may be applied concurrently by way of a multi-threaded embodiment of the invention.

Abstract: A method for the design and layout for a patterned deep N-well. A tile is specified as a fundamental building block for the deep N-well pattern. The tile comprises a first element on a first layer and may comprise a second element on a second layer. A two dimensional region is covered with an array of contiguous tiles, with the elements on each layer connecting with elements of adjacent tiles to form extended shapes. The array may be converted to a collection of sub-arrays through the removal of tiles. The array or collection of sub-arrays may be merged to produce a first layer pattern and second layer pattern. Design rule checks may be applied to verify the pattern. The first layer shapes and second layer shapes may be edited. The first layer shapes and the second layer shapes may then be combined to produce a deep N-well pattern.

Abstract: An approach is provided for selectively optimizing a circuit design to be physical implemented. The approach includes generating a circuit routing solution in accordance with a plurality of constraints for parametric resources of the circuit design, with the constraints being defined respectively by a plurality of corresponding constraint instances. Each constraint instance variably indicates an effective constraining limit and degree of consumption for at least one of the parametric resources. At least one of the constraints is selectively adjusted by a predetermined over-constraining amount, and the circuit routing solution is preliminarily modified by applying at least one routing action selected responsive to the constraint adjustment. An automatic evaluation is then made of the potential impact upon constraint compliance.

Abstract: According to one embodiment, a design apparatus includes an extractor, a regression equation generator and an output module. The extractor extracts a critical part from a net list of a semiconductor integrated circuit. The critical part has a delay value greater than a delay threshold. The regression equation generator generates a regression equation to reproduce the delay value of the critical part using a regression algorithm. The output module outputs the regression equation.

Abstract: A congestive placement preventing apparatus, applied in a logic circuit layout having 2K logic circuits, where K is a positive integer, is provided. The congestive placement preventing apparatus includes a restructuring module and a synthesizing module. The restructuring module adds a selecting unit in the logic circuit layout, and adds (N?K) buffers in each of the 2K logic circuits, where N is a positive integer. The synthesizing module synthesizes the restructured logic circuit layout according to a plurality of “don't touch” synthesizing commands associated with the added buffers. In the synthesized logic circuit layout, all of the 2K logic circuits are independent and not coupled or merged with one another.

Abstract: A method used for supporting designing of a printed circuit board including a plurality of conductive layers having conductive areas to which a constant potential is applied, includes specifying conductive areas having a predetermined wiring from the conductive areas for each of the plurality of conductive layers, extracting areas that overlap each other in a planar view from the specified conductive areas, specifying an interlayer connection member that electrically connects at least two of the plurality of conductive layers in the extracted area, and clearly specifying an area within a predetermined distance from a center of the specified interlayer connection member and in the extracted area.

Abstract: An optical network design apparatus includes a memory and a processor. The memory stores a connection limit corresponding to the number of connections between ports. The processor provisionally designs a traffic path across an optical network independently of a connection limit of an asymmetric optical hub, calculates a penalty allowance with respect to the penalty limit of the traffic path, calculates an additional penalty caused on a detour path derived by replacing a port with a replacement port in the asymmetric optical hub, and if an asymmetric optical hub is included in the detour path, generates asymmetric optical hub information about the included asymmetric optical hub, generates, based on the connection limit, penalty allowance, additional penalty, and asymmetric optical hub information, a constraint condition for adopting the traffic path satisfying the connection limit and penalty limit, and calculates the traffic path by mathematical programming under the constraint condition.

Abstract: Improving routability of an integrated circuit (IC) design without impacting the area is described. A local region of congestion of an IC design is determined according to a design parameter. A cell with a specified level of complexity is identified within the local region of congestion. An alternative cell is algorithmically created with a same logic function as the cell by adding an access point to the alternative cell. The cell is then replaced with the alternative cell within the local region of congestion.

Abstract: Capacitance extraction techniques are provided. In one aspect, a method for analyzing variational coupling capacitance between conductors in an integrated circuit design is provided. The method comprises the following steps. Coupling capacitance is computed between conductors of interest from the design using a set of floating random walk paths. One or more of the conductors are perturbed. Any of the floating random walk paths affected by the perturbation are modified. The coupling capacitance between the conductors of interest is recomputed to include the modified floating random walk paths.

Abstract: A computer-implemented method of routing a circuit design for a target integrated circuit (IC) can include determining a characterization of routing congestion of the circuit design within the target IC and determining a first order cost component of using routing resources of the target IC according to the characterization. The method can include determining a higher order cost component of using routing resources of the target IC according to the characterization and assigning signals of the circuit design to routing resources according to costs calculated using the first order cost component and the higher order cost component. Signal assignments of the circuit design can be output.

Abstract: Provided is an integrated circuit layout design supporting device which can reduce the wiring length by avoiding bypass wirings when a plurality of same-type macro blocks are used. The integrated circuit layout design supporting device includes a terminal coordinate calculation control unit and a layout processing control unit. The terminal coordinate calculation control unit considers the plurality of same-type macro blocks included in a plurality of types of macro blocks as each of different types of macro blocks, and calculates the optimum coordinate positions of each macro terminal of each macro block. The layout processing control unit performs various types of wiring layout processing related to each of the macro terminals based on each of the macro terminal positions calculated by the terminal coordinate calculation control unit.

Abstract: Some embodiments of the invention provide a method of routing. The method selects a net with a set of routable elements in a multi-layer layout region. In some embodiments, the method identifies a route for the net based on different congestion goals on different layers. In other embodiments, the method identifies a route for the net based on different congestion goals between different layer pairs. In some embodiments, the method identifies a route for the net based on both the different congestion goals on different layers and between different layer pairs.

Abstract: A method, system, and computer usable program product for an improved object placement in integrated circuit design are provided in the illustrative embodiments. The IC design includes cells, the cells including electronic components, wires, and pins defined for interconnections of the IC. An initial placement corresponding to the design is received. A characteristic of the initial placement is estimated, which may include congestion, pin density, or both in an area of the initial placement. A transformation is performed on a part of the initial placement including the area to improve the characteristic. If the characteristic has improved in the transformed placement, a final placement corresponding to the transformed placement is produced. The transformation may be any combination of resizing an object, weighting a connection, clustering a plurality of objects, shortening of a route taken by a wire, and straightening a bend in a wire in the initial placement.

Abstract: A method, program product and apparatus include extending lengths that project from a microchip trace into dielectric material. The extending lengths may not connect to another trace. Placement of the extending lengths may be optimized to increase the dissipation of heat from the trace, while maintaining an acceptable level of capacitance.

Abstract: A technique will automatically route interconnect of an integrated circuit and adjust spacing between tracks or interconnect in order to improve performance or reduce electromigration effects. By increasing spacing between certain tracks or moving tracks, performance can improve because a track will be more noise immunity from nearby tracks on the same layer or on different layers. The automatic router will adjust spacing between tracks depending on one or more factors. These factors may include current associated with a track, width of a track, capacitance, inductance, and electromigration. In a specific implementation, the technique uses a shape-based approach where a grid is not used. The technique may further vary the width of the tracks.

Abstract: Disclosed are improved approaches for implementing design entry. An efficient, spread-sheet based representation is provided for both the instances and connections in a design. Visualization techniques provide the user with visual cues, to direct and identify compatible connection points, unconnected instances, and contention situations. Techniques are disclosed to automatically filter the spreadsheet in a variety of ways, to help the user to dynamically hide portions of the design space that are not interesting at a particular time, and thus to improve the efficiency with which they can work.

Abstract: A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box.

Abstract: A method of producing a flexible timing-driven routing tree is provided. Two or more target nodes are sorted in accordance with data criticality. A source-sink grid is built from one or more source nodes and the two or more target nodes. An initial routing tree is built comprising the one or more source nodes. A routing tree generation algorithm is executed on the initial routing tree, utilizing the sorted two or more target nodes and the source-sink grid in accordance with a user-defined timing factor to construct a flexible timing-driven routing tree. The user-defined timing factor specifies an extent of isolation for a routing path from a given one of the one or more source nodes to a given one of the two or more target nodes.

Abstract: A computer-implemented method of partitioning a circuit design into clock domains for implementation within a programmable integrated circuit (IC) can include storing a plurality of constraints that depend upon a plurality of variables, wherein the plurality of constraints regulate placement of components to different clock regions of the programmable IC. The method can include storing an objective function and determining a result indicating whether a feasible solution exists for clock domain partitioning of the circuit design by minimizing the objective function subject to the plurality of constraints. The result can be output.

Abstract: A method of performing a pre-route repeater insertion methodology for at least part of a circuit design may include: partitioning at least part of a circuit design into a plurality of tiles; determining at least one attribute of one or more individual tiles of the plurality of tiles; and determining a repeater solution based at least in part on the determined attributes of the one or more individual tiles. A computer implemented tool for performing a pre-route repeater insertion methodology for at least part of a circuit design may include: a module configured to partition at least part of a circuit design into a plurality of tiles; a module configured to determine at least one attribute of one or more individual tiles of the plurality of tiles; and a module configured to determine a repeater solution based at least in part on the determined attributes of the one or more individual tiles.