Abstract: A system and methods are provide for modeling the behavior of a lithographic scanner and, more particularly, a system and methods are provide using thresholds of an image profile to characterize through-pitch printing behavior of a lithographic scanner. The method includes running a lithographic model for a target tool and running a lithographic model on the matching tool for a plurality of different settings using lens numerical aperture, numerical aperture of the illuminator and annular ratio of a pattern which is produced by an illuminator. The method then selects the setting that most closely matches the output of the target tool.

Abstract: According to one embodiment, an original plate evaluation method is disclosed. The original plate includes a substrate and N patterns differing from one another in shape. The method includes selecting N1 patterns from the N patterns based on first criterion, obtaining measured values for the N1 patterns, performing a decision whether the obtained measured values satisfy first specification value, selecting N2 patterns from the N patterns based on second criterion, predicting shapes of transfer patterns corresponding to N2 patterns, performing a decision whether the predicted shapes satisfy second specification value, and evaluating the plate based on the decision.

Abstract: A method of forming a device is disclosed. The method includes providing at least one original artwork file having front end and back end information. The original artwork file includes an original artwork file format. A modified artwork file corresponding to the original artwork file is provided in a first modified artwork file format. The modified artwork file contains back end information. The method also includes checking to ensure that the original and modified artwork files are consistent.

Abstract: A method for decomposing a designed pattern layout and a method for fabricating an exposure mask using the same. After the designed pattern layout is automatically decomposed to obtain a plurality of mask layouts, a problematic region is determined through simulation of the mask layout, and fed back to correct the designed pattern layout. As a result, problems can be detected in each process and corrected to reduce the process time.

Abstract: Provided is an etch proximity correction method in which an accurate etch bias value is calculated. The etch proximity correction method includes creating an etch bias value from a project area corresponding to an area blocked by a pattern region within a linear distance projected from a target position selected in a target layout to an outermost portion of the proximity region and a non-project area corresponding to an area projected into an edge linear distance from an edge of the pattern region blocked in the linear distance to the outermost portion of the proximity region and correcting the target position in the layout using the etch bias value. Since an etch bias model includes the project area and the non-project area, the accurate etch bias value may be calculated.

Abstract: A method for resizing a pattern to be written by using lithography technique includes calculating a first dimension correction amount of a pattern for correcting a dimension error caused by a loading effect, for each small region made by virtually dividing a writing region of a target workpiece into meshes of a predetermined size, based on an area density of the each small region, calculating a second dimension correction amount in accordance with a line width dimension of the pattern to be written in the each small region, correcting the first dimension correction amount by using the second dimension correction amount, and resizing the line width dimension of the pattern by using a corrected first dimension correction amount, and outputting a result of the resizing.

Abstract: A method including providing a present wafer to be processed by a photolithography tool, selecting a processed wafer having a past chip design from a plurality of processed wafers, the processed wafer being previously processed by the photolithography tool, selecting a plurality of critical dimension (CD) data points extracted from a plurality of fields on the processed wafer, modeling the plurality of CD data points with a function relating CD to position on the processed wafer, creating a field layout on the present wafer for a new chip design, creating an initial exposure dose map for the new chip design using the function and the field layout, and controlling the exposure of the photolithography tool according to the initial exposure dose map to form the new chip design on the present wafer.

Abstract: A method includes: generating electron beam exposure data, used for electron beam exposure, from design data of a semiconductor device; extracting differential information indicating a difference in shape between an electron beam exposure pattern formed on a substrate through electron beam exposure on the basis of the electron beam exposure data and a photoexposure pattern formed on the substrate through photoexposure on the basis of the design data of the semiconductor device; determining whether the size of the difference in shape between the electron beam exposure pattern and the photoexposure pattern falls within a predetermined reference value; acquiring shape changed exposure data by changing the shape of the pattern of the electron beam exposure data in accordance with the differential information and updating the electron beam exposure data; and repeating the differential extraction, the determination and the updating when the size of the difference falls outside the predetermined reference value.

Abstract: A spare logic circuit for implementing any one of a plurality of logic gates includes a multiplexer circuit whose select inputs are utilized as logic gate inputs, and whose output is utilized as a logic gate output. Each of a plurality of data inputs of the multiplexer circuit is configured to receive one of first and second logic voltage levels which define the desired logic function. By modifying a single photolithographic mask, the spare logic gate can be: configured to perform the desired logic function; connected into a target logic circuit; or both configured and connected into a target logic circuit.

Abstract: One embodiment of the present invention provides a system that determines image intensity at a location in a photoresist (PR) layer on a wafer. During operation, the system receives a set of masks which were used to generate one or more patterned layers of a multilayer structure on the wafer, wherein a patterned layer includes a set of reflectors on a top surface of the patterned layer, which correspond to patterns in a patterned-layer mask in the set of masks, wherein a reflector reflects light from a light source during a photolithography process. The system then generates a first virtual mask based on the first mask and the patterned-layer mask, wherein the first virtual mask uses a clear area to model a reflector in the set of reflectors. Next, the system determines the image intensity value at the location on the PR layer based at least on the first mask and the first virtual mask.

Abstract: An optical proximity correction method is provided. A target pattern is provided, and then the target pattern is decomposed to a first pattern and a second pattern. The first pattern and the second pattern are alternately arranged in a dense region. Then, a compensation pattern is provided and it is determined whether the compensation pattern is added into the first pattern to become a first revised pattern, or into the second pattern to become a second revised pattern. Finally, the first revised pattern is output onto a first mask and the second revised pattern is output onto a second mask.

Abstract: According to various embodiments of the invention, systems and methods for system and methods for compressed post-OPC data created during the design and manufacturing of integrated circuits. In one embodiment of the invention, the method begins by generating a post-OPC layout from a circuit layout during the design phase of a circuit. This post-OPC layout is generated by way of an OPC process. Next, a set of differences between the post-OPC layout and the circuit layout are calculated and a dataset containing these differences are generated In some embodiments the dataset is generated during the OPC process.

Abstract: In one embodiment, a photomask designing method for creating a pattern layout having an assist pattern placed around a design pattern is disclosed. The method can place a plurality of evaluation points around the design pattern and set an evaluation index for imaging properties of the design pattern on an imaging surface. The method can combine a light intensity distribution of the design pattern with light intensity distributions of the evaluation points to obtain a light intensity distribution on the imaging surface and evaluate the light intensity distribution on the imaging surface using the evaluation index to determine a region having an effective evaluation point placed. In addition, the method can determine a placement condition for the assist pattern based on the region where the effective evaluation point is placed and place the assist pattern around the design pattern based on the placement condition to create the pattern layout.

Abstract: According to various embodiments of the invention, systems and methods for system and methods for compressed post-OPC data created during the design and manufacturing of integrated circuits. In one embodiment of the invention, the method begins by generating a post-OPC layout from a circuit layout during the design phase of a circuit. This post-OPC layout is generated by way of an OPC process. Next, a set of differences between the post-OPC layout and the circuit layout are calculated and a dataset containing these differences are generated In some embodiments the dataset is generated during the OPC process.

Abstract: According to one embodiment, an acceptance determining method of a blank for an EUV mask includes evaluating whether or not an integrated circuit device becomes defective, on the basis of information of a defect contained in a blank for an EUV mask and design information of a mask pattern to be formed on the blank. The integrated circuit device is to be manufactured by using the EUV mask. The EUV mask is manufactured by forming the mask pattern on the blank. And the blank is determined to be non-defective in a case that the integrated circuit device is not to be defective.

Abstract: A method and system for designing a photomask. The method provides a single machine methodology for inspecting photomasks having regions that repeat and regions that do not repeat. The method includes generating a chip dataset representing an integrated circuit chip design to be included in a cell region of a photomask, generating a kerf dataset to be included in the cell region, generating a kerf copy dataset, and merging the chip dataset, the kerf dataset and the kerf copy dataset into a photomask dataset representing a pattern of clear and opaque regions of the photomask.

Abstract: A method of forming a photomask includes providing a layout of design patterns, setting an optical proximity correction (OPC) with respect to the layout of design patterns, and forming a layout of correction patterns with respect to the layout of design patterns by using the set OPC. The method also includes collecting verification data about the layout of correction patterns by using a layout of contour patterns based on the layout of correction patterns, and verifying whether the layout of design patterns and the layout of correction patterns are substantially identical to each other by using the verification data.

Abstract: Data including information related to each area with a graphic disposed therein is inputted to the writing apparatus. The area is delimited with meshes each having a predetermined size. Next, an area value of a graphic lying within each of the meshes and its center-of-gravity position are determined. For every mesh, a check is made whether the area value is less than or equal to a predetermined value. When the area value is less than or equal to the predetermined value, a range allowable for an x coordinate of the center-of-gravity position is determined and a check is made whether an actual x coordinate falls within this range. Next, a range allowable for a y coordinate of the center-of-gravity position is determined and a check is made whether an actual y coordinate falls within this range.

Abstract: A mechanism is provided for simultaneous optical proximity correction (OPC) and decomposition for double exposure lithography. The mechanism begins with two masks that are equal to each other and to the target. The mechanism simultaneously optimizes both masks to obtain a wafer image that both matches the target and is robust to process variations. The mechanism develops a lithographic cost function that optimizes for contour fidelity as well as robustness to variation. The mechanism minimizes the cost function using gradient descent. The gradient descent works on analytically evaluating the derivative of the cost function with respect to mask movement for both masks. It then moves the masks by a fraction of the derivative.

Abstract: A method for the creation of rectilinear Steiner minimum trees includes determining a set of candidate connections from a terminal node to a different terminal node or to a graph edge. The length of each candidate connection may be used to determine the set of candidate connections that span the graph with a minimum total length.

Abstract: One embodiment of a method for process window optimized optical proximity correction includes applying optical proximity corrections to a design layout, simulating a lithography process using the post-OPC layout and models of the lithography process at a plurality of process conditions to produce a plurality of simulated resist images. A weighted average error in the critical dimension or other contour metric for each edge segment of each feature in the design layout is determined, wherein the weighted average error is an offset between the contour metric at each process condition and the contour metric at nominal condition averaged over the plurality of process conditions. A retarget value for the contour metric for each edge segment is determined using the weighted average error and applied to the design layout prior to applying further optical proximity corrections.

Abstract: A solution for improving photomask fabrication time and yield, through the reduction in the number of exposure shots used for a given photomask pattern to be written on the photomask. In one embodiment, non-critical elements can be configured into a shape that the write tool can write with less exposure shots, while maintaining the original intent of the non-critical element. In another embodiment, the pattern of non-critical elements can be configured such that the non-critical elements are aligned with the grid lines of the operational grid of the write tool to further reduce shot count. In another embodiment, the manufacturing parameters and placement of non-critical elements can be modifying, e.g., by identifying which elements are critical and which are non-critical, and then printing non-critical elements with a first exposure parameter (e.g. a single pass exposure) while critical elements are printed with a second exposure parameter (e.g., a multi pass exposure).

Abstract: A method for inspecting lithography masks includes generating integrated circuit design data and using context information from the integrated circuit design data to inspect a mask.

Abstract: A pattern verification-test method according to an embodiment of the present invention includes: deriving an illumination condition at a verification-test subject position in a photomask surface of a mask pattern as a verification or a test subject based on the verification-test subject position and illumination condition information about a distribution of an illumination condition in a photomask surface of exposure light incident on the mask pattern, performing lithography simulation on the mask pattern based on the derived illumination condition and the mask pattern, and verifying or testing the mask pattern based on a result of the lithography simulation.

Abstract: Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation.

Abstract: This invention discloses a photomask manufacturing method. A pattern dimensional map is generated by preparing a photomask in which a mask pattern is formed on a transparent substrate, and measuring a mask in-plane distribution of the pattern dimensions. A transmittance correction coefficient map is generated by dividing a pattern formation region into a plurality of subregions, and determining a transmittance correction coefficient for each of the plurality of subregions. The transmittance correction value of each subregion is calculated on the basis of the pattern dimensional map and the transmittance correction coefficient map. The transmittance of the transparent substrate corresponding to each subregion is changed on the basis of the transmittance correction value.

Abstract: A method of generating an integrated circuit with a DPT compatible via pattern using a reduced DPT compatible via design rule set. A reduced DPT compatible via design rule set. A method of forming an integrated circuit using a via pattern generated from a reduced DPT compatible design rule set.

Abstract: A method and system for computing Fourier coefficients for a Fourier representation of a mask transmission function for a lithography mask. The method includes: sampling a polygon of a mask pattern of the lithography mask to obtain an indicator function which defines the polygon, performing a Fourier Transform on the indicator function to obtain preliminary Fourier coefficients, and scaling the Fourier coefficients for the Fourier representation of the mask transmission function, where at least one of the steps is carried out using a computer device.

Abstract: A semiconductor device includes: a plurality of line features including at least one real feature which includes a gate electrode portion, and at least one dummy feature. Two of multiple ones of the dummy feature, and at least one of the line features interposed between the two dummy features and including the at least one real feature form parallel running line features which are evenly spaced. The parallel running line features have an identical width, and line end portions of the parallel running line features are substantially flush. Line end portion uniformization dummy features are formed on extensions of the line end portions of the parallel running line features. The line end portion uniformization dummy features include a plurality of linear features each having a same width as each of the line features and spaced at intervals equal to an interval between each adjacent pair of the line features.

Abstract: A method of generating complementary masks based on a target pattern having features to be imaged on a substrate for use in a multiple-exposure lithographic imaging process is disclosed. The method includes defining an initial H-mask and an initial V-mask corresponding to the target pattern; identifying horizontal critical features in the H-mask and vertical critical features in the V-mask; assigning a first phase shift and a first percentage transmission to the horizontal critical features, which are to be formed in the H-mask; and assigning a second phase shift and a second percentage transmission to the vertical critical features, which are to be formed in the V-mask. The method further includes the step of assigning chrome to all non-critical features in the H-mask and the V-mask.

Abstract: A technique for reconstructing a mask pattern corresponding to a photo-mask using a target mask pattern (which excludes defects) and an image of at least a portion of the photo-mask is described. This image may be an optical inspection image of the photo-mask that is determined using inspection optics which includes an optical path, and the reconstructed mask pattern may include additional spatial frequencies than the image. Furthermore, the reconstructed mask pattern may be reconstructed based on a characteristic of the optical path (such as an optical bandwidth of the optical path) using a constrained inverse optical calculation in which there are a finite number of discrete feature widths allowed in the reconstructed mask pattern, and where a given feature has a constant feature width. Consequently, the features in the reconstructed mask pattern may each have the constant feature width, such as an average critical dimension of the reconstructed mask pattern.

Abstract: The embodiments of via mask splitting methods for double patterning technology described enable via patterning to align to a metal layer underneath or overlying to reduce overlay error and to increase via landing. If adjacent vias violate the G0-mask-split-rule for space or pitch (or both) between vias, the mask assignment of end vias are given higher priority to ensure good landing of end vias, since they are at higher risk of mislanding. The metal correlated via mask splitting methods enable better via performance, such as lower via resistance, and higher via yield.

Abstract: A method of manufacturing a semiconductor device, including the steps of: acquiring information on a graphic composing a physical layout of a semiconductor integrated circuit; carrying out calculation for a transferred image in the physical layout; carrying out calculation for a signal delay based on the physical layout, and obtaining a wiring not meeting a specification having the signal delay previously set therein; and setting a portion into which a repeater is to be inserted based on at least one result of results obtained from the information on the graphic and calculation for the transferred image, respectively, with respect to the wiring not meeting the specification.

Abstract: A design process for varying hole locations or sizes or both in an ion beam grid includes identifying a control grid to be modified; obtaining a change factor for the grid pattern; and using the change factor to generate a new grid pattern. The change factor is one or both of a hole location change factor or a hole diameter change factor. Also included is an ion beam grid having the characteristic of hole locations or sizes or both defined by a change factor modification of control grid hole locations or sizes or both.

Abstract: A method and system for lithography simulation and measurement of critical dimensions with improved CD marker generation and placement is disclosed. The method and system specify a position for measuring a difference between a lithography image and a target pattern, generate one or more CD marker candidates, and select at least one CD marker from the one or more CD marker candidates.

Abstract: A two-dimensional transmission cross coefficient is obtained based on a function representing a light intensity distribution formed by an illumination apparatus on a pupil plane of the projection optical system and a pupil function of the projection optical system. Based on the two-dimensional transmission cross coefficient and data of a pattern on an object plane of the projection optical system, an approximate aerial image is calculated by using at least one of plural components of an aerial image on an image plane of the projection optical system. Data of a pattern of an original is produced based on the approximate aerial image.

Abstract: Systems and methods for creating and implementing two-dimensional (2D), image-based design rules (IBDRs) are disclosed. Techniques for creating 2D IBDR can include identifying a search pattern that is representative of a 2D pattern of interest of a design, creating a pattern representation based on the search pattern, defining an anchor point for the pattern representation, and assigning weights to elements of the pattern representation. The 2D MDR can be used in systems and method for searching a design by comparing the 2D IBDR to the design. A number of 2D IBDRs can be merged into a subset of similar 2D IBDRs by characterizing desired rule geometries, sorting the 2D IBDRs into groups according to the desired rule geometries, merging the groups of 2D IBDRs into a single representative search pattern. Additionally, standard design rules can be created from the disclosed 2D IBDRs.

Abstract: A method and system checks a double patterning layout and outputs a representation of G0-rule violations and critical G0-spaces. The method includes receiving layout data having patterns, determining whether each distance between adjacent pattern elements is a G0-space, find all G0-space forming a G0-rule violation, finding all G0-space that are critical G0-spaces, and outputting a representation of G0-rule violations and critical G0-spaces to an output device. By resolving G0-rule violations and critical G0-spaces, a design checker can effectively generate a double patterning technology (DPT) compliant layout.

Abstract: Some embodiments include methods in which a mathematical representation of a photomask construction is defined, with such representation comprising a plurality of pillars that individually contain a plurality of distinct layers. Each of the layers has two or more characteristic parameters which are optimized through an optimization loop. Subsequently, specifications obtained from the optimization loop are utilized to form actual layers over an actual reticle base. Some embodiments include photomask constructions in which a radiation-patterning topography is across a reticle base, with such topography including multiple pillars that individually contain at least seven distinct layers.

Abstract: A computer readable medium comprising multiple instructions stored in a computer readable device, upon executing these instructions, a computer performing the following steps: providing a first semiconductor layout and a second semiconductor layout predetermined to be fabricated on different material layers of a semiconductor device, the second semiconductor layout comprising a circuit pattern; setting a forbidden area of the circuit pattern on the first semiconductor layout according to a restriction condition; defining at least a virtual pattern arrangement area on a portion of the first semiconductor layout which does not correspond to the forbidden area; and selecting a positioning point at a boundary of the virtual pattern arrangement area and providing a virtual pattern array in the virtual pattern arrangement by taking the positioning point as an origin of a coordinate system of the virtual pattern array.

Abstract: A mechanism is provided for resolving patterning conflicts. The mechanism performs decomposition with stitches at all candidate locations to find the solution with the minimum number of conflicts. The mechanism then defines interactions between a layout of a first mask and a layout of a second mask through design rules, as well as interactions of mask1/mask2 with top and bottom layers (i.e., contacts, vial, etc.). The mechanism then gives the decomposed layout and design rule definition to any existing design rule fixing or layout compaction tool to solve native conflicts. The modified design rules are that same-layer spacing equals spacing of single patterning, different-layer spacing equals spacing of final layout, and layer overlap equals minimum overlap length.

Abstract: One embodiment of the present invention provides techniques and systems for modeling mask errors based on aerial image sensitivity. During operation, the system can receive an uncalibrated process model which includes a mask error modeling term which is based at least on an aerial image sensitivity to mask modifications which represent mask errors. Next, the system can fit the uncalibrated process model using measured CD data. Note that the mask error modeling term can also be dependent on the local pattern density. In some embodiments, the mask error modeling term can include an edge bias term and a corner rounding term. The edge bias term can be based on the sensitivity of the aerial image intensity to an edge bias, and the corner rounding term can be based on the sensitivity of the aerial image intensity to a corner rounding adjustment.

Abstract: A stencil for character projection (CP) charged particle beam lithography and a method for manufacturing the stencil is disclosed, where the stencil contains two circular characters, where each character is capable of forming patterns on a surface in a range of sizes by using different dosages, and where the size ranges for the two characters is continuous. A method for forming circular patterns on a surface using variable-shaped beam (VSB) shots of different dosages is also disclosed. A method for forming circular patterns on a surface using a set of shots, where all of the shots comprise dosages, is also disclosed.

Abstract: A method for the reproducible determination of the positions of structures (3) on a mask (2) is disclosed. A pellicle frame (30) is firmly attached to the mask (2). A theoretical model of the bending of the mask (2) with the firmly attached pellicle frame (30) is calculated, wherein material properties of the mask (2), of the pellicle frame (30), and of the attaching means between the pellicle frame (30) and the mask (2) are taken into account in the calculation of the bending of the mask (2). For the calculation of the bending of the mask (2) its contact with three support points is considered. The positions of the structures (3) on the mask (2) are measured with a metrology tool (1). The measured positions of each structure are corrected with the theoretical model of the bending of the mask at the position of the respectively measured structure.

Abstract: The present invention provides a generation method that obtains a position at which an auxiliary pattern is to be placed and generates a mask pattern (its data), which achieves excellent imaging performance, even when a halftone mask is used as an original.

Abstract: Methods and apparatus are disclosed that arrange mask patterns in response to the contribution of a second pattern to image intensity. In some methods of arranging mask patterns, a distribution of functions h(??x) is obtained which represents the contribution of a second pattern to image intensity on a first pattern. Neighboring regions of the first pattern are discretized into finite regions, and the distribution of the functions h(??x) is replaced with representative values h(x,?) of the discretized regions. A position of the second pattern is determined using polygonal regions having the same h(x,?). As described, the term x is the position of the first pattern and the term ? is the position of the assist.

Abstract: A method of exposing a pattern on a light sensitive surface comprises forming a spatially modulated light beam including a rectangular matrix pattern of rows and columns of image data over a surface, wherein the spatially modulated light beam is operable to expose contiguous sub-exposure areas of the surface, each sub-exposure area associated with a datum of the image data, aligning one of the rows or columns of the spatially modulated light beam with a scan direction and the other one of the rows and columns of the spatially modulated light beam with a cross-scan direction for exposing the surface, shearing at least one portion of the modulated light beam with respect to a second portion of the modulated light beam in a cross scan direction by an amount less than a center to center distance between two sub-exposure areas in a cross scan direction, exposing the surface in the scan direction with the sheared spatially modulated light beam, and overlapping exposed sub-areas in the cross scan direction as a resu

Abstract: A method and a computer system for designing an optical photomask for forming a prepattern opening in a photoresist layer on a substrate wherein the photoresist layer and the prepattern opening are coated with a self-assembly material that undergoes directed self-assembly to form a directed self-assembly pattern. The methods includes: generating a mask design shape from a target design shape; generating a sub-resolution assist feature design shape based on the mask design shape; using a computer to generate a prepattern shape based on the sub-resolution assist feature design shape; and using a computer to evaluate if a directed self-assembly pattern of the self-assembly material based on the prepattern shape is within specified ranges of dimensional and positional targets of the target design shape on the substrate.

Abstract: According to a mask verifying method of the embodiment, a difference between an actual dimension of a mask pattern and a simulation dimension is calculated as a computational estimated value. Moreover, a difference between an actual dimension of the mask pattern that is actually measured and a dimension on pattern data is calculated as an actually-measured difference. Then, it is verified whether a mask pattern dimension passes or fails based on the calculated value. When calculating the computational estimated value, a model function, which is set based on each correspondence relationship between an actual dimension and a mask simulation dimension of a test pattern, which includes a plurality of types of pattern ambient environments, to the mask pattern.

Abstract: According to one embodiment, a design layout highly likely to be a dangerous point in a lithography process is set, a coherence map kernel for generating the mask layout is set with respect to the set design layout, the coherence map is created based on the set coherence map kernel and the set design layout, the auxiliary pattern is extracted from the created coherence map and shaped to generate the mask layout, a cost function COST for evaluating an optimization degree of the mask layout is defined, the generated mask layout is evaluated using the cost function, and at least one of parameters of the coherence map kernel and parameters in extracting and shaping the auxiliary pattern from the coherence map are changed until the mask layout evaluated using the cost function is optimized.