Abstract: A method is provided for inspecting a chip layout. The method includes providing a chip layout having a plurality of patterns designed according to a design rule and performing a first inspection to the plurality of patterns according to the design rule. The method also includes determining patterns violating the design rule, as violating patterns, and corresponding violation values, and determining violating patterns having a minimum violation value among the violating patterns. Further, the method includes classifying the violating patterns having the minimum violation value into at least one sub-category based on characteristics of the violating patterns having the minimum violation value, and performing a second inspection on a selected violating pattern from the sub-category to determine whether the selected violating pattern and other violating patterns in the sub-category satisfy fabrication process conditions.

Abstract: A multivariable solver for proximity correction uses a Jacobian matrix to approximate effects of perturbations of segment locations in successive iterations of a design loop. The problem is formulated as a constrained minimization problem with box, linear equality, and linear inequality constraints. To improve computational efficiency, non-local interactions are ignored, which results in a sparse Jacobian matrix.

Abstract: Described herein are methods for matching the characteristics of a lithographic projection apparatus to a reference lithographic projection apparatus, where the matching includes optimizing projection optics characteristics. The projection optics can be used to shape wavefront in the lithographic projection apparatus. According to the embodiments herein, the methods can be accelerated by using linear fitting algorithm or using Taylor series expansion using partial derivatives of transmission cross coefficients (TCCs).

Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having a main feature; performing an optical proximity correction (OPC) process to the design layout; and thereafter, performing a jog reduction process to the design layout such that jog features of the design layout are reduced.

Abstract: A method of making a mask includes receiving an IC design layout from a designer, applying an logic operation (LOP) correction, performing an OPC correction, fracturing the modified data into a plurality of main features in an electron beam format, and sending the electron beam format data to a mask writer for a mask fabrication. An XOR operation is implemented into the method to check and verify if a pattern is lost during OPC modification and/or data fracture. A BACKBONE XOR operation is also implemented into the method for a plurality of main features with a critical dimension (CD) size smaller than the max OPC correction to check and verify if a small pattern feature is lost during OPC modification and/or data fracture for 45 nm and beyond semiconductor technologies.

Abstract: Systems and methods are disclosed for a stochastic model of mask process variability of a photolithography process, such as for semiconductor manufacturing. In one embodiment, a stochastic error model may be based on a probability distribution of mask process error. The stochastic error model may generate a plurality of mask layouts having stochastic errors, such as random and non-uniform variations of contacts. In other embodiments, the stochastic model may be applied to critical dimension uniformity (CDU) optimization or design rule (DR) sophistication.

Abstract: Methods for fabricating semiconductor devices are provided. In an embodiment, a method of fabricating a semiconductor device includes scanning a circuit design layout and proposing patterns for decomposed layouts. The proposed patterns are then compared with a library of prior patterns including a category of forbidden patterns and a category of preferred patterns. If a selected proposed pattern matches a forbidden pattern, the selected proposed pattern is eliminated. If the selected proposed pattern matches a preferred pattern, then the selected proposed pattern is identified for use in the decomposed layouts. Decomposed layouts are generated from the identified patterns. A plurality of masks is fabricated based on the decomposed layouts. Then a multiple patterning lithographic technique is performed with the plurality of masks on a semiconductor substrate.

Abstract: A computer-implemented method of determining an attribute of a circuit includes using a computationally expensive technique to simulate the attribute (such as timing delay or slew) of a portion of the circuit, at predetermined values of various parameters (e.g. nominal values of channel length or metal width), to obtain at least a first value of the attribute. The method also uses a computationally inexpensive technique to estimate the same attribute, thereby to obtain at least a second value which is less accurate than the first value. Then the computationally inexpensive technique is repeatedly used on other values of the parameter(s), to obtain a number of additional second values of the attribute. Applying to the additional second values, a function obtained by calibrating the at least one second value to the at least one first value, can yield calibrated estimates very quickly, which represent the attribute's variation relatively accurately.

Abstract: An apparatus and method for reporting design rule violations of an integrated circuit design includes collecting data from a design rule checker module, processing the data, and displaying design rule violations onto the layout. The display of the design rule violations may be interactive by including hypertext links to specifications, text bubbles with violation explanations, measurements, highlighting areas of the layout corresponding to a particular rule, and providing hierarchically expandable nodes for constraint violations in a browser.

Abstract: Data associated with a substrate can be processed by measuring a property of at least a first type of specific features and a second type of specific features on a substrate. The first type of specific features is measured at a first plurality of locations on the substrate to generate a first group of measured values, and the second type of specific features is measured at a second plurality of locations on the substrate to generate a second group of measured values, in which the first and second groups of measured values are influenced by critical dimension variations of the substrate. A combined measurement function is defined based on combining the at least first and second groups of measured values. At least one group of measured values is transformed prior to combining with another group or other groups of measured values, in which the transformation is defined by a group of coefficients.

Abstract: A method for verifying that acceptable device feature gradients and device feature disparities are present in a semiconductor device layout, is provided. The method provides for dividing a device layout into a plurality of windows and measuring or otherwise determining the device feature density within each window. The device layout includes various device regions and the method provides for comparing an average device feature density within one region to surrounding areas or other regions and also for determining gradients of device feature densities. The gradients may be monitored from within a particular device region to surrounding regions. Instructions for carrying out the method may be stored on a computer readable storage medium and executed by a processor.

Abstract: A method, system, and computer program product for classifying and prioritizing a set of recommended rule (RR) violations in an integrated circuit (IC) design are provided in the illustrative embodiments. The set of RR violations is received. A layout corresponding to the IC design is received. A set of features is selected in the layout. A classification model corresponding to the set of features is selected. Using the set of features and the classification model, the first RR violation is classified into a classification from a set of classifications. The classification is prioritized in an order of priority such that the first RR violation in the classification is recommended for remedying in the order of priority.

Abstract: A method of forming a compact model for an electrical device includes obtaining shape information for the device and obtaining nominal information for the device. The method also includes merging the shape information and the nominal information to form composite data, and fitting the compact model to the composite data.

Abstract: Various embodiments related to correlating a location of a defect on a substrate for a semiconductor device to an electrical significance of a device structure at that location are disclosed. For example, one embodiment includes receiving a defect location for the location on the substrate where the defect was detected; receiving a physical representation of the semiconductor device for the defect location; generating a significance determination indicating whether the defect is located in an electrically significant region by correlating the defect location to logical and physical layout information included in the physical representation; and displaying the significance determination.

Abstract: Aspects of the invention relate to techniques for determining edge fragment correlation information. With various implementations of the invention, image intensity slope information for edge fragments in a layout design is determined. The image intensity slope information comprises information describing how image intensity for each of the edge fragments changes with its position. Image amplitude sensitivity information for the edge fragments is also determined. The image amplitude sensitivity information comprises information describing how image amplitude for each of the edge fragments changes with positions of neighboring edge fragments. Based on the image intensity slope information and the image amplitude sensitivity information, edge fragment correlation information for the edge fragments is determined. Using the edge fragment correlation information, the layout design may be processed by using, for example, OPC techniques.

Abstract: Disclosed are techniques for simulating and correcting the mask shadowing effect using the domain decomposition method (DDM). According to various implementations of the invention, DDM signals for an extreme ultraviolet (EUV) lithography mask are determined for a plurality of azimuthal angles of illumination. Base on the DDM signals, one or more layout designs for making the mask may be analyzed and/or modified.

Abstract: A method for creating double patterning compliant integrated circuit layouts is disclosed. The method allows patterns to be assigned to different masks and stitched together during lithography. The method also allows portions of the pattern to be removed after the process.

Abstract: A method includes performing a place and route operation using an electronic design automation tool to generate a preliminary layout for a photomask to be used to form a circuit pattern of a semiconductor device. The place and route operation is constrained by a plurality of single patterning spacer technique (SPST) routing rules. Dummy conductive fill patterns are emulated within the EDA tool using an RC extraction tool to predict locations and sizes of dummy conductive fill patterns to be added to the preliminary layout of the photomask. An RC timing analysis of the circuit pattern is performed within the EDA tool, based on the preliminary layout and the emulated dummy conductive fill patterns.

Abstract: A method of manufacturing an exposure mask includes generating or preparing flatness variation data relating to a mask blanks substrate to be processed into an exposure mask, the flatness variation data being data relating to change of flatness of the mask blank substrate caused when the mask blank substrate is chucked by a chuck unit of an exposure apparatus, generating position correction, data of a pattern to be drawn on the mask blanks substrate based on the flatness variation data such that a mask pattern of the exposure mask comes to a predetermined position in a state that the exposure mask is chucked by the chuck unit, and drawing a pattern on the mask blanks substrate, the drawing the pattern including drawing the pattern with correcting a drawing position of the pattern and inputting drawing data corresponding to the pattern and the position correction data into a drawing apparatus.

Abstract: A method of data preparation in lithography processes is described. The method includes providing an integrated circuit (IC) layout design in a graphic database system (GDS) grid, converting the IC layout design GDS grid to a first exposure grid, applying a non-directional dither technique to the first exposure, coincident with applying dithering to the first expose grid, applying a grid shift to the first exposure grid to generate a grid-shifted exposure grid and applying a dither to the grid-shifted exposure grid, and adding the first exposure grid (after receiving dithering) to the grid-shifted exposure grid (after receiving dithering) to generate a second exposure grid.

Abstract: A system and method for improved electron beam writing that is capable of taking design intent, equipment capability and design requirements into consideration. The system and method determines an optimal writing pattern based, at least in part, on the received information.

Abstract: A flare map calculating method of an embodiment calculates an optical image intensity distribution in each division region set in a pattern region. Furthermore, an average value of the optical image intensity distribution is calculated in each division region. A pattern or plural patterns, which has a pattern density corresponding to the average value, is calculated as a corresponding density pattern in each division region. Furthermore, a density map, which represents a pattern density distribution within the pattern region, is generated based on the corresponding density pattern, and a flare map representing a flare intensity distribution within the pattern region is calculated by convolution integral of the density map and a point spread function.

Abstract: The invention is directed to a method for checking a die seal ring on a layout. The method comprises steps of receiving a digital database of a layout corresponding to at least a device with a text information corresponding to the layout. Tape-out information corresponding to the layout is received. A checking process is performed according to the digital database of the layout and the tape-out information and, meanwhile, a mask design procedure for designing a mask pattern corresponding to the layout is performed by using the digital database of the layout, the text information and the tape-out information. A result of the checking process is recorded in an inspection table corresponding to the layout.

Abstract: Methods for fabricating semiconductor devices are provided. In an embodiment, a method of fabricating a semiconductor device includes scanning a circuit design layout and proposing patterns for decomposed layouts. The proposed patterns are then compared with a library of prior patterns including a category of forbidden patterns and a category of preferred patterns. If a selected proposed pattern matches a forbidden pattern, the selected proposed pattern is eliminated. If the selected proposed pattern matches a preferred pattern, then the selected proposed pattern is identified for use in the decomposed layouts. Decomposed layouts are generated from the identified patterns. A plurality of masks is fabricated based on the decomposed layouts. Then a multiple patterning lithographic technique is performed with the plurality of masks on a semiconductor substrate.

Abstract: One embodiment of a method for process window optimized optical proximity correction includes applying optical proximity corrections to a design layout, simulating a lithography process using the post-OPC layout and models of the lithography process at a plurality of process conditions to produce a plurality of simulated resist images. A weighted average error in the critical dimension or other contour metric for each edge segment of each feature in the design layout is determined, wherein the weighted average error is an offset between the contour metric at each process condition and the contour metric at nominal condition averaged over the plurality of process conditions. A retarget value for the contour metric for each edge segment is determined using the weighted average error and applied to the design layout prior to applying further optical proximity corrections.

Abstract: A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing a double patterning technology-compliant logical design for the integrated circuit, the logical design including a plurality of elements; scoring the design of one or more of the plurality of elements to produce a design score; modifying the design based at least in part on the design score; generating a mask set implementing the modified logical design; and employing the mask set to implement the logical design in and on a semiconductor substrate.

Abstract: Disclosed are method(s), system(s), and article(s) of manufacture for implementing a layout of an electronic circuit using one or more constraint checking windows. The method identifies some constraints on multiple-patterning lithography and multiple constraint checking windows for the layout. The method determines one or more metrics for a constraint checking window or for a layout and assigns one or more shapes in the one or more constraint checking windows to their respective mask designs based on the one or more metrics. The method traverses through the one or more constraint checking windows until all shapes in the layout are assigned to their respective mask designs. The method may also determine a processing order for the one or more constraint checking windows based on the distribution of a type of shapes in the layout.

Abstract: A mechanism is provided for multiple patterning lithography with conflict removal aware coloring. The mechanism makes multiple patterning coloring aware of the conflict removal overhead. The coloring solution explicitly considers ease of conflict removal as one of the coloring objectives. The mechanism pre-computes how much shapes can move in each direction. The mechanism generates a conflict graph where nodes represent shapes in the layout and edges represent conflicts between shapes. The mechanism assigns weights to edges based on available spatial slack between conflicting features. The mechanism then uses the weights to guide multiple patterning coloring. The mechanism prioritizes conflicting features with higher weights to be assigned different colors.

Abstract: Methods for jointly calibrating etch and exposure mask process models from etch only data are described. Initially, an etch model and an exposure model may be identified. Subsequently, a combined etch/exposure model may be generated based upon the etch model and the exposure model. Following which, a global optimization process may be performed to calibrate the combined etch/exposure model based upon measured data representing the etch and the exposure effects. With some implementations, the global optimization process is based in part upon a cost function representing the norm of the difference between the simulated mask contours and the measured mask contours. Furthermore, in some implementations, the optimization variable set is the union of the parameter sets corresponding to the etch model and the exposure model individually. Further still, with various implementations, the optimization of based upon the etch parameter set is “nested” inside an optimization of the exposure parameter set, or, vice versa.

Abstract: A relational database may be integrated into an integrated circuit design and analysis environment as the persistent data store for data associated with the design. This design data may include two or more abstractions of the design, such as layout data models and timing data models, in some embodiments. Design data may be partitioned in the database and indexed according to various attributes. The use of a relational database may facilitate cross-probing of design data corresponding to different abstractions of the design. The relational database may be queried to produce design reports and to identify design errors or weaknesses. Reports may be graphical or tabular, and may be displayed, printed, stored, or posted for viewing. Proposed modifications to a design may be investigated by modifying data in the relational database, rather than in the actual design. Design reports may be re-generated and compared with corresponding reports for the un-modified design.

Abstract: Various embodiments are directed at methods and systems for implementing automatic fixing of a layout, implementing fuzzy pattern replacement, and implementing pattern capturing in a layout of an electronic circuit design. Various processes or modules comprise the act or module of identifying a first pattern from within an electronic circuit layout. The processes or modules also comprise identifying a fixing process or a replacement pattern for the first pattern and the act of performing pattern replacement or pattern fixing on the first pattern. The processes or modules may further comprise the act or module of searching the layout for patterns that match the first pattern, and the act or module of performing pattern replacement of pattern fixing on the patterns that match the first pattern. Some embodiments are also directed at articles of manufacture embodying a sequence of instructions for implementing the processes described here.

Abstract: A method for automatically decomposing a shape of an IC design layout into two or more shapes in order to resolve a double patterning loop violation involving the shape. The method decomposes the shape by introducing one or more splicing graphs on the shape. These splicing graphs serve as cuts to be made on the shape. By decomposing the shape into several shapes and assigning the shapes to alternating masks for the same layer, the method breaks the double patterning loop. That is, no pair of the shape and other shapes that form the loop will be assigned to the same color for a mask after the shape is decomposed. In some embodiments, the method introduces splicing points to more than one shape of the loop-forming shapes when necessary. Some embodiments minimize the number of splicing points introduced to the shape(s).

Abstract: In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques.

Abstract: A computer-implemented method for improving a lithographic process for imaging a portion of a design layout onto a substrate using a lithographic projection apparatus comprising an illumination source and projection optics, the method including computing a multi-variable cost function of a plurality of design variables that are characteristics of the lithographic process, at least some of the design variables being characteristics of the illumination source and the design layout, the computing of the multi-variable cost function accounting for lens heating effects; and reconfiguring the characteristics of the lithographic process by adjusting the design variables until a predefined termination condition is satisfied.

Abstract: Disclosed are methods, systems, and articles of manufacture for processing a electronic design, which use a computer system to identify an operation associated with a task to be performed on the electronic design, to generate a hierarchical output for multiple shapes for performing the task based at least in part on performing an operation associated with the task, and to display or to store the hierarchical output. The task comprises a dummy fill insertion task or a design verification task in some embodiments. The methods or the systems may further determine or identify an inverse transform and apply the inverse transform to a shape before adding the shape to the hierarchical output. In some embodiments, there exists no duplication among the shapes in the hierarchical output, or only shapes derived from original shapes that belong to the first instance of a cellview master are added to the hierarchical output.

Abstract: The present disclosure involves a method of data preparation in lithography processes. The method of data preparation includes providing an integrated circuit (IC) layout design in a graphic database system (GDS) grid, and converting the IC layout design GDS grid to a second exposure grid by applying an error diffusion and a grid shift technique to a sub-pixel exposure grid.

Abstract: A technique for providing information about defects in a mask pattern is described. In this technique, defects in the mask pattern may be determined based on differences between a calculated pattern produced at an image plane in the photolithographic process, when the mask pattern, illuminated by an associated source pattern, is at an object plane in the photolithographic process, and a target pattern that excludes the defects. Then the defect information may be provided to the user, such as a spatial map of the determined defects, where the spatial map is associated with at least the portion of the mask pattern.

Abstract: Described herein is a method for simulating an image formed within a resist layer on a substrate resulting from an incident radiation, the substrate having a first feature and a second feature underlying the resist layer, the method comprising: simulating a first partial image using interaction of the incident radiation and the first feature without using interaction of the incident radiation and the second feature; simulating a second partial image using the interaction of the incident radiation and of the second feature without using the interaction of the incident radiation and the first feature; computing the image formed within the resist layer from the first partial image, and the second partial image; wherein the interaction of the incident radiation and the first feature is different from the interaction of the incident radiation and the second feature.

Abstract: A method of preparing a set of target layout data for the application of a photolithographic friendly design (LFD) analysis or other photolithographic analysis. The target layout data is revised to remove areas or features prior to performing the LFD analysis. The features removed include features that have been determined to print correctly, duplicate features and features that are not sensitive to variations in process conditions. The revised target layout is analyzed to determine if the features that remain will print correctly on a wafer.

Abstract: According to one embodiment, generating virtual data by mirroring data based on a dimension measurement result in a measurement region on an inner side of a shot region to a non-shot region on an outer side of a shot edge, and calculating dose data of the measurement region and a non-measurement region based on data in the measurement region and the virtual data are included.

Abstract: Aspects of the invention relate to hybrid hotspot detection techniques. The hybrid hotspot detection techniques combine machine learning classification, pattern matching and process simulation. A machine learning model, along with false hotspots and false non-hotspots for pattern matching, is determined based on training patterns. The determined machine learning model is then used to classify patterns in a layout design into three categories: preliminary hotspots, preliminary non-hotspots and potential hotspots. Pattern matching is then employed to identify false positives and false negatives in the first two categories. Process simulation is employed to identify boundary hotspots in the last category.

Abstract: Solutions for accounting for photomask deviations in a lithographic process during optical proximity correction verification are disclosed. In one embodiment, a method includes: identifying a wafer control structure in a data set representing one of a first chip or a kerf; biasing the data set representing the first chip in the case that the wafer control structure is in the data set representing the first chip; biasing the data set representing the kerf or a second chip distinct from the first chip, in the case that the wafer control structure is in the data set representing the kerf or the second chip; simulating formation of the wafer control structure; determining whether the simulated wafer control structure complies with a target control structure; and iteratively adjusting an exposure dose condition in the case that the simulated wafer control structure does not comply with the target control structure.

Abstract: A hierarchical schematic design editor displays mask layers for each shape as mask specific colors and alerts a user to mask layer conflicts during the design and editing process. According to an embodiment, mask colors may be assigned at the time the shapes or geometries and cells are placed in a circuit design layout, or when a mask layer condition indicating that two or more shapes should be set to different mask layers is detected. In an embodiment, if the distance between two shapes is less than a predetermined threshold, those shapes may cause a mask layer condition. Shapes may be grouped to facilitate mask layer condition detection and mask layer assignment.

Abstract: After layout design data has been modified using a resolution enhancement process, a repair flow is initiated. This repair flow includes checking a layout design altered by a resolution enhancement process for errors. A repair process is performed to correct detected sub-resolution assist feature errors. The repair process may employ a rule-based sub-resolution assist feature technique, a model-based sub-resolution assist feature technique, an inverse lithography-based sub-resolution assist feature technique, or any combination thereof.

Abstract: A mechanism is provided for optimizing a photolithograph mask. A given target pattern is received. An initial fictitious mask is generated from the given target pattern and an initial value of ?2 is selected where the initial value of ?2 is used to determine a light intensity and a wafer image. The light intensity for each pixel in the initial fictitious mask and the wafer image for each pixel in the initial fictitious mask are then determined. A determination is then made as to whether a convergence has been achieved by comparing the wafer image generated from the fictitious mask to the given target pattern. Responsive to a convergence of the wafer image generated from the fictitious mask to the given target pattern, a final mask is generated to use to transfer an image to a wafer.

Abstract: A library of waivable images with corresponding waiver constraints is generated. Each of the waivable images is an image of a region of a reference design layout including a raw error as determined by an optical rule checks (ORC) program and does not require a correction for printability on a photoresist layer. A list of raw errors is generated by running the ORC program on a target design layout. Error region images corresponding to the list of raw errors are generated by selecting a region of the target design layout around points corresponding to the raw errors. A list of matches between the library of waivable images and the error region images is generated. By removing a subset of raw errors that correspond to a subset of the list of matches from the list of raw errors, a list of real errors is generated.

Abstract: A method includes connecting in a wiring area a plurality of basic block patterns which include a plurality of track patterns extending to one direction and being disposed at a prescribed pitch in an intersection direction intersecting the one direction to generate a plurality of parallel wiring patterns, each of which includes the track patterns connected together; generating a wiring route running on a track pattern; cutting away a track pattern terminal end, on which no wiring route runs, out of track pattern terminal ends of a track pattern including a route end of the wiring route and an adjacent track pattern connected to a track pattern start end of the track pattern concerned; and generating a wiring pattern data including a block pattern identifier corresponding to a basic block pattern out of the basic block patterns in the wiring area and a layout position of the basic block pattern.

Abstract: A mechanism is provided for optimizing a photolithograph mask. A given target pattern is received. An initial fictitious mask is generated from the given target pattern and an initial value of ?2 is selected where the initial value of ?2 is used to determine a light intensity and a wafer image. The light intensity for each pixel in the initial fictitious mask and the wafer image for each pixel in the initial fictitious mask are then determined. A determination is then made as to whether a convergence has been achieved by comparing the wafer image generated from the fictitious mask to the given target pattern. Responsive to a convergence of the wafer image generated from the fictitious mask to the given target pattern, a final mask is generated to use to transfer an image to a wafer.

Abstract: A method of generating a mask having optical proximity correction features.

Abstract: An dual function distance metric for pattern matching based hotspot clustering is described. The dual function distance metric can handle patterns containing multiple polygons, is easy to compute, and is tolerant of small variations or shifts of the shapes. Compared with an XOR distance metric pattern clustering, the dual function distance metric can achieve up to 37.5% accuracy improvement with 2X-4X computational cost in the context of cluster analysis. The dual function distance metric is reliable and accurate for characterizing clips (e.g. hotspots), thereby making it desirable for industry applications.