Code Restructuring Patents (Class 717/159)
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Patent number: 8595284Abstract: In a first embodiment of the present invention, a method is provided comprising: determining if a portion of a script of web application code within a web application is migratable to a remote infrastructure, wherein the portion of the script contains one or more functions; and modifying the portion of the script if the portion of the script is migratable, such that execution of the portion of the script results in the one or more functions being executed on the remote infrastructure, wherein the remote infrastructure is not restricted to the device on which the web application was designed or distributed.Type: GrantFiled: December 14, 2009Date of Patent: November 26, 2013Assignee: Samsung Electronics Co., LtdInventors: Mithun Sheshagiri, Swaroop S. Kalasapur, Onur Aciicmez, Yu Song, Doreen Cheng
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Patent number: 8589884Abstract: The present invention provides a method, system and computer program product for identifying regression test cases for a software application by identifying one or more units of functionalities of the software application, structuring the use case activity diagrams using the identified units of functionalities, modifying the structured use case activity diagrams when there is a change in the software application, and analyzing the modifications made to the structured use case activity diagrams to identify regression test cases for the changes in the software application.Type: GrantFiled: September 27, 2010Date of Patent: November 19, 2013Assignee: Infosys LimitedInventors: Ravi Prakash Gorthi, Kailash Kumar Prasad Chanduka, Benny Leong, Anjaneyulu Pasala
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Patent number: 8589900Abstract: A code region forming part of a computer program is modified during execution of the computer program by a plurality of threads. In one aspect, identical modification instructions are provided to each thread for modifying a site in the code region having a desirable idempotent atomic modification, and the modification instructions direct each thread to make the desirable idempotent atomic modification. In another aspect, a thread is selected to modify the code region, each thread other than the selected thread is directed to execute an alternative execution path that generates output identical to the output of the code region after the code region has been modified, and, responsive to directing each thread other than the selected thread, the selected thread is directed to modify the code region.Type: GrantFiled: August 21, 2007Date of Patent: November 19, 2013Assignee: International Business Machines CorporationInventors: Kevin Alexander Stoodley, Mark Graham Stoodley
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Patent number: 8589897Abstract: Disclosed herein are systems, methods, and computer readable-media for obfuscating code. The method includes extracting a conditional statement from a computer program, creating a function equivalent to the conditional statement, creating a pointer that points to the function, storing the pointer in an array of pointers, replacing the conditional statement with a call to the function using the pointer at an index in the array, and during runtime of the computer program, dynamically calculating the index corresponding to the pointer in the array. In one aspect, a subset of instructions is extracted from a path associated with the conditional statement and the subset of instructions is placed in the function to evaluate the conditional statement. In another aspect, the conditional statement is replaced with a call to a select function that (1) calculates the index into the array, (2) retrieves the function pointer from the array using the index, and (3) calls the function using the function pointer.Type: GrantFiled: August 26, 2008Date of Patent: November 19, 2013Assignee: Apple Inc.Inventors: Gideon M. Myles, Julien Lerouge, Tanya Michelle Lattner, Augustin J. Farrugia
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Patent number: 8584111Abstract: A code region forming part of a computer program is modified during execution of the computer program by a plurality of threads. In one aspect, identical modification instructions are provided to each thread for modifying a site in the code region having a desirable idempotent atomic modification, and the modification instructions direct each thread to make the desirable idempotent atomic modification. In another aspect, a thread is selected to modify the code region, each thread other than the selected thread is directed to execute an alternative execution path that generates output identical to the output of the code region after the code region has been modified, and, responsive to directing each thread other than the selected thread, the selected thread is directed to modify the code region.Type: GrantFiled: August 21, 2007Date of Patent: November 12, 2013Assignee: International Business Machines CorporationInventors: Kevin Alexander Stoodley, Mark Graham Stoodley
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Patent number: 8578357Abstract: In one embodiment of the invention code (e.g., compiler, tool) may generate information so a first code portion, which includes a pointer value in a first endian format (e.g., big endian), can be properly initialized and executed on a platform having a second endian format (e.g., little endian). Also, various embodiments of the invention may identify problematic regions of code (e.g., source code) where a particular byte order is cast away through void pointers.Type: GrantFiled: December 21, 2009Date of Patent: November 5, 2013Assignee: Intel CorporationInventors: Michael P. Rice, Hugh Wilkinson, Maximillian J. Domeika, Evgueni V. Brevnov, Peter Lachner
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Patent number: 8572596Abstract: A code region forming part of a computer program is modified during execution of the computer program by a plurality of threads. In one aspect, identical modification instructions are provided to each thread for modifying a site in the code region having a desirable idempotent atomic modification, and the modification instructions direct each thread to make the desirable idempotent atomic modification. In another aspect, a thread is selected to modify the code region, each thread other than the selected thread is directed to execute an alternative execution path that generates output identical to the output of the code region after the code region has been modified, and, responsive to directing each thread other than the selected thread, the selected thread is directed to modify the code region.Type: GrantFiled: August 21, 2007Date of Patent: October 29, 2013Assignee: International Business Machines CorporationInventors: Kevin Alexander Stoodley, Mark Graham Stoodley
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Patent number: 8561041Abstract: A method, tangible computer-readable medium and apparatus for concurrently executing subsystems in a graphical model is provided. An embodiment can transform a conventional graphical model supporting single threaded execution into a model supporting multi-threaded execution through the replacement of a single block. The transformed model may support concurrent execution of a plurality of subsystems using a plurality of threads when the graphical model executes. An embodiment provides a user interface that allows a user to intuitively configure a model for current execution of the subsystems.Type: GrantFiled: March 12, 2010Date of Patent: October 15, 2013Assignee: The MathWorks, Inc.Inventors: Steve Kuznicki, Chad Van Fleet
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Patent number: 8561045Abstract: Techniques for processing computer code are disclosed. In one example, an indication that a computer code is to begin execution at a portion of code other than a starting portion of the code is received, and a runtime state associated with the portion of the code at which execution is to begin is constructed. In some examples, execution of the portion of code is initiated. In some examples, a program counter associated with the portion of the code is used to initiate execution of the code. In some examples, the computer code comprises a fallback code associated with a previously executing code.Type: GrantFiled: July 30, 2010Date of Patent: October 15, 2013Assignee: Apple Inc.Inventors: Victor Leonel Hernandez Porras, Christopher Arthur Lattner, Jia-Hong Chen, Eric Marshall Christopher, Roger Scott Hoover, Francois Jouaux, Robert John McCall, Thomas John O'Brien, Pratik Solanki
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Patent number: 8554807Abstract: A technique for incrementally unloading classes using a region-based garbage collector is described. One aspect of such a technique includes maintaining a remembered set for a class set. The remembered set indicates whether instances of the class set are contained in one or more regions in memory, and in which regions the instances are contained. Upon performing an incremental garbage collection process for a subset of the regions in memory, the technique examines the remembered set to determine whether the class set includes instances in regions outside of the subset. If the remembered set indicates that the class set includes instances outside of the subset of regions, the technique identifies the class set as “live.” This will preclude unloading the class set from the subset of regions.Type: GrantFiled: March 28, 2012Date of Patent: October 8, 2013Assignee: International Business Machines CorporationInventors: Peter Wiebe Burka, Jeffrey Michael Disher, Daryl James Maier, Aleksandar Micic, Ryan Andrew Sciampacone
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Patent number: 8555267Abstract: A mechanism for performing register allocation based on priority spills and assignments is disclosed. A method of embodiments of the invention includes repetitively detecting fat points during a compilation process of a software program running on a virtual machine of a computer system, each fat point representing a program point having a high register pressure, the high register pressure occurs when a number of live program variables of the software program living at a given program point of the software program is greater than a number of available processor registers of the computer system. The method further includes choosing a fat point with a highest register pressure, selecting a live program variable having a lowest priority at the chosen fat point, and spilling the lowest priority live program variable to memory of the computer system.Type: GrantFiled: March 3, 2010Date of Patent: October 8, 2013Assignee: Red Hat, Inc.Inventor: Vladimir Makarov
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Patent number: 8549507Abstract: A loop coalescing method and a loop coalescing device are disclosed. The loop coalescing method comprises removing an inner-most loop from among nested loops, so that an outer operation provided outside of the inner-most loop is performed when a condition of a conditional statement is satisfied, generating a guard code by applying an if-conversion method to the conditional statement, and converting a guard by using an instruction calculating the guard of the guard code, the instruction calculating the guard using a register where information related to a period of time corresponding to the number of iterations of the inner-most loop is stored.Type: GrantFiled: August 22, 2007Date of Patent: October 1, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Hee Seok Kim, Hong-Seok Kim, Chang-Woo Baek, Jeongwook Kim
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Patent number: 8549503Abstract: Dangling pointers and memory leak locations within software are detected. As the software allocates and deallocates memory, lists of pointers referencing the memory, and pointer status, are maintained. As the software writes new addresses within pointers and reads addresses referenced by the pointers, the pointer lists are maintained to determine whether the pointers are dangling and to detect memory leak locations. A balanced binary tree having a number of nodes can be maintained. The nodes represent heap or stack records. Each heap record corresponds to heap memory that has been allocated and has a list of pointers referencing the heap memory. Each stack record corresponds to a stack within which a stack frame is allocated each time a function is entered. The stack record has frame records corresponding to the stack frames. Each frame record has a list of pointers referencing the corresponding stack frame.Type: GrantFiled: April 17, 2012Date of Patent: October 1, 2013Assignee: International Business Machines CorporationInventor: Satish Chandra Gupta
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Patent number: 8549506Abstract: APIs are provided, that are external to a programming language but that provide functionality that can be plugged into a language compiler. The provided APIs tailor functionality associated with asynchronous programming, iterators or writing symmetric co-routines using a generalized pattern-based approach. Several types of resumable methods are provided in the APIs which can be applied to method bodies written in traditional program code. Syntactically distinguishable control points in method bodies written in traditional program code invoke transformation of the code by the compiler using the external APIs. The transformed code enables the pausing and resumption of the code sandwiched between control points in the transformed code. The source code contained within a method having control points in it is transformed so that code within the method can be executed in discrete parts, each part starting and ending at a control point in the transformed code.Type: GrantFiled: April 27, 2010Date of Patent: October 1, 2013Assignee: Microsoft CorporationInventors: Henricus Johannes Maria Meijer, Mads Torgersen, Neal M. Gafter, Niklas Gustafsson
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Patent number: 8539467Abstract: Embodiments relate to solving conflicts in assembler programs. An aspect includes generating an internal representation of the control flow of the source code of the assembler program, the internal representation including nodes for every instruction and a directed edge for every possible flow of control between nodes. Data attributes are attributed to the nodes and/or the edges to store the information about whether the resource used by an instruction is available or for which amount of time is unavailable. A data-flow analysis is the applied to the internal representation of the control flow of the source code to determine whether the resource used by an instruction of the assembler program is available or for which amount of time is unavailable. Each node is checked for whether the instruction accesses a resource which is unavailable. An appropriate action is then taken to overcome the resource conflict.Type: GrantFiled: March 14, 2007Date of Patent: September 17, 2013Assignee: International Business Machines CorporationInventor: Wolfgang Gellerich
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Patent number: 8539458Abstract: The present invention extends to methods, systems, and computer program products for changing addressing mode during code generation. Generally, embodiments of the invention use a compiler transformation to transform lower level code from one address alignment to another address alignment. The transformation can be based upon assumptions of a source programming language. Based on the assumptions, the transformation can eliminate arithmetic operations that compensate for different addressing alignment, resulting in more efficient code. Some particular embodiments use a compiler transformation to transform an Intermediate Representation (“IR”) from one-byte addressing alignment into multi-byte (e.g., four-byte) addressing alignment.Type: GrantFiled: June 10, 2011Date of Patent: September 17, 2013Assignee: Microsoft CorporationInventors: Weirong Zhu, Yosseff Levanoni
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Patent number: 8533665Abstract: A computer-implemented method is disclosed for generating Dojo-conforming JavaScript Object Notation (JSON) objects for base objects of an object-oriented programming environment that have been annotated to denote which attribute declarations of the base object correspond to identified Dojo attributes. In a Java class, for example, annotations may be made to indicate which class attributes correspond to the identifier attribute of a Dojo JSON object and based on those annotations a Dojo-conforming JSON object may be generated.Type: GrantFiled: November 16, 2009Date of Patent: September 10, 2013Assignee: Cisco Technology, Inc.Inventors: Limin Yu, Inderpreet Bhullar, Mukesh Garg
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Patent number: 8527971Abstract: A method for compiling a source code into a parallel executable form, in which the execution order of the executable is partially undefined. During the compilation process a partial execution order is first defined for instructions having ordering constraints related to the source code level. The partial execution order is then completed with architecture related ordering constraints in order to produce an executable code.Type: GrantFiled: March 30, 2006Date of Patent: September 3, 2013Assignee: Atostek OyInventor: Juhana Helovuo
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Patent number: 8516229Abstract: A test code generation technique that replaces instructions having a machine state dependent result with special redirection instructions provides generation of test code in which state dependent execution choices are made without a state model. Redirection instructions cause execution of a handler than examines the machine state and replaces the redirection instruction with a replacement instruction having a desired result resolved in accordance with the current machine state. The instructions that are replaced may be conditional branch instructions and the result a desired execution path. The examination of the machine state permits determination of a branch condition for the replacement instruction so that the next pass of the test code executes along the desired path. Alternatively, the handler can execute a jump to the branch instruction, causing immediate execution of the desired branch path.Type: GrantFiled: February 5, 2010Date of Patent: August 20, 2013Assignee: International Business Machines CorporationInventors: Allon Adir, Brad Lee Herold, John Martin Ludden, Pedro Martin-de-Nicolas, Charles Leverett Meissner, Gil Eliezer Shurek
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Patent number: 8516463Abstract: A mechanism for allocating statement frontier annotations to source code statements of a software program is disclosed. A method of embodiments of the invention includes generating statement frontier annotations during translation of source code statements of a software program on a computer system. The method further includes allocating the statement frontier annotations to the source code statements, wherein a statement frontier annotation indicates a frontier of a source code statement to which the statement frontier annotation is allocated.Type: GrantFiled: May 28, 2010Date of Patent: August 20, 2013Assignee: Red Hat, Inc.Inventor: Alexandre Oliva
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Patent number: 8510723Abstract: A binary rewriter that can provide complete code coverage without relocation information is provided, together with a method of performing such rewriting. The method can include processing a binary file as an original binary file. The method can also include disassembling the binary file to provide a disassembled binary file. The method can further include rewriting the disassembled binary file without relocation information to provide a rewritten binary file. The rewriting can provide a physical transformation in a recording medium relative to the binary file in the recording medium prior to the rewriting. The processing the binary file, disassembling the binary file, and rewriting the disassembled binary file can be performed by a particular machine.Type: GrantFiled: May 24, 2010Date of Patent: August 13, 2013Assignee: University of MarylandInventors: Rajeev Kumar Barua, Matthew Smithson
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Patent number: 8495605Abstract: A method for policy-based program optimization of existing software code is performed where the code is segmented into code modules. The optimization is based on a performance policy that defines a target characteristic and a sacrificial characteristic relating to the existing software code and further defines an allowable degradation of the sacrificial characteristic resulting from optimization of the target characteristic. This method may include identifying code modules that contribute to suboptimal performance of the software code with respect to the target characteristic; identifying code transformations that increase performance of the suboptimal code modules with respect to the target characteristic; and optimizing the identified code modules by selectively applying the code transformations in accordance with the performance policy to increase performance of the software code with respect to the target characteristic.Type: GrantFiled: June 16, 2008Date of Patent: July 23, 2013Assignee: International Business Machines CorporationInventors: Neeraj Joshi, David L. Kaminsky
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Patent number: 8489653Abstract: A technique for incrementally unloading classes using a region-based garbage collector is described. One aspect of such a technique includes maintaining a remembered set for a class set. The remembered set indicates whether instances of the class set are contained in one or more regions in memory, and in which regions the instances are contained. Upon performing an incremental garbage collection process for a subset of the regions in memory, the technique examines the remembered set to determine whether the class set includes instances in regions outside of the subset. If the remembered set indicates that the class set includes instances outside of the subset of regions, the technique identifies the class set as “live.” This will preclude unloading the class set from the subset of regions.Type: GrantFiled: February 8, 2011Date of Patent: July 16, 2013Assignee: International Business Machines CorporationInventors: Peter Wiebe Burka, Jeffrey Michael Disher, Daryl James Maier, Aleksandar Micic, Ryan Andrew Sciampacone
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Patent number: 8479180Abstract: Disclosed is a system and method for maintaining software instructions stored in a wireless communications device memory. The software is organized using code sections, where each code section is in a contiguous portion of memory and relocatable independently of other code sections. Maintenance includes the ability to run a unique software component called a compactor while the normal system is not in executable form. The compactor expands, compresses, and relocates code sections to allow downloaded code to be incorporated into the system code base.Type: GrantFiled: October 23, 2006Date of Patent: July 2, 2013Assignee: KYOCERA CorporationInventors: Gowri Rajaram, Diego Kaplan
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Patent number: 8479183Abstract: In one embodiment, the present invention includes a method for emitting a live range statement into a program for a memory variable to be cached during run-time that has at least one simulation state variable if the memory variable is dynamically mapped, and defining the simulation state variable at a first execution path of the program. In such manner, the program may be optimized using the live range statement and the simulation state variable. Also, a debugger may use the simulation state variables in obtaining and displaying the memory variable from a cache.Type: GrantFiled: October 22, 2009Date of Patent: July 2, 2013Assignee: Marvell World Trade Ltd.Inventors: Cheng-Hsueh A. Hsieh, Lei Jin, Liping Gao
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Patent number: 8479179Abstract: A method for compiling a program including a loop is provided. In the program, the loop includes K instructions (K>2) and repeats for M times (M>2). The compiling method comprises following steps: performing resource conflict analysis to the K instructions in the loop; dividing the K instructions in the loop into a first combined instruction section, a connection instruction section and a second combined instruction section, wherein there is no resource conflict between the instructions in the first combined instruction section and the instructions in the second combined instruction section respectively; and compiling the program, wherein the instructions in the first combined instruction section in the cycle N (N=2, 3, . . . M) and the instructions in the second combined instruction section in the cycle N?1 are combined to be compiled respectively. A compiling apparatus and a computer system for realizing the above-mentioned compiling method are further provided.Type: GrantFiled: December 7, 2005Date of Patent: July 2, 2013Assignee: St-Ericsson SAInventors: Fan Wu, Yanmeng Sun
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Patent number: 8473935Abstract: Pre-compiling postdominating functions. Some embodiments may be practiced in a computing environment including a runtime compilation. For example one method includes acts for compiling functions. The method includes determining that a function of an application has been called. A control flow graph is used to determine one or more postdominance relationships between the function and one or more other functions. The one or more other functions are assigned to be pre-compiled based on the postdominance relationship.Type: GrantFiled: April 21, 2008Date of Patent: June 25, 2013Assignee: Microsoft CorporationInventor: Matthew B. Grice
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Patent number: 8468508Abstract: An optimizing compiler device, a method, a computer program product which are capable of performing parallelization of irregular reductions. The method for performing parallelization of irregular reductions includes receiving, at a compiler, a program and selecting, at compile time, at least one unit of work (UW) from the program, each UW configured to operate on at least one reduction operation, where at least one reduction operation in the UW operates on a reduction variable whose address is determinable when running the program at a run-time. At run time, for each successive current UW, a list of reduction operations accessed by that unit of work is recorded. Further, it is determined at run time whether reduction operations accessed by a current UW conflict with any reduction operations recorded as having been accessed by prior selected units of work, and assigning the unit of work as a conflict free unit of work (CFUW) when no conflicts are found.Type: GrantFiled: October 9, 2009Date of Patent: June 18, 2013Assignee: International Business Machines CorporationInventors: Alexandre E. Eichenberger, Yangchun Luo, John K. O'Brien, Xiaotong Zhuang
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Patent number: 8464208Abstract: Systems and methods are described for capturing and utilizing specific module dependency information. A hierarchical model can be created to arrange the components an existing software system in a particular hierarchy. The model defines a priority of dependencies among the components. A tool is provided for analyzing each class file of the system for references to other class files and determining, for each said class file, whether each reference is acceptable according to the hierarchical model. Once the class files and references have been analyzed, a surrogate class file can be automatically generated for the references that are determined to be unacceptable according to the hierarchical model. This process can utilize white lists and black lists associated with the class files, where the white lists specify modules to which references are acceptable and the black lists specify modules to which references are unacceptable.Type: GrantFiled: March 26, 2010Date of Patent: June 11, 2013Assignee: Oracle International CorporationInventor: Lawrence Feigen
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Patent number: 8464237Abstract: One embodiment of the present invention provides a system for compiling a computer program. During operation, the system receives one or more source code files associated with a computer program at a compiler. Next, the system starts a linker which links object files into an executable program. The system then compiles the one or more source code files into one or more object files. Upon creating each object file, the system sends the object file to the linker without waiting to create the remaining object files.Type: GrantFiled: February 27, 2008Date of Patent: June 11, 2013Assignee: Google Inc.Inventor: Ian Lance Taylor
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Patent number: 8458683Abstract: A system and method are provided in which an enumerated type is extendable. In an embodiment, additional attributes are assigned to instances of a class, thus extending the enumerated type. The addition of values to an enumeration may depend upon the surrounding system environment and/or the calling application.Type: GrantFiled: October 10, 2008Date of Patent: June 4, 2013Assignee: SAP AGInventor: Efstratios Tsantilis
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Patent number: 8458684Abstract: Mechanisms are provided for inserting indicated instructions for tracking and indicating exceptions in the execution of vectorized code. A portion of first code is received for compilation. The portion of first code is analyzed to identify non-speculative instructions performing designated non-speculative operations in the first code that are candidates for replacement by replacement operation-and-indicate instructions that perform the designated non-speculative operations and further perform an indication operation for indicating any exception conditions corresponding to special exception values present in vector register inputs to the replacement operation-and-indicate instructions. The replacement is performed and second code is generated based on the replacement of the at least one non-speculative instruction.Type: GrantFiled: August 19, 2009Date of Patent: June 4, 2013Assignee: International Business Machines CorporationInventors: Alexandre E. Eichenberger, Alan Gara, Michael K. Gschwind
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Publication number: 20130139136Abstract: A computer-implemented method for removing redundant function calls in a computer program includes identifying a first set of equivalent function calls appearing in the computer program. For each of the equivalent function calls, the method identifies whether the function call is partially available or partially anticipable. When a function call is identified as being partially anticipable, a result of the function call is stored in a temporary variable. When a function call is identified as being partially available, the function call is removed and replaced with use of the temporary variable.Type: ApplicationFiled: November 29, 2011Publication date: May 30, 2013Applicant: Microsoft CorporationInventors: Patrick W. Sathyanathan, Ten Tzen
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Patent number: 8453135Abstract: A compiler selects a nested loop within software code that includes an outer loop and an inner loop. The outer loop includes an outer induction variable and the inner loop includes an inner induction variable. The compiler identifies a computation included in the nested loop that generates an irregular array access, which includes an expression of both the outer induction variable and the inner induction variable. Next, the compiler identifies a redundant calculation for the computation based upon the outer induction variable and the inner induction variable, and generates a temporary variable to correspond with the redundant calculation. The compiler replaces the computation with the temporary variable in the nested loop and, in turn, compiles the nested loop with the included temporary variable.Type: GrantFiled: March 11, 2010Date of Patent: May 28, 2013Assignee: Freescale Semiconductor, Inc.Inventor: Abderrazek Zaafrani
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Patent number: 8453133Abstract: A method for arithmetic expression optimization comprises validating at least one input stack associated with a first instruction operable on at least one operand of a first type and optimizing the first instruction to a second instruction operable on at least one operand of a second type that is smaller than the first type based at least in part on the relative size of the first type and the second type. The method also comprises matching the second type with an operand type of at least one operand in the at least one input stack associated with the second instruction. The matching comprises changing the type of instructions in a chain of instructions to equal the second type if the operand type is less than the second type. The chain is bounded by the second instruction and a third instruction that is the source of the at least one operand.Type: GrantFiled: November 12, 2003Date of Patent: May 28, 2013Assignee: Oracle America, Inc.Inventors: Judith Schwabe, Zhiqun Chen
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Patent number: 8448157Abstract: One embodiment of a method for eliminating redundant operations establishing common properties includes identifying a first virtual register storing a first value having a common property. The method may assign the first virtual register to use a real register. The method may further identify a second virtual register storing a second value also having the common property. The method may assign the second virtual register to use the same real register after the first value is no longer live. As a result of assigning the second virtual register to the first real register, the method may eliminate an operation configured to establish the common property for the second virtual register since this operation is redundant and is no longer needed.Type: GrantFiled: October 26, 2010Date of Patent: May 21, 2013Assignee: International Business Machines CorporationInventors: Marcel Mitran, Kishor V. Patil, Joran S. C. Siu, Mark G. Stoodley, Vijay Sundaresan
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Patent number: 8443351Abstract: The subject disclosure pertains broadly to parallelization of workflow loops. More specifically, loop containers and related elements are cloned several times to match a desired number of parallel iterations or threads. The cloned containers are communicatively coupled or connected to a single enumerator component and can interact therewith to facilitate acquisition of collection elements. This arrangement, among other things, ensures that the correct number of iterations are executed as if the loop was processed sequentially.Type: GrantFiled: February 23, 2006Date of Patent: May 14, 2013Assignee: Microsoft CorporationInventors: J. Kirk Haselden, Sergei Ivanov
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Patent number: 8443349Abstract: A runtime system implemented in accordance with the present invention provides an application platform for parallel-processing computer systems. Such a runtime system enables users to leverage the computational power of parallel-processing computer systems to accelerate/optimize numeric and array-intensive computations in their application programs. This enables greatly increased performance of high-performance computing (HPC) applications.Type: GrantFiled: February 9, 2012Date of Patent: May 14, 2013Assignee: Google Inc.Inventors: Matthew N. Papakipos, Brian K. Grant, Morgan S. McGuire, Christopher G. Demetriou
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Patent number: 8429637Abstract: Disclosed herein are systems, methods, and computer readable-media for obfuscating code through conditional expansion obfuscation. The method includes identifying a conditional expression in a computer program, identifying a sequence of conditional expressions that is semantically equivalent to the conditional expression, and replacing the conditional expression with the semantically equivalent sequence of conditional expressions. One option replaces each like conditional expression in the computer program with a diverse set of sequences of semantically equivalent conditional expressions. A second option rearranges computer instructions that are to be processed after the sequence of conditional expression is evaluated so that a portion of the instructions is performed before the entire sequence of conditional expressions is evaluated. A third option performs conditional expansion obfuscation of a conditional statement in combination with branch extraction obfuscation.Type: GrantFiled: September 2, 2008Date of Patent: April 23, 2013Assignee: Apple Inc.Inventors: Gideon M. Myles, Tanya Michelle Lattner, Julien Lerouge, Augustin J. Farrugia
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Patent number: 8429623Abstract: A mechanism is disclosed for enabling a set of code intended to be executed on a first platform (intended platform) to be executed on another platform (target platform). In one implementation, this mechanism takes a significantly different approach than that taken by current techniques. Rather than duplicating, augmenting, or changing a platform to accommodate the set of code, this mechanism alters the set of code to accommodate the platform. By altering the set of code, the mechanism causes the set of code to compensate for the difference(s) between the intended platform and the target platform. By compensating for the difference(s) in the two platforms, the set of code, when executed on the target platform, is able to produce the same result or results as it would have produced had it been executed on the intended platform. Thus, the set of code is able to execute properly on the target platform.Type: GrantFiled: January 16, 2007Date of Patent: April 23, 2013Assignee: Oracle America Inc.Inventors: Kenneth B. Russell, Ira A. Wyant
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Patent number: 8423960Abstract: A method for software processing in which software locations are assigned priorities indicative of respective likelihoods that the locations contain program faults, based on review information pertaining to reviews that have been conducted on respective locations in software code. In some methods, a software location is detected to be critical based on the priorities.Type: GrantFiled: March 31, 2008Date of Patent: April 16, 2013Assignee: International Business Machines CorporationInventors: Eitan Daniel Farchi, Sergey Novikov, Orna Raz-Pelleg
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Patent number: 8418157Abstract: A compiler comprises an analysis unit that detects directives (options and pragmas) from a user to the compiler, an optimization unit that is made up of a processing unit (a global region allocation unit, a software pipelining unit, a loop unrolling unit, a “if” conversion unit, and a pair instruction generation unit) that performs individual optimization processing designated by options and pragmas from a user, following the directives and the like from the analysis unit, etc. The global region allocation unit performs optimization processing, following designation of the maximum data size of variables to be allocated to a global region, designation of variables to be allocated to the global region, and options and pragmas regarding designation of variables not to be allocated in the global region.Type: GrantFiled: February 16, 2010Date of Patent: April 9, 2013Assignee: Panasonic CorporationInventors: Hajime Ogawa, Taketo Heishi, Toshiyuki Sakata, Shuichi Takayama, Shohei Michimoto, Tomoo Hamada, Ryoko Miyachi
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Patent number: 8418156Abstract: Generally, the present disclosure provides systems and methods to generate a two-stage commit (TSC) region which has two separate commit stages. Frequently executed code may be identified and combined for the TSC region. Binary optimization operations may be performed on the TSC region to enable the code to run more efficiently by, for example, reordering load and store instructions. In the first stage, load operations in the region may be committed atomically and in the second stage, store operations in the region may be committed atomically.Type: GrantFiled: December 16, 2009Date of Patent: April 9, 2013Assignee: Intel CorporationInventors: Cheng Wang, Youfeng Wu
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Patent number: 8418155Abstract: Techniques are disclosed for automating the generation of parallel SIMD native source code in three major functional areas of data transmission, synchronization, and SIMD operations. An annotation standard is defined that is independent from native compilers and, coupled with a source-to-source compiler that provides high-level abstractions of data transmission, synchronization, and SIMD operations, relieves the need for programmers to work in a hardware-specific manner, while addressing issues of productivity and portability in a parallel SIMD computing environment.Type: GrantFiled: February 10, 2009Date of Patent: April 9, 2013Assignee: International Business Machines CorporationInventors: Jeffrey S. McAllister, Nelson Ramirez
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Patent number: 8418160Abstract: A method to selectively remove memoizing functions from computer program code includes initially locating a memoizing function call in the program code. The method then replaces the memoizing function call with a simple object allocation. Using escape analysis, the method determines whether the replacement is legal. If the replacement is not legal, the method removes the simple object allocation and reinserts the original memoizing function call in its place. If the replacement is legal, the method retains the simple object allocation in the program code. If desired, certain compiler optimizations, such as stack allocation and scalarization, may then be performed on the simple object allocation. A corresponding computer program product and apparatus are also disclosed.Type: GrantFiled: October 13, 2010Date of Patent: April 9, 2013Assignee: International Business Machines CorporationInventor: Patrick R. Doyle
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Patent number: 8402447Abstract: Various technologies and techniques are disclosed for transforming a sequential loop into a parallel loop for use with a transactional memory system. Open ended and/or closed ended sequential loops can be transformed to parallel loops. For example, a section of code containing an original sequential loop is analyzed to determine a fixed number of iterations for the original sequential loop. The original sequential loop is transformed into a parallel loop that can generate transactions in an amount up to the fixed number of iterations. As another example, an open ended sequential loop can be transformed into a parallel loop that generates a separate transaction containing a respective work item for each iteration of a speculation pipeline. The parallel loop is then executed using the transactional memory system, with at least some of the separate transactions being executed on different threads.Type: GrantFiled: July 25, 2011Date of Patent: March 19, 2013Assignee: Microsoft CorporationInventors: John Joseph Duffy, Jan Gray, Yosseff Levanoni
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Patent number: 8396764Abstract: Methods and apparatus, including computer systems and program products, for transmitting mobile device data are described. A method includes querying a first mobile device for data residing on the first mobile device; wirelessly transmitting, to a computer system, a specification of the data residing on the first mobile device; determining suitability of data for a second mobile device; and receiving, at the second mobile device, a specification of data for the second mobile device that is based on the specification of the data residing on the first mobile device. Another method includes wirelessly receiving, at a computer system, a specification of data residing on the first mobile device; and wirelessly transmitting, to the second mobile device, a specification of data for the second mobile device that is based on the specification of the data residing on the first mobile device.Type: GrantFiled: August 23, 2010Date of Patent: March 12, 2013Assignee: Single Touch Interactive, Inc.Inventor: Anthony G. Macaluso
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Patent number: 8392900Abstract: Systems and methods according to the present invention provide techniques which modify programs having barrier statements. Dependence relations between statements, and enforcement associations between the barrier statements and the dependence relations, in the program are identified. The dependence relations are classified as being either enforceable by point-to-point synchronization or not enforceable by point-to-point synchronization. A subset of the barrier statements, which will enforce those dependence relations that are unenforceable by point-to-point synchronization, are determined. Other(s) of the barrier statements are replaced with a point-to-point synchronization routine.Type: GrantFiled: March 17, 2005Date of Patent: March 5, 2013Assignee: Hewlett-Packard Development Company, L.P.Inventors: Jean-Francois Collard, Robert Schreiber
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Patent number: 8387035Abstract: A scheduling algorithm is provided for selecting the placement of instructions with internal slack into a schedule of instructions within a loop. The algorithm achieves this by pinning nodes with internal slack to corresponding nodes on the critical path of the code that have similar properties in terms of the data dependency graph, such as earliest time and latest time. The effect is that nodes with internal slack are more often optimally placed in the schedule, reducing the need for rotating registers or register copy instructions. The benefit of the present invention can primarily be seen when performing instruction scheduling or software pipelining on loop code, but can also apply to other forms of instruction scheduling when greater control of placement of nodes with internal slack is desired.Type: GrantFiled: January 13, 2009Date of Patent: February 26, 2013Assignee: International Business Machines CorporationInventor: Allan Russell Martin
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Patent number: 8387065Abstract: A method and a data processing system by which population count (popcount) operations are efficiently performed without incurring the latency and loss of critical processing cycles and bandwidth of real time processing. The method comprises: identifying data to be stored to memory for which a popcount may need to be determined; speculatively performing a popcount operation on the data as a background process of the processor while the data is being stored to memory; storing the data to a first memory location; and storing a value of the popcount generated by the popcount operation within a second memory location. The method further comprises: determining a size of data; determining a granular level at which the popcount operation on the data will be performed; and reserving a size of said second memory location that is sufficiently large to hold the value of the popcount.Type: GrantFiled: April 16, 2009Date of Patent: February 26, 2013Assignee: International Business Machines CorporationInventors: Ravi K. Arimilli, Ronald N. Kalla, Balaram Sinharoy