Abstract: An integrated circuit is formed by identifying multiple regions, each having transistors that have a gate oxide thickness that differs between the multiple regions. One of the regions includes transistors having a nanocluster layer and another of the regions includes transistors with a thin gate oxide used for logic functions. Formation of the gate oxides of the transistors is sequenced based upon the gate oxide thickness and function of the transistors. Thin gate oxides for at least one region of transistors are formed after the formation of gate oxides for the region including the transistors having the nanocluster layer.

Abstract: A semiconductor device, which is arranged in a semiconductor body (1), and which comprises at least one source region (4) and at least one drain region (5), each being of the first conductivity type, and at least one body (8) of the second conductivity type, arranged between source region (4) and drain region (5), and at least one gate electrode (10) which is isolated with respect to the semiconductor body (1) via an isolation layer (9). Said isolation layer (9) comprises polarizable particles, which are composed of a nanoparticulate isolating core and a sheath of polarizable anions or polarizable cations. The isolation layer (9) exhibits a high dielectric constant ?.

Abstract: A memory charge storage device has regions of sacrificial material overlying a substrate (12). For each memory cell a first doped region (20) and a second doped region (24) are formed within the substrate and on opposite sides of one (16) of the regions of sacrificial material. A discrete charge storage layer (28) overlies the substrate and is between the regions of sacrificial material. In one form a control electrode (34) is formed per memory cell overlying the substrate with an underlying substrate diffusion and laterally adjacent one of the regions of sacrificial material. A third substrate diffusion (60) is positioned between the two control electrodes. In another form two control electrodes are formed per memory cell with a substrate diffusion underlying each control electrode. In both forms a select electrode (64) overlies and is between both of the two control electrodes.

Abstract: The device implements nanotechnology by embedding nanocircuits with sensors to surfaces such as walls, wall coverings, clothing, windows, window coverings, flooring, roofs, roadways and telephone poles. Using a plurality of nanocircuits in a multitude of locations, events can be continuously detected and recorded without intrusion, and reconstructed at a later time.

Abstract: Systems and methodologies are provided for temperature compensation of thin film diode voltage levels in memory sensing circuits. The subject invention includes a temperature sensitive bias circuit and an array core with a temperature variable select device. The array core can consist of a thin film diode in series with a nanoscale resistive memory cell. The temperature sensitive bias circuit can include a thin film diode in series with two resistors, and provides a temperature compensating bias voltage to the array core. The thin film diode of the temperature sensitive bias circuit tracks the diode of the array core, while the two resistors create a resistive ratio to mimic the effect of temperature and/or process variation(s) on the array core. The compensating bias reference voltage is generated by the temperature sensitive bias circuit, duplicated by a differential amplifier, and utilized to maintain a constant operation voltage level on the nanoscale resistive memory cell.

Abstract: A layer of nanocrystals for use in making EEPROMs is made by creating a matrix of silicon seeds in annealed silicon oxide atop a thin silicon dioxide layer. Then nanocrystals are grown on the seeds by vapor deposition of silane in a reactor until a time before agglomeration occurs as silicon atoms crystallize on the silicon seeds to form a layer of non-contacting nanocrystals. A protective insulative layer is then deposited over the nanocrystal layer.

Abstract: A nanowire includes a single crystalline semiconductor material having an exterior surface and an interior region and at least one dopant atom. At least a portion of the nanowire thermally switches between two conductance states; a high conductance state, where a high fraction of the dopant atoms is in the interior region, and a low conductance state, where a lower fraction of the dopant atoms is at the interior region and a higher fraction of the atoms is at the exterior surface.