Information Storage Or Retrieval Using Nanostructure Patents (Class 977/943)
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Publication number: 20110149637Abstract: A data storage device and methods for storing and reading data are provided. The data storage device includes a data storage medium and second device. The data storage medium has an insulating layer, a first electrode layer over the insulating layer and at least one layer of resistance variable material over the first electrode layer. The second device includes a substrate and at least one conductive point configured to electrically contact the data storage medium.Type: ApplicationFiled: July 16, 2010Publication date: June 23, 2011Inventors: Jun Liu, Mike Violette, Gurtej Sandhu
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Publication number: 20110141813Abstract: Memory devices and methods of operating memory devices are provided, such as those that involve a memory architecture that replaces typical static and/or dynamic components with emerging non-volatile memory (NV) elements. The emerging NV memory elements can replace conventional latches, can serve as a high speed interface between a flash memory array and external devices and can also be used as high performance cache memory for a flash memory array.Type: ApplicationFiled: February 22, 2011Publication date: June 16, 2011Inventor: Ramin Ghodsi
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Publication number: 20110133268Abstract: Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.Type: ApplicationFiled: February 10, 2011Publication date: June 9, 2011Applicant: MICRON TECHNOLOGY, INC.Inventors: Kyu S. Min, Rhett T. Brewer, Tejas Krishnamohan, Thomas M. Graettinger, D.V. Nirmal Ramaswamy, Ronald A. Weimer, Arup Bhattacharyya
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Publication number: 20110134691Abstract: A multi-functional and multi-level memory cell comprises a tunnel layer formed over a substrate. In one embodiment, the tunnel layer comprises two layers such as HfO2 and LaAlO3. A charge blocking layer is formed over the tunnel layer. In one embodiment, this layer is formed from HfSiON. A control gate is formed over the charge blocking layer. A discrete trapping layer is embedded in either the tunnel layer or the charge blocking layer, depending on the desired level of non-volatility. The closer the discrete trapping layer is formed to the substrate/insulator interface, the lower the non-volatility of the device. The discrete trapping layer is formed from nano-crystals having a uniform size and distribution.Type: ApplicationFiled: February 15, 2011Publication date: June 9, 2011Inventor: Arup Bhattacharyya
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Publication number: 20110122686Abstract: A configuration bit array including a hybrid electromechanical and semiconductor memory cell, and circuitry for addressing and controlling read, write, and erase accesses of the memory.Type: ApplicationFiled: December 21, 2010Publication date: May 26, 2011Applicant: AGATE LOGIC, INC.Inventors: David Richard Trossen, Malcolm John Wing
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Patent number: 7948054Abstract: A two terminal memory device includes first and second conductive terminals and a nanotube article. The article has at least one nanotube, and overlaps at least a portion of each of the first and second terminals. The device also includes stimulus circuitry in electrical communication with at least one of the first and second terminals. The circuit is capable of applying first and second electrical stimuli to at least one of the first and second terminal(s) to change the relative resistance of the device between the first and second terminals between a relatively high resistance and a relatively low resistance. The relatively high resistance between the first and second terminals corresponds to a first state of the device, and the relatively low resistance between the first and second terminals corresponds to a second state of the device.Type: GrantFiled: August 23, 2010Date of Patent: May 24, 2011Assignee: Nantero, Inc.Inventors: Claude L. Bertin, Mitchell Meinhold, Steven L. Konsek, Thomas Rueckes, Max Strasburg, Frank Guo, X. M. Henry Huang, Ramesh Sivarajan
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Patent number: 7944735Abstract: Random access memory including nanotube switching elements. A memory cell includes first and second nanotube switching elements and an electronic memory. Each nanotube switching element includes conductive terminals, a nanotube article and control circuitry capable of controllably form and unform an electrically conductive channel between the conductive terminals. The electronic memory is a volatile storage device capable of storing a logic state in response to electrical stimulus. In certain embodiment the electronic memory has cross-coupled first and second inverters in electrical communication with the first and second nanotube switching elements. The cell can operate as a normal electronic memory, or can operate in a shadow memory or store mode (e.g., when power is interrupted) to transfer the electronic memory state to the nanotube switching elements. The device may later be operated in a recall mode where the state of the nanotube switching elements may be transferred to the electronic memory.Type: GrantFiled: August 31, 2009Date of Patent: May 17, 2011Assignee: Nantero, Inc.Inventors: Claude L. Bertin, Thomas Rueckes, Brent M. Segal
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Patent number: 7940557Abstract: A configuration bit array including a hybrid electromechanical and semiconductor memory cell, and circuitry for addressing and controlling read, write, and erase accesses of the memory.Type: GrantFiled: December 21, 2010Date of Patent: May 10, 2011Assignee: Agate Logic, Inc.Inventors: David Richard Trossen, Malcolm John Wing
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Publication number: 20110095257Abstract: Memory cells, and methods of forming such memory cells, are provided that include a steering element coupled to a carbon-based reversible resistivity switching material that has an increased resistivity, and a switching current that is less than a maximum current capability of the steering element used to control current flow through the carbon-based reversible resistivity switching material. In particular embodiments, methods and apparatus in accordance with this invention form a steering element, such as a diode, having a first width, coupled to a reversible resistivity switching material, such as aC, having a second width smaller than the first width.Type: ApplicationFiled: July 13, 2010Publication date: April 28, 2011Inventors: Huiwen Xu, Er-Xuan Ping, Xiying Costa
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Patent number: 7932549Abstract: A trench-type storage device includes a trench in a substrate (100), with bundles of carbon nanotubes (202) lining the trench and a trench conductor (300) filling the trench. A trench dielectric (200) may be formed between the carbon nanotubes and the sidewall of the trench. The bundles of carbon nanotubes form an open cylinder structure lining the trench. The device is formed by providing a carbon nanotube catalyst structure on the substrate and patterning the trench in the substrate; the carbon nanotubes are then grown down into the trench to line the trench with the carbon nanotube bundles, after which the trench is filled with the trench conductor.Type: GrantFiled: December 18, 2003Date of Patent: April 26, 2011Assignee: International Business Machines CorporationInventors: Steven J. Holmes, Toshiharu Furukawa, Mark C. Hakey, David V. Horak, Charles W. Koburger, III, Larry A. Nesbit
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Patent number: 7932189Abstract: An electronic device can include a layer of discontinuous storage elements. A dielectric layer overlying the discontinuous storage elements can be substantially hydrogen-free. A process of forming the electronic device can include forming a layer including silicon over the discontinuous storage elements. In one embodiment, the process includes oxidizing at least substantially all of the layer. In another embodiment, the process includes forming the layer using a substantially hydrogen-free silicon precursor material and oxidizing at least substantially all of the layer.Type: GrantFiled: January 26, 2007Date of Patent: April 26, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Tushar P. Merchant, Chun-Li Liu, Ramachandran Muralidhar, Marius K. Orlowski, Rajesh A. Rao, Matthew Stoker
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Publication number: 20110089241Abstract: Populations of quantum dots are combined with quantities of a modulator of photoluminescence to produce a plurality of optical barcodes having at least two distinguishable colors arising from varying quantities of a modulator of photoluminescence bound to the populations of quantum dots.Type: ApplicationFiled: October 19, 2010Publication date: April 21, 2011Applicant: THE GOVERNMENT OF THE UNITED STATES OF AMERICA, AS REPRESENTED BY THE SECRETARY OF THE NAVYInventors: Igor L. Medintz, Dorothy Farrell, Hedi M. Mattoussi
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Publication number: 20110090731Abstract: The present disclosure provides a green transistor for nano-Si Ferro-electric random access memory (FeRAM) and method of operating the same. The nano-Si FeRAM includes a plurality of memory cells arranged in an array with bit-lines and word-lines, and each memory cell includes a MOSFET including a gate, a source, a drain, a substrate, and a data storage element formed on the drain spacer of the gate and made of nano-Si in porous SiO2; a word-line connected to the gate; a first bit-line connected to the drain; a second bit-line connected to the source; and an substrate bias supply connected to the substrate, and the gate induced drain leakage current of the MOSFET serves as the read current of the memory cell.Type: ApplicationFiled: August 27, 2010Publication date: April 21, 2011Applicant: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Min-hwa Chi, Deyuan Xiao
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Publication number: 20110084328Abstract: A method for making a non-volatile memory device provides a semiconductor substrate including a surface region and a tunnel dielectric layer overlying the surface region. Preferably the tunnel dielectric layer is a high-K dielectric, characterized by a dielectric constant higher than 3.9. The method forms a source region within a first portion and a drain region within a second portion of the semiconductor substrate. The method includes forming a first and second nanocrystalline silicon structures overlying the first and second portions between the source region and the drain region to form a first and second floating gate structures while maintaining a separation between the first and second nanocrystalline silicon structures. The method includes forming a second dielectric layer overlying the first and second floating gate structures. The method also includes forming a control gate structure overlying the first and second floating gate structures.Type: ApplicationFiled: September 20, 2010Publication date: April 14, 2011Applicant: Semiconductor Manufacturing International (Shangha) CorporationInventor: DEYUAN XIAO
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Publication number: 20110068438Abstract: In inlets used for ID tags and the like, a defective connection between an integrated circuit part and an antenna is suppressed by improvement of tolerance for a bending or a pressing pressure. The integrated circuit part includes a semiconductor chip and a multilayer substrate having a concave portion. The semiconductor chip is mounted on the bottom of the concave portion. The multilayer substrate includes a connection electrode at the top surface and a connection electrode connected to the semiconductor chip on the bottom of the concave portion. The connection electrode on the bottom of the concave portion is connected to the connection electrode at the top surface by a penetration electrode inside a multilayer substrate. By such a configuration, the semiconductor chip is connected to the antenna.Type: ApplicationFiled: November 23, 2010Publication date: March 24, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei YAMAZAKI, Yasuyuki ARAI
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Patent number: 7910977Abstract: A semiconductor storage element includes: a semiconductor layer constituted of a line pattern with a predetermined width formed on a substrate; a quantum dot forming an electric charge storage layer formed on the semiconductor layer through a first insulating film serving as a tunnel insulating film; an impurity diffusion layer formed in a surface layer of the semiconductor layer so as to sandwich the quantum dot therebetween; and a control electrode formed on the quantum dot through a second insulating film.Type: GrantFiled: November 29, 2007Date of Patent: March 22, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Kenji Kawabata
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Publication number: 20110051499Abstract: A method of adjusting a resistive change element using a reference is disclosed. The method comprises inspecting a resistive change element to determine a first state; comparing the first state to a reference wherein said reference provides stimulus parameters corresponding to a transition from the first state to a second state; and applying the stimulus parameters to the resistive change element. A resistive change memory cell array is also disclosed.Type: ApplicationFiled: September 1, 2010Publication date: March 3, 2011Inventor: Darlene HAMILTON
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Patent number: 7898850Abstract: Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.Type: GrantFiled: October 12, 2007Date of Patent: March 1, 2011Assignee: Micron Technology, Inc.Inventors: Kyu S. Min, Rhett T. Brewer, Tejas Krishnamohan, Thomas M. Graettinger, D. V. Nirmal Ramaswamy, Ronald A. Weimer, Arup Bhattacharyya
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Publication number: 20110044091Abstract: A two terminal memory device includes first and second conductive terminals and a nanotube article. The article has at least one nanotube, and overlaps at least a portion of each of the first and second terminals. The device also includes stimulus circuitry in electrical communication with at least one of the first and second terminals. The circuit is capable of applying first and second electrical stimuli to at least one of the first and second terminal(s) to change the relative resistance of the device between the first and second terminals between a relatively high resistance and a relatively low resistance. The relatively high resistance between the first and second terminals corresponds to a first state of the device, and the relatively low resistance between the first and second terminals corresponds to a second state of the device.Type: ApplicationFiled: August 23, 2010Publication date: February 24, 2011Applicant: NANTERO, INC.Inventors: Claude L. BERTIN, Mitchell MEINHOLD, Steven L. KONSEK, Thomas RUECKES, Max STRASBURG, Frank GUO, X. M. Henry HUANG, Ramesh SIVARAJAN
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Publication number: 20110044115Abstract: A non-volatile memory device includes a floating gate with pyramidal-shaped silicon nanocrystals as electron storage elements. Electrons tunnel from the pyramidal-shaped silicon nanocrystals through a gate oxide layer to a control gate of the non-volatile memory device. The pyramidal shape of each silicon nanocrystal concentrates an electrical field at its peak to facilitate electron tunneling. This allows an erase process to occur at a lower tunneling voltage and shorter tunneling time than that of prior art devices.Type: ApplicationFiled: August 21, 2009Publication date: February 24, 2011Applicant: Chartered Semiconductor Manufacturing, Ltd.Inventors: Elgin Quek, Chunshan Yin, Shyue Seng Tan, Jae Gon Lee, Chung Foong Tan
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Publication number: 20110037042Abstract: A method for fabricating a phase change memory device including memory cells includes patterning a via to a contact surface of a substrate corresponding to each of an array of conductive contacts to be connected to access circuitry, lining each via with a conformal conductive seed layer to the contact surface, forming a dielectric layer covering the conductive seed layer, and etching a center region of each via to the contact surface to expose the conformal conductive seed layer at the contact surface. The method further includes electroplating phase change material on exposed portions of the conformal conductive seed layer, recessing the phase change material within the center region forming a conductive material that remains conductive upon oxidation, on the recessed phase change material, oxidizing edges of the conformal conductive seed layer formed along sides of each via, and forming a top electrode over each memory cell.Type: ApplicationFiled: August 14, 2009Publication date: February 17, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthew J. Breitwisch, Eric A. Joseph, Alejandro G. Schrott, Xiaoyan Shao
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Publication number: 20110038025Abstract: Provided is a compound semiconductor nanoparticle that exhibits circularly polarized luminescence characteristics. CdS prepared inside a core of ferritin, which is a cage-like protein, exhibits a high circularly polarized luminescence (CPL). A wavelength of the circularly polarized luminescence (CPL) can be controlled by laser irradiation, thereby enabling utilization of the compound semiconductor nanoparticle in the field of bionanotechnology, for example, in creating a WORM (Write-Once Read-Many times) memory. As the cage-like protein, which is a protein with a cavity formed therein, a protein belonging to the ferritin protein family, such as apoferritin, or a recombinant thereof can be used.Type: ApplicationFiled: March 26, 2009Publication date: February 17, 2011Inventors: Masanobu Naitou, Kenji Iwahori
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Publication number: 20110032743Abstract: Colloidal-processed Si particle devices, device fabrication, and device uses have been presented. The generic device includes a substrate, a first electrode overlying the substrate, a second electrode overlying the substrate, laterally adjacent the first electrode, and separated from the first electrode by a spacing. A colloidal-processed Si particle layer overlies the first electrode, the second electrode, and the spacing between the electrodes. The Si particle layer includes a first plurality of nano-sized Si particles and a second plurality of micro-sized Si particles.Type: ApplicationFiled: July 14, 2010Publication date: February 10, 2011Inventors: Jiandong Huang, Liang Tang, Changqing Zhan, Chang-Ching Tu
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Patent number: 7884430Abstract: The present invention is directed to structures and methods of fabricating electromechanical memory cells having nanotube crossbar elements. Such memory cells include a substrate having transistor with a contact that electrically contacts with the transistor. A first support layer is formed over the substrate with an opening that defines a lower chamber above the electrical contact. A nanotube crossbar element is arranged to span the lower chamber. A second support layer is formed with an opening that defines a top chamber above the lower chamber, the top chamber including an extension region that extends beyond an edge of the lower chamber to expose a portion of the top surface of the first support layer. A roof layer covers the top of the top chamber and includes an aperture that exposes a portion of the extension region of the top chamber and includes a plug that extends into the aperture in the roof layer to seal the top and bottom chambers.Type: GrantFiled: February 23, 2010Date of Patent: February 8, 2011Assignee: Nantero, Inc.Inventors: Richard J. Carter, Peter A. Burke, Verne C. Hornback, Thomas Rueckes, Claude L. Bertin
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Patent number: 7885103Abstract: A configuration bit array including a hybrid electromechanical and semiconductor memory cell, and circuitry for addressing and controlling read, write, and erase accesses of the memory.Type: GrantFiled: November 22, 2005Date of Patent: February 8, 2011Assignee: Agate Logic, Inc.Inventors: David Richard Trossen, Malcolm John Wing
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Publication number: 20110024715Abstract: A nano-ionic memory device is provided. The memory device includes a substrate, a chemically inactive lower electrode provided on the substrate, a solid electrolyte layer provided on the lower electrode and including a silver (Ag)-doped telluride (Te)-based nano-material, and an oxidizable upper electrode provided on the electrolyte layer.Type: ApplicationFiled: October 30, 2008Publication date: February 3, 2011Applicant: Ewha University-Industry Collaboration Foundation UnivInventors: William Jo, Ah-Reum Jeong
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Publication number: 20110007559Abstract: Disclosed herein are a nanowire and a current-induced domain wall displacement-type memory device using the same.Type: ApplicationFiled: December 4, 2008Publication date: January 13, 2011Inventors: Kyung-Jin Lee, Hyun-Woo Lee, Soon-Wook Jung
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Patent number: 7858978Abstract: A nonvolatile organic bistable memory device includes a substrate, a lower electrode disposed on the substrate, a lower charge injection layer disposed on the lower electrode, an insulating polymer layer including nanoparticles disposed on the lower charge injection layer, an upper charge injection layer disposed on the insulating polymer layer, and an upper electrode disposed on the upper charge injection layer. The lower and upper charge injection layers each include fullerenes and/or carbon nanotubes.Type: GrantFiled: December 3, 2008Date of Patent: December 28, 2010Assignees: Samsung Electronics Co., Ltd., Industry-University Cooperation FoundationInventors: Tae-Whan Kim, Fushan Li, Young-Ho Kim, Jae-Hun Jung
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Patent number: 7854016Abstract: A process manufactures a probe intended to interact with a storage medium of a probe-storage system, wherein a sacrificial layer is deposited on top of a substrate; a hole is formed in the sacrificial layer; a mold layer is deposited; the mold layer is etched via the technique for forming spacers so as to form a mold region delimiting an opening having an area decreasing towards the substrate. Then a stack of conductive layers is deposited on top of the sacrificial layer, the stack is etched so as to form a suspended structure, formed by a pair of supporting arms arranged to form a V, and an interaction tip projecting monolithically from the supporting arms. Then a stiffening structure is formed, of insulating material, and the suspended structure is fixed to a supporting wafer. The substrate, the sacrificial layer, and, last, the mold region are then removed.Type: GrantFiled: December 18, 2007Date of Patent: December 14, 2010Assignee: STMicroelectronics S.r.l.Inventor: Agostino Pirovano
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Publication number: 20100301117Abstract: The invention relates to a system and a process for storing and reading information, having a data storage medium for storing information and a reading unit for reading the information stored in the data storage medium, the data storage medium having a dielectric and the information being formed by the presence or non-presence of at least one storage electrode in the data storage medium, and the reading unit having at least one input electrode and at least one reading electrode, it being possible for the data storage medium and the reading unit to be coupled to each other, for the purpose of reading the information, in such a manner that the input electrode and the storage electrode form a first capacitor and the reading electrode and the storage electrode form a second capacitor. The reading unit also has means for generating a digital voltage jump at the input electrode and means for comparing the voltage jump occurring at the reading electrode with a reference voltage.Type: ApplicationFiled: October 10, 2007Publication date: December 2, 2010Inventors: Arved Hübber, Thoralt Franz, Michael Otto
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Publication number: 20100291764Abstract: Some embodiments include methods of removing noble metal-containing particles from over a substrate. The substrate is exposed to a composition that reduces adhesion between the noble metal-containing particles and the substrate, and simultaneously the substrate is spun to sweep at least some of the noble metal-containing particles off from the substrate. Some embodiments include methods in which tunnel dielectric material is formed across a semiconductor wafer. Metallic nanoparticles are formed across the tunnel dielectric material. A stack of two or more different materials is formed over the metallic nanoparticles. A portion of the stack is covered with a protective mask while another portion of the stack is left unprotected. The unprotected portion of the stack is removed to expose some of the metallic nanoparticles. The semiconductor wafer to is subjected to etchant suitable to undercut at least some of the exposed metallic nanoparticles, and simultaneously the semiconductor wafer is spun.Type: ApplicationFiled: May 18, 2009Publication date: November 18, 2010Inventors: Fatma Arzum Simsek-Ege, Brian Dolan
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Patent number: 7835170Abstract: Under one aspect, a covered nanotube switch includes: (a) a nanotube element including an unaligned plurality of nanotubes, the nanotube element having a top surface, a bottom surface, and side surfaces; (b) first and second terminals in contact with the nanotube element, wherein the first terminal is disposed on and substantially covers the entire top surface of the nanotube element, and wherein the second terminal contacts at least a portion of the bottom surface of the nanotube element; and (c) control circuitry capable of applying electrical stimulus to the first and second terminals. The nanotube element can switch between a plurality of electronic states in response to a corresponding plurality of electrical stimuli applied by the control circuitry to the first and second terminals. For each different electronic state, the nanotube element provides an electrical pathway of different resistance between the first and second terminals.Type: GrantFiled: August 8, 2007Date of Patent: November 16, 2010Assignee: Nantero, Inc.Inventors: Claude L. Bertin, X. M. Henry Huang, Thomas Rueckes, Ramesh Sivarajan
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Publication number: 20100285336Abstract: A magnetic storage medium is formed of magnetic nanoparticles that are encapsulated within carbon nanotubes, which are arranged in a substrate to facilitate the reading and writing of information by a read/write head. The substrate may be flexible or rigid. Information is stored on the magnetic nanoparticles via the read/write head of a storage device. These magnetic nanoparticles are arranged into data tracks to store information through encapsulation within the carbon nanotubes. As carbon nanotubes are bendable, the carbon nanotubes may be arranged on flexible or rigid substrates, such as a polymer tape or disk for flexible media, or a glass substrate for rigid disk. A polymer may assist holding the nano-particle filled carbon-tubes to the substrate.Type: ApplicationFiled: February 5, 2010Publication date: November 11, 2010Inventor: Tyson York Winarski
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Patent number: 7829886Abstract: A nonvolatile carbon nanotube memory device using multiwall carbon nanotubes and methods of operating and fabricating the same are provided. The nonvolatile memory device may include a substrate, at least one first electrode on the substrate, first and second vertical walls on the at least one first electrode spaced from each other, a multiwall carbon nanotube on the at least one first electrode between the first and second vertical walls, second and third electrodes on the first and second vertical walls respectively and at least one fourth electrode spaced a variable distance D (where D?0) from the multiwall carbon nanotubes.Type: GrantFiled: January 3, 2007Date of Patent: November 9, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Leonid Maslov, Jin-Gyoo Yoo, Cheol-Soon Kim
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Publication number: 20100276654Abstract: Memory cells described herein have an increased current density at lateral edges of the active region compared to that of conventional mushroom-type memory cells, resulting in improved operational current efficiency.Type: ApplicationFiled: April 30, 2009Publication date: November 4, 2010Applicant: Macronix International Co., Ltd.Inventors: Shih-Hung Chen, Yi-Chou Chen
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Patent number: 7826336Abstract: The present invention relates to a device for data storage. In particular the invention relates to a single electron memory device utilizing multiple tunnel junctions, and arrays or matrixes of such devices. The data storage device according to the invention comprises at least one nanowhisker adapted to store a charge. Each of the nanowhiskers comprises a sequence of axial segments of materials of different band gaps, arranged to provide a sequence of conductive islands separated by tunnel barriers and a storage island arranged at one end of the conductive island/tunnel barrier sequence, whereby to provide a data storage capability. The number of conductive islands should preferably be between five and ten.Type: GrantFiled: February 23, 2006Date of Patent: November 2, 2010Assignee: QuNano ABInventors: Claes Thelander, Lars Samuelson
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Patent number: 7821813Abstract: A nanowire memory device and a method of manufacturing the same are provided. A memory device includes: a substrate; a first electrode formed on the substrate; a first nanowire extending from an end of the first electrode; a second electrode formed over the first electrode to overlap the first electrode; and a second nanowire extending from an end of the second electrode corresponding to the end of the first electrode in the same direction as the first nanowire, wherein an insulating layer exists between the first and second electrodes.Type: GrantFiled: March 7, 2007Date of Patent: October 26, 2010Assignees: Samsung Electronics Co., Ltd., Seoul National University Industry FoundationInventors: Jin-gyoo Yoo, Cheol-soon Kim, Jung-hoon Lee
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Patent number: 7817458Abstract: A hybrid memory system having electromechanical memory cells is discussed. A memory cell core circuit has an array of electromechanical memory cells, in which each cell is a crossbar junction at least one element of which is a nanotube or a nanotube ribbon. An access circuit provides array addresses to the memory cell core circuit to select at least one corresponding cell. The access circuit is constructed of semiconductor circuit elements.Type: GrantFiled: February 13, 2008Date of Patent: October 19, 2010Assignee: Nantero, Inc.Inventors: Brent M. Segal, Darren K. Brock, Thomas Rueckes
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Patent number: 7813160Abstract: Memory devices and recordable media are disclosed that take advantage of memory effects in the electronic transport in CdSe nanocrystal (NC) quantum dot arrays. Conduction through a NC array can be reduced with a negative voltage and then restored with a positive voltage. Light can also be used to restore or even increase the NC array conduction. The switching of the conduction in CdSe NC arrays and found the behavior to be highly sensitive to the value and duration of the laser and voltage pulses.Type: GrantFiled: January 11, 2006Date of Patent: October 12, 2010Assignee: The Trustees Of The University Of PennsylvaniaInventors: Marija Drndic, Michael D. Fischbein
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Patent number: 7811883Abstract: A non-volatile memory transistor with a nanocrystal-containing floating gate formed by nanowires is disclosed. The nanocrystals are formed by the growth of short nanowires over a crystalline program oxide. As a result, the nanocrystals are single-crystals of uniform size and single-crystal orientation.Type: GrantFiled: May 15, 2008Date of Patent: October 12, 2010Assignee: International Business Machines CorporationInventor: Guy M. Cohen
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Publication number: 20100224930Abstract: Some embodiments include methods of forming memory cells. Dopant is implanted into a semiconductor substrate to form a pair of source/drain regions that are spaced from one another by a channel region. The dopant is annealed within the source/drain regions, and then a plurality of charge trapping units are formed over the channel region. Dielectric material is then formed over the charge trapping units, and control gate material is formed over the dielectric material. Some embodiments include memory cells that contain a plurality of nanosized islands of charge trapping material over a channel region, with adjacent islands being spaced from one another by gaps. The memory cells can further include dielectric material over and between the nanosized islands, with the dielectric material forming a container shape having an upwardly opening trough therein. The memory cells can further include control gate material within the trough.Type: ApplicationFiled: May 21, 2010Publication date: September 9, 2010Applicant: MICRON TECHNOLOGY, INC.Inventor: Hussein I. Hanafi
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Patent number: 7792009Abstract: A ferroelectric polarization pattern with differing feedback signals. An apparatus including a ferroelectric layer and a polarization pattern configured in the ferroelectric layer to represent position data. The polarization pattern has a first switchable polarization state domain and a second switchable polarization state domain that are both switchable by an applied signal. The first switchable polarization state domain has a first feedback signal in response to the applied signal that is different than a second feedback signal of the second switchable polarization state domain at the applied signal.Type: GrantFiled: October 2, 2007Date of Patent: September 7, 2010Assignee: Seagate Technology LLCInventors: Florin Zavaliche, Philip George Pitcher, Tong Zhao, Dierk Guenter Bolten
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Publication number: 20100213473Abstract: An optical memory cell having a material layer associated with a pixel capable of emitting and receiving light. The material layer has phosphorescent material formed therein for storing data as light received from and emitted to the pixel.Type: ApplicationFiled: April 29, 2010Publication date: August 26, 2010Inventor: Terry L. Gilton
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Patent number: 7782652Abstract: Nanotube-based switching elements with multiple controls and circuits made from such. A switching element includes an input node, an output node, and a nanotube channel element having at least one electrically conductive nanotube. A control structure is disposed in relation to the nanotube channel element to controllably form and unform an electrically conductive channel between said input node and said output node. The output node is constructed and arranged so that channel formation is substantially unaffected by the electrical state of the output node. The control structure includes a control electrode and a release electrode, disposed on opposite sides of the nanotube channel element. The control and release may be used to form a differential input, or if the device is constructed appropriately to operate the circuit in a non-volatile manner. The switching elements may be arranged into logic circuits and latches having differential inputs and/or non-volatile behavior.Type: GrantFiled: October 6, 2008Date of Patent: August 24, 2010Assignee: Nantero, Inc.Inventors: Claude L. Bertin, Thomas Rueckes, Brent M. Segal
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Patent number: 7781831Abstract: A semiconductor device includes a substrate (12), a first insulating layer (14) over a surface of the substrate (12), a layer of nanocrystals (13) over a surface of the first insulating layer (14), a second insulating layer (15) over the layer of nanocrystals (13). A nitriding ambient is applied to the second insulating layer (15) to form a barrier to further oxidation when a third insulating layer (22) is formed over the substrate (12). The nitridation of the second insulating layer (15) prevents oxidation or shrinkage of the nanocrystals and an increase in the thickness of the first insulating layer 14 without adding complexity to the process flow for manufacturing the semiconductor device (10).Type: GrantFiled: December 12, 2007Date of Patent: August 24, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Sangwoo Lim, Robert F. Steimle
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Patent number: 7782650Abstract: Under one aspect, a memory array includes word lines; bit lines; memory cells; and a memory operation circuit. Each memory cell responds to electrical stimulus on a word line and on a bit line and includes: a two-terminal non-volatile nanotube switching device having first and second terminals, a semiconductor diode element, and a nanotube fabric article capable of multiple resistance states. The semiconductor diode and nanotube article are between and in electrical communication with the first and second terminals, which are coupled to the word line bit line respectively. The operation circuit selects cells by activating bit and/or word lines, detects a resistance state of the nanotube fabric article of a selected memory cell, and adjusts electrical stimulus applied to the cell to controllably induce a selected resistance state in the nanotube fabric article. The selected resistance state corresponds to an informational state of the memory cell.Type: GrantFiled: August 8, 2007Date of Patent: August 24, 2010Assignee: Nantero, Inc.Inventors: Claude L. Bertin, Thomas Rueckes, X. M. Henry Huang, Ramesh Sivarajan, Eliodor G. Ghenciu, Steven L. Konsek, Mitchell Meinhold, Jonathan W. Ward, Darren K. Brock
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Patent number: 7781862Abstract: A two terminal switching device includes first and second conductive terminals and a nanotube article. The article has at least one nanotube, and overlaps at least a portion of each of the first and second terminals. The device also includes a stimulus circuit in electrical communication with at least one of the first and second terminals. The circuit is capable of applying first and second electrical stimuli to at least one of the first and second terminal(s) to change the relative resistance of the device between the first and second terminals between a relatively high resistance and a relatively low resistance. The relatively high resistance between the first and second terminals corresponds to a first state of the device, and the relatively low resistance between the first and second terminals corresponds to a second state of the device.Type: GrantFiled: November 15, 2005Date of Patent: August 24, 2010Assignee: Nantero, Inc.Inventors: Claude L. Bertin, Mitchell Meinhold, Steven L. Konsek, Thomas Ruckes, Max Strasburg, Frank Guo, X. M. Henry Huang, Ramesh Sivarajan
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Publication number: 20100202272Abstract: A method of fabricating an information storage medium, the method including forming a plurality of nanorod recording layers on a substrate by sputtering using a mask having a plurality of nanorod patterns.Type: ApplicationFiled: January 25, 2010Publication date: August 12, 2010Inventors: Joo-ho Kim, Tao Hong, Dae-hwan Kim, Seung-jin Oh, Sun-rock Choi
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Publication number: 20100197095Abstract: Some embodiments include methods of forming memory cells. A semiconductor construction may be provided, with such construction including tunnel dielectric material over a semiconductor substrate. The construction may be placed within a chamber. While the construction is within the chamber, a plurality of charge-trapping centers may be dispersed over the tunnel dielectric material. The charge-trapping centers may be nanoclusters formed by sputter-depositing metallic nanoparticles into an aggregation chamber, and then aggregating groups of the nanoparticles into the nanoclusters. Also while the construction is within the chamber, electrically insulative material may be formed over and between the charge-trapping centers. Control gate material may then be formed over the electrically insulative material.Type: ApplicationFiled: February 3, 2009Publication date: August 5, 2010Inventor: John Mark Meldrim
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Publication number: 20100195249Abstract: A method of manufacturing a magnetic recording medium includes forming an electrically conductive intermediate layer over a non-magnetic substrate; forming an aluminum-containing layer on the intermediate layer; forming a plurality of micro pits in the aluminum-containing layer; generating an alumina-containing layer by oxidizing the aluminum-containing layer and simultaneously forming nano holes in the alumina-containing layer originating from the micro pits to expose the intermediate layer; cleaning and drying the nano holes using a sub- and super-critical fluid; and depositing a magnetic metal selectively on the intermediate layer to form a magnetic recording layer having a plurality of magnetic recording elements. The method thus employs alumina nano holes (ANHs) to fill magnetic metal uniformly and selectively even for ANHs with a diameter not larger than 25 nm.Type: ApplicationFiled: February 3, 2010Publication date: August 5, 2010Applicant: Fuji Electric Device Technology Co., Ltd.Inventor: Kouichi Tsuda