Abstract: A memory device includes first and second electrodes and a phase-changeable material region disposed between the first and second electrodes and including first and second portions contacting respective ones of the first and second electrodes and a third portion interconnecting the first and second portions and configured to preferentially heat with respect to the first and second portions responsive to a current passing between the first and second electrodes. The first and second portions of the phase-changeable material region may contact respective ones of the first and second electrodes at respective first and second electrode contact surfaces and the third portion may have a cross-sectional area that is less than areas of each of the first and second contact surfaces. For example, the third portion may include a filament portion extending between the first and second portions.

Abstract: An electrically bistable body for use in electronic devices wherein the bistable body is converted from a low conductivity state to a high conductivity state. The bistable body includes a polymer matrix in which a sufficient amount of capped nanoparticles are dispersed so that the bistable body is converted from a low conductivity state to a high conductivity state upon application of an electrical field. The capped nanoparticles are metal nanoparticles that have been coated with an aromatic thiol.

Abstract: Some embodiments include methods of forming memory cells. Dopant is implanted into a semiconductor substrate to form a pair of source/drain regions that are spaced from one another by a channel region. The dopant is annealed within the source/drain regions, and then a plurality of charge trapping units are formed over the channel region. Dielectric material is then formed over the charge trapping units, and control gate material is formed over the dielectric material. Some embodiments include memory cells that contain a plurality of nanosized islands of charge trapping material over a channel region, with adjacent islands being spaced from one another by gaps. The memory cells can further include dielectric material over and between the nanosized islands, with the dielectric material forming a container shape having an upwardly opening trough therein. The memory cells can further include control gate material within the trough.

Abstract: The present teachings provide for systems, and components thereof, for detecting and/or analyzing light. These systems can include, among others, optical reference standards utilizing luminophores, such as nanocrystals, for calibrating, validating, and/or monitoring light-detection systems, before, during, and/or after sample analysis.

Abstract: An object of the present invention is to provide a resistive nonvolatile memory element having an electric current path which can be realized by a simple and convenient process, and capable of allowing for micro-fabrication. The resistive nonvolatile memory element of the present invention includes first electrode 203, oxide semiconductor layer 204a which is formed on the first electrode 203 and the resistance of which is altered depending on the applied voltage, metal nanoparticles 204b having a diameter of between 2 nm and 10 nm arranged on the oxide semiconductor layer 204a, tunnel barrier layer 204c formed on the oxide semiconductor layer 204a and on the metal nanoparticles 204b, and second electrode 206 formed on the tunnel barrier layer 204c, in which the metal nanoparticles 204b are in contact with the oxide semiconductor layer 204a.

Abstract: Field programmable device (FPD) chips with large logic capacity and field programmability that are in-circuit programmable are described. FPDs use small versatile nonvolatile nanotube switches that enable efficient architectures for dense low power and high performance chip implementations and are compatible with low cost CMOS technologies and simple to integrate.

Abstract: An optical memory cell having a material layer associated with a pixel capable of emitting and receiving light. The material layer has phosphorescent material formed therein for storing data as light received from and emitted to the pixel.

Abstract: Techniques are provided for fabricating memory with metal nanodots as charge-storing elements. In an example approach, a coupling layer such as an amino functional silane group is provided on a gate oxide layer on a substrate. The substrate is dip coated in a colloidal solution having metal nanodots, causing the nanodots to attach to sites in the coupling layer. The coupling layer is then dissolved such as by rinsing or nitrogen blow drying, leaving the nanodots on the gate oxide layer. The nanodots react with the coupling layer and become negatively charged and arranged in a uniform monolayer, repelling a deposition of an additional monolayer of nanodots. In a configuration using a control gate over a high-k dielectric floating gate which includes the nanodots, the control gates may be separated by etching while the floating gate dielectric extends uninterrupted since the nanodots are electrically isolated from one another.

Abstract: Electro-mechanical switches and memory cells using vertically-oriented nanofabric articles and methods of making the same. Under one aspect, a nanotube device includes a substantially horizontal substrate having a vertically oriented feature; and a nanotube film substantially conforming to a horizontal feature of the substrate and also to at least the vertically oriented feature. Under another aspect, an electromechanical device includes a structure having a major horizontal surface and a channel formed therein, the channel having first and second wall electrodes defining at least a portion of first and second vertical walls of the channel; first and second nanotube articles vertically suspended in the channel and in spaced relation to a corresponding first and second wall electrode, and electromechanically deflectable in a horizontal direction toward or away from the corresponding first and second wall electrode in response to electrical stimulation.

Abstract: A nanoelectromechanical tunneling current switch includes a cantilevered nanofilament including a secured end and an unsecured end and a conductor with a surface substantially perpendicular to a longitudinal axis of the nanofilament when the nanofilament is undeflected. The nanofilament is positioned with respect to the conductor to define a gap between the unsecured end of the nanofilament and the surface of the conductor substantially perpendicular to the longitudinal axis of the nanofilament. The nanofilament and the conductor are electrically connected by a circuit, and a tunneling current is configured to flow from the nanofilament to the surface of the conductor substantially perpendicular to the longitudinal axis of the nanofilament. In other embodiments of the nanoelectromechanical tunneling current switch, an electrically conductive membrane can be utilized in place of, or in addition to, the cantilevered nanofilament.

Abstract: A non-volatile bistable nano-electromechanical switch is provided for use in memory devices and microprocessors. The switch employs carbon nanotubes as the actuation element. A method has been developed for fabricating nanoswitches having one single-walled carbon nanotube as the actuator. The actuation of two different states can be achieved using the same low voltage for each state.

Abstract: A resistive memory device includes a first conductive line on a substrate, a vertical selection diode comprising a nanowire or a nanotube and being arranged over the first conductive line, a resistive element including a resistive layer arranged over the vertical selection diode; and a second conductive line arranged over the resistive element.

Abstract: A memory cell (300, 500), the memory cell (300, 500) comprising a substrate (301), a nanowire (302) extending along a vertical trench formed in the substrate (301), a control gate (303) surrounding the nanowire (302), and a charge storage structure (320, 501) formed between the control gate (303) and the nanowire (302).

Abstract: Programmable metallization memory cells include an electrochemically active electrode and an inert electrode and an ion conductor solid electrolyte material between the electrochemically active electrode and the inert electrode. A sacrificial metal is disposed between the electrochemically active electrode and the inert electrode.

Abstract: An information storage apparatus uses an optical data element (nano-grating) with features that are smaller than the wavelength of light. The optical data element alters one or more properties of the light such as reflected amplitude, polarization, phase, wavelength, and spatial orientation to encode data in a massively multi-level format.

Abstract: A non-volatile solid state resistive device that includes a first electrode, a p-type poly-silicon second electrode, and a non-crystalline silicon nanostructure electrically connected between the electrodes. The nanostructure has a resistance that is adjustable in response to a voltage being applied to the nanostructure via the electrodes. The nanostructure can be formed as a nanopillar embedded in an insulating layer located between the electrodes. The first electrode can be a silver or other electrically conductive metal electrode. A third (metal) electrode can be connected to the p-type poly-silicon second electrode at a location adjacent the nanostructure to permit connection of the two metal electrodes to other circuitry. The resistive device can be used as a unit memory cell of a digital non-volatile memory device to store one or more bits of digital data by varying its resistance between two or more values.

Abstract: Methods for obtaining codes to be implemented in coding nanoscale wires are described. The methods show how to code a reduced number of nanoscale wires through the use of rotation group codes. The methods further show how to generate different code permutations through random misalignment and how to promote uniform code probability selection.

Abstract: Methods of forming planar carbon nanotube (“CNT”) resistivity-switching materials for use in memory cells are provided, that include depositing first dielectric material, patterning the first dielectric material, etching the first dielectric material to form a feature within the first dielectric material, depositing CNT resistivity-switching material over the first dielectric material to fill the feature at least partially with the CNT resistivity-switching material, depositing second dielectric material over the CNT resistivity-switching material, and planarizing the second dielectric material and the CNT resistivity-switching material so as to expose at least a portion of the CNT resistivity-switching material within the feature. Other aspects are also provided.

Abstract: A resistive memory device includes an insulation layer over a substrate, a nanowire penetrating the insulation layer, a resistive layer formed over the insulation layer and contacting with the nanowire, and an upper electrode formed over the resistive layer.

Abstract: A functional molecular device displaying its functions under the action of an electrical field is provided. A Louis base molecule, exhibiting positive dielectric constant anisotropy or exhibiting dipole moment along the long-axis direction of the Louis base molecule, is arrayed in the form of a pendant on an electrically conductive linear or film-shaped principal-axis molecule of a conjugated system, via a metal ion capable of acting as a Louis acid. The resulting structure is changed in conformation on application of an electrical field to exhibit its function. The electrically conductive linear or film-shaped principal-axis molecule and the Louis base molecule form a complex with the metal ion. On application of the electrical field, the Louis base molecule performs a swinging movement or a seesaw movement to switch the electrical conductivity of the principal-axis molecule.

Abstract: A functional protein crystal, wherein each protein in the crystal comprises a cavity containing a core nano-particle, the core nano-particle formed from an elemental metal, a metal alloy, or a metal compound, with the proviso that the protein is not apoferritin Dpr or E. Coli dps when the core particle is ferrihydrite.

Abstract: Provided is a semiconductor memory device that can retain information by trapping electric charges into a trap level in a gate insulating film. The information retention capacity is improved by restricting lateral diffusion of electric charges. The semiconductor memory device is provided with a semiconductor substrate (11), first and second impurities diffusion layers (12; 13) disposed in the semiconductor substrate, a gate insulating film (15) disposed on the semiconductor substrate, and a first gate electrode (16) disposed on the semiconductor substrate by way of the gate insulating film (15). The gate insulating film (15) has a silicon oxide film (14) that contains impurities which tend to combine with oxygen in the silicon oxide film and which are discrete at an atomic level.

Abstract: Non-volatile and radiation-hard switching and memory devices using vertical nano-tubes and reversibly held in state by van der Waals' forces and methods of fabricating the devices. Means for sensing the state of the devices include measuring capacitance, and tunneling and field emission currents.

Abstract: Nanotube-based switching elements and logic circuits. Under one embodiment of the invention, a switching element includes an input node, an output node, a nanotube channel element having at least one electrically conductive nanotube, and a control electrode. The control electrode is disposed in relation to the nanotube channel element to controllably form an electrically conductive channel between the input node and the output node. The channel at least includes said nanotube channel element. The output node is constructed and arranged so that channel formation is substantially unaffected by the electrical state of the output node.

Abstract: A memory device and a method for fabricating the same provide a device capable of increasing or maximizing the performance of a microstructure device. The device includes: a plurality of word lines formed with a gap therebetween and extending in parallel with each other in a first direction of extension; and a bit line insulated from the plurality of word lines, intersecting the plurality of word lines and extending in a second direction of extension, a transition electrode portion of the bit line positioned in the gap and spaced apart from the plurality of word lines by a predetermined distance, the transition electrode portion of the bit line configured and arranged to be bent toward any one of the plurality of word lines in response to an electrical signal applied to at least one of the plurality of word lines.

Abstract: A nano-magnetic memory device capable of writing/reading multi data in the nano-magnetic memory cell by controlling an amount of an induced current which is formed after a magnetic nanodot is perturbed and rearranged according to a word line current flowing from the first electrode through a nanowire of the nano-magnetic memory device to the second electrode. Consequently, a size of the memory device is reduced and a density of the memory device may be improved by providing a simplified nano-magnetic memory device of which a cell size is smaller.

Abstract: Encapsulated particles and methods for manufacturing encapsulated particles and structures are described. Such particles may have a length no greater than 40 nm, and include at least one material selected from the group consisting of ferromagnetic materials and ferrimagnetic materials. A polymeric encapsulant surrounds the particle, the polymeric encapsulant including a phase-separated block copolymer including a glassy first phase and a rubbery second phase, the glassy first phase positioned between the particle and the second rubbery phase. The glassy first phase includes a hydrophobic copolymer having a glass transition temperature of at least 50° C. The rubbery second phase includes a polymer having at least one of (i) a glass transition temperature of no greater than 30° C., and (ii) a tan delta peak maximum of no greater than 30° C. Other embodiments are described and claimed.

Abstract: Electro-mechanical switches and memory cells using vertically-oriented nanofabric articles and methods of making the same. Under one aspect, a nanotube device includes a substantially horizontal substrate having a vertically oriented feature; and a nanotube film substantially conforming to a horizontal feature of the substrate and also to at least the vertically oriented feature. Under another aspect, an electromechanical device includes a structure having a major horizontal surface and a channel formed therein, the channel having first and second wall electrodes defining at least a portion of first and second vertical walls of the channel; first and second nanotube articles vertically suspended in the channel and in spaced relation to a corresponding first and second wall electrode, and electromechanically deflectable in a horizontal direction toward or away from the corresponding first and second wall electrode in response to electrical stimulation.

Abstract: Circuit arrays having cells with combinations of transistors and nanotube switches. Under one embodiment, cells are arranged as pairs with the nanotube switching elements of the pair being cross coupled so that the set electrode of one nanotube switching element is coupled to the release electrode of the other and the release electrode of the one nanotube switching element being coupled to the set electrode of the other. The nanotube articles are coupled to the reference line, and the source of one field effect transistor of a pair is coupled to the set electrode to one of the two nanotube switching elements and the source of the other field effect transistor of the pair is coupled to the release electrode to the one of the two nanotube switching elements.

Abstract: Random access memory including nanotube switching elements. A memory cell includes first and second nanotube switching elements and an electronic memory. Each nanotube switching element includes conductive terminals, a nanotube article and control circuitry capable of controllably form and unform an electrically conductive channel between the conductive terminals. The electronic memory is a volatile storage device capable of storing a logic state in response to electrical stimulus. In certain embodiment the electronic memory has cross-coupled first and second inverters in electrical communication with the first and second nanotube switching elements. The cell can operate as a normal electronic memory, or can operate in a shadow memory or store mode (e.g., when power is interrupted) to transfer the electronic memory state to the nanotube switching elements. The device may later be operated in a recall mode where the state of the nanotube switching elements may be transferred to the electronic memory.

Abstract: According to some embodiments, an article of manufacture comprises a substrate; a molecular layer on the substrate comprising at least one charge storage molecule coupled to the substrate by a molecular linker; a solid barrier dielectric layer directly on the molecular layer; and a conductive layer directly on the solid barrier dielectric layer. In some embodiments, the solid barrier dielectric layer is configured to provide a voltage drop across the molecular layer that is greater than a voltage drop across the solid barrier dielectric layer when a voltage is applied to the conductive layer. In some embodiments, the molecular layer has a thickness greater than that of the solid barrier dielectric layer. The article of manufacture contains no electrolyte between the molecular layer and the conductive layer.

Abstract: A memory device may include a channel including at least one carbon nanotube. A source and a drain may be arranged at opposing ends of the channel and may contact different parts of the channel. A first storage node may be formed under the channel, and a second storage node may be formed on the channel. A first gate electrode may be formed under the first storage node and a second gate electrode may be formed on the second storage node.

Abstract: A method of operating an information storage device using a magnetic domain wall movement in a magnetic nanowire is provided. The magnetic nanowire includes a plurality of magnetic domains and pinning sites formed in regions between the magnetic domains. The method includes depinning the magnetic domain wall from a first pinning site by applying a first pulse current having a first pulse current density to the magnetic nanowire and moving the magnetic domain wall to a second pinning site by applying a second pulse current having a second pulse current density to the magnetic nanowire. The first pulse current density is greater than the second pulse current density.

Abstract: A nanostructure comprising a first structure comprising conductive material, which is attached to a second structure comprising one or more portions of conductive material separated by insulator material, which is attached to a third structure comprising a material in which a change can be effected. The third structure may comprise a dielectric or ferroelectric material, and the change effected in the material may be polarization of the material. The nanostructure may comprise one or more nanocapacitors, each of which comprises a part of the third structure in which a change comprising polarization may be effected. The nanocapacitors may be used to store data.

Abstract: A magnetic head for use in a magnetic recording apparatus for magnetically recording information in a state of heating and elevating the temperature of a recording portion of a recording medium by emitting electrons to the recording medium, the magnetic head including a recording magnetic pole having a magnetic surface opposed to the recording medium, and supplying a magnetic flux to the recording medium and an electron emitting source formed in the recording magnetic pole. The electron emitting source has a concave portion having an opening formed in the recording magnetic pole and open to the recording magnetic pole surface and a bundle of a plurality of carbon nanotubes each extending from the bottom to the opening of the concave portion.

Abstract: Some embodiments include memory cells that contain a dynamic random access memory (DRAM) element and a nonvolatile memory (NVM) element. The DRAM element contains two types of DRAM nanoparticles that differ in work function. The NVM contains two types of NVM nanoparticles that differ in trapping depth. The NVM nanoparticles may be in vertically displaced charge-trapping planes. The memory cell contains a tunnel dielectric, and one of the charge-trapping planes of the NVM may be further from the tunnel dielectric than the other. The NVM charge-trapping plane that is further from the tunnel dielectric may contain larger NVM nanoparticles than the other NVM charge-trapping plane. The DRAM element may contain a single charge-trapping plane that has both types of DRAM nanoparticles therein. The memory cells may be incorporated into electronic systems.

Abstract: Isolated conductive nanoparticles on a dielectric layer and methods of fabricating such isolated conductive nanoparticles provide charge storage units in electronic structures for use in a wide range of electronic devices and systems. The isolated conductive nanoparticles may be used as a floating gate in a flash memory. In an embodiment, conductive nanoparticles are deposited on a dielectric layer by a plasma-assisted deposition process such that each conductive nanoparticle is isolated from the other conductive nanoparticles to configure the conductive nanoparticles as charge storage elements.

Abstract: Carbon nanotube memory comprises a buffered data path including a forwarding write line and a returning read line for transferring data. Furthermore, bit line is multi-divided for reducing parasitic capacitance, so that multi-stage sense amps are used for reading, wherein a local sense amp receives a memory cell output through the bit line, a segment sense amp receives a local sense amp output, and a global sense amp receives a segment sense amp output. By the sense amps, a voltage difference in the bit line is converted to a time difference for differentiating high data and low data. For example, high data is quickly transferred to an output latch circuit through the sense amps with high gain, but low data is rejected by a locking signal based on high data as reference signal. Additionally, alternative circuits and memory cell structures for implementing the memory are described.

Abstract: An electrically erasable programmable read only memory (EEPROM) cell includes cell selection circuitry and a storage cell for storing the informational state of the cell. The storage cell is an electro-mechanical data retention cell in which the physical positional state of a storage cell element represents the informational state of the cell. The storage cell element is a carbon nanotube switching element. The storage is writable with supply voltages used by said cell selection circuitry. The storage is writable and readable via said selection circuitry with write times and read times being within an order of magnitude. The write times and read times are substantially the same. The storage has no charge storage or no charge trapping.

Abstract: A memory device may include a channel including at least one carbon nanotube. A source and a drain may be arranged at opposing ends of the channel and may contact different parts of the channel. A first storage node may be formed under the channel, and a second storage node may be formed on the channel. A first gate electrode may be formed under the first storage node and a second gate electrode may be formed on the second storage node.

Abstract: The present invention relates to reconfigurable circuitry, and more particularly to the reconfiguration of the characteristics of materials used in the formation of electronic circuitry as the result of applied external influences. Exemplary embodiments of the present invention provide an apparatuses, methods, electronic devices and computer program products that include a nanoscale material layer, and a programmable element in close proximity to at least a first section of the nanoscale material layer. The programmable element is configured to produce interference with an electron wave in at least the first section of the nanoscale material layer.

Abstract: A micro electronic component, preferably in the form of an electronic memory, includes the use of clusters as an electronic memory. Also disclosed as part of the present invention is a method for fabricating a micro electronic component. The present invention contemplates fabrication of an especially compact electronic memory that works especially with single-electron transistors or single-electronic transfers. According to the present invention, clusters with a metallic cluster nucleus are arranged in parallel grooves essentially in lines or rows and are connected individually to first and second connecting electrodes, such that individually the clusters can be electrically modified or polled independently of each other.

Abstract: Methods and apparatuses for nanoenabled memory devices and anisotropic charge carrying arrays are described. In an aspect, a memory device includes a substrate, a source region of the substrate, and a drain region of the substrate. A population of nanoelements is deposited on the substrate above a channel region, the population of nanolements in one embodiment including metal quantum dots. A tunnel dielectric layer is formed on the substrate overlying the channel region, and a metal migration barrier layer is deposited over the dielectric layer. A gate contact is formed over the thin film of nanoelements. The nanoelements allow for reduced lateral charge transfer. The memory device may be a single or multistate memory device.

Abstract: A flash memory device with a nanoscale floating gate and a method of manufacturing thereof are disclosed. At least one embodiment of the present invention provides a much simpler and easier method of manufacturing nanocrystals (or nanocrystallines) for the flash memory device than the conventional method. Since the nanocrystals are homogeneously dispersed as a polymer layer without agglomeration, size and density of the nanoparticles may be controlled. Additionally, one embodiment of the present invention provides memory devices with nanoscale floating gates, and related methods of manufacture, of high efficiency and cost effectiveness by employing electrically and chemically more stable nanoscale floating gates compared to conventional ones.

Abstract: The invention relates a cell device and a cell string for high density flash memory. The cell string includes a plurality of cell devices and switching devices connected to ends of the plurality of cell devices. The cell device includes a semiconductor substrate, an insulating film, a charge storage node composed of nano-sized dots, a control insulating film and a control electrode which are sequentially formed on the semiconductor substrate, without source/drain regions. In the cell string, the silicon substrate enables easy formation of an inversion layer acting as the source/drain regions. The switching device does not include a source or drain region at a side connected to an adjacent cell device but includes a source or drain region at the side opposite to the side connected to the adjacent cell device.

Abstract: Disclosed is a phase change memory device including: a semiconductor substrate formed with a first insulating interlayer having a first contact hole; a contact plug formed in such a manner so as to be recessed within the first contact hole; a catalyst layer formed on the contact plug in such a manner so as to fill the first contact hole; a second insulating interlayer formed on the first insulating interlayer including the catalyst layer having a second contact hole through which the catalyst layer is exposed; a carbon nano tube lower electrode formed within the second contact hole in such a manner so as to come in contact with the catalyst layer; a phase change layer formed on the carbon nano tube lower electrode and a second insulating interlayer portion around the second contact hole; and an upper electrode formed on the phase change layer.

Abstract: Random access memory including nanotube switching elements. A memory cell includes first and second nanotube switching elements and an electronic memory. Each nanotube switching element includes conductive terminals, a nanotube article and control circuitry capable of controllably form and unform an electrically conductive channel between the conductive terminals. The electronic memory is a volatile storage device capable of storing a logic state in response to electrical stimulus. In certain embodiment the electronic memory has cross-coupled first and second inverters in electrical communication with the first and second nanotube switching elements. The cell can operate as a normal electronic memory, or can operate in a shadow memory or store mode (e.g., when power is interrupted) to transfer the electronic memory state to the nanotube switching elements. The device may later be operated in a recall mode where the state of the nanotube switching elements may be transferred to the electronic memory.

Abstract: A Bi4Ti3O12 nanoplate, an array of such Bi4Ti3O12 nanoplate and their making methods as well as their applications are provided. Using a vapor phase growth method, a flux layer of VOx is deposited on a SrTiO3 (001) faced substrate and then Bi4Ti3O12 is deposited on the flux layer. A Bi4Ti3O12 single crystal nanoplate is formed standing up on the flux layer in the form of a rectangular solid whose independent three sides are crystallographically oriented in directions coincident with particular crystallographic directions of the single crystal substrate, respectively. The nanoplates as a nanostructure grown by the bottom-up method are substantially fixed in shape and are densely arrayed not in contact with one another, and are applicable to a low-cost ferroelectric memory and the like.

Abstract: Isolated conductive nanoparticles on a dielectric layer and methods of fabricating such isolated conductive nanoparticles provide charge storage units in electronic structures for use in a wide range of electronic devices and systems. The isolated conductive nanoparticles may be used as a floating gate in a flash memory. In an embodiment, conductive nanoparticles are deposited on a dielectric layer by a plasma-assisted deposition process such that each conductive nanoparticle is isolated from the other conductive nanoparticles to configure the conductive nanoparticles as charge storage elements.

Abstract: A magnetic switching element according to an example of the present invention includes a magnetic element, first and second electrodes which put the magnetic element therebetween, a current control section which is connected to the first and second electrodes, the current control section controlling a magnetization direction of a magnetization free section in such a manner that a current is made to flow between the magnetization free section and the magnetization fixed section, a movable conductive tube having a fixed end and a free end, and a third electrode connected to the fixed end of the conductive tube. A switching operation is performed in such a manner that a spatial position of the conductive tube is caused to change depending on the magnetization direction of the magnetization free section.