Abstract: An embodiment of the invention provides an isolation cell for isolating a second power domain from a first power domain. The isolation cell includes an input terminal capable of receiving a first signal of the first power domain, an output terminal capable of outputting an output signal with a predetermined logic state to the second power domain, a first power terminal and a second power terminal. The first power terminal is capable of receiving a voltage from a power source, the power source is different from a first power source of the first power domain, and the isolation cell is powered by the voltage.

Abstract: A device, such as a transceiver or a sensor, is provided. An interface circuit of the device terminates a signal line with an impedance matching an impedance of the signal line. A controller of the device is configured to transmit or receive data on the signal line through the interface circuit and according to a communication protocol employing pulse width modulation (PWM) for data encoding. A system having two or more devices with impedance matching interface circuits, and a method for communication with a device having an impedance matching interface circuit, are also provided.

Abstract: Method and apparatus to calibrate sampling phases of a multi-phase sampling system. The method includes on-chip generating a pristine phase reference pattern signal for use in generating at least one reference output signal from a data path; sampling, responsive to a clock signal, the at least one reference output signal to obtain samples; and modifying a phase of the clock signal to align the obtained samples to pattern edges of at least one reference output signal. Both symmetric and asymmetric duty cycle distortion are removed from the pristine phase reference pattern signal input to the data path. The effects of asymmetric distortion in the data path output signal upon the phase calibration are cancelled by periodically inverting the at least one reference output signal.

Abstract: A data sampling circuit module, a data sampling method and a memory storage device are provided. The method includes: receiving a differential signal and generating a sensing voltage pair according to the differential signal, where the sensing voltage pair includes a first sensing voltage and a second sensing voltage, a voltage value of the first sensing voltage is related to a first differential signal of the differential signal, and a voltage value of the second sensing voltage is related to a second differential signal of the differential signal; and receiving the sensing voltage pair and outputting a sampling data stream according to a clock of the differential signal and a voltage relative relationship of the sensing voltage pair.

Abstract: A method for 3D voltage type TSV signal transmission, comprising transmitting a full swing signal of data with a first voltage through TSVs for each one of a plurality of slave devices to determine a transmission time required for data transmission to a master device. Then, full swing signal is sensed by the master device for reduce the first voltage to be a small swing signal with lower voltage. Logic “0” signals or logic “1” signals with the lower voltage are transmitted through the TSVs by the plurality of slave devices. It is sharing charge and balancing voltage level to a mean value for the logic “1” signals or the logic “0” signals by the master device.

Abstract: A data output circuit may include a first node, which receives a first strobe signal, a second node, which receives a second strobe signal, an input control unit that is coupled to the first and second nodes, and receives the first strobe signal generated from a single strobe signal transmitted through a first path of a semiconductor memory apparatus and the second strobe signal generated from the single strobe signal transmitted from a second path of the semiconductor memory apparatus in response to a read command, generates a first input control signal based on the first strobe signal and the second strobe signal, and generates a second input control signal based on the second strobe signal.

Abstract: A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to generate an indication of whether the first signal exceeds a threshold level. A first threshold control circuit is coupled to receive the indication from the receive circuit and configured to adjust the threshold level according to whether the first signal exceeds the threshold level. A drive strength control circuit is coupled to receive the indication from the receive circuit and configured to adjust a drive strength of at least one output driver of the plurality of output drivers according to whether the first signal exceeds the threshold level.

Abstract: A buffer circuit of a semiconductor apparatus includes a sensing circuit configured to sense input signals according to a data strobe signal, generate latch control signals, provide the latch control signals at nodes, and remove parasitic components of the nodes in response to a clock signal; and a latch circuit configured to generate and latch output data in response to the latch control signals.

Abstract: A method for enabling double pumping in a limited switch dynamic logic circuit includes precharging a dynamic node in accordance with a first clock signal and a second clock signal. The dynamic node is evaluated to a first value in response to one or more first input signals of a first evaluation tree in accordance with the first clock signal. The dynamic node is evaluated to a second value in response to one or more second input signals of a second evaluation tree in accordance with the second clock signal.

Abstract: A dynamic logic circuit includes a precharge device configured to precharge a dynamic node in accordance with a first and second evaluation clock signal. A first evaluation tree is configured to evaluate the dynamic node to a first value in response to one or more first input signals in accordance with the first evaluation clock signal. A second evaluation tree configured to evaluate the dynamic node to a second value in response to one or more second input signals in accordance with the second evaluation clock signal.

Abstract: In one embodiment, a system for communication has a receiver for receiving data from a passive transmitter capacitively coupled to the receiver. The receiver has a sensing element having a plurality of terminals configured to be capacitively coupled to the passive transmitter and DC isolated from the passive transmitter.

Abstract: A method of controlling signal termination includes providing first logic for selectively terminating signals received at a first device on a bidirectional data bus, providing second logic for selectively terminating signals received at a second device on the bidirectional data bus, sending first signals from the first device to the second device on the bidirectional data bus at a first speed, stopping the sending of the first signals, after stopping the sending of the first signals, enabling the second logic and shifting a reference voltage of the second device from a first level to a second level, after enabling the second logic at the second device, sending second signals from the first device to the second device on the bidirectional data bus at a higher speed, and controlling the first logic based on a speed of signals received at the first device on the bidirectional data bus.

Abstract: Hardening of an integrated circuit such as a GPU processor to soft errors caused by particle strikes is applied selectively to the set of devices according to the magnitude of error resulting from this soft error for the particular device. This approach differs from approaches that protect all devices, all devices likely to produce an output error, or all devices that are vulnerable.

Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit and a data receiving circuit that receives data transmitted from the data transmitting circuit. The data transmitting circuit includes a data output circuit that outputs the data or sets an output to a high impedance state, and a control circuit that outputs a control signal to the data output circuit so that the data output circuit outputs the data when the data transmitting circuit transmits the data, and the data output circuit keeps outputting data last output in the previous data transmission, during a predetermined period after the previous data transmission when the data transmitting circuit further transmits another data after transmitting the data.

Abstract: An input buffer includes a first driving circuit, a second driving circuit, a pull up circuit, and a pull down circuit. The first driving circuit is arranged for driving a first input signal to generate an output signal. The second driving circuit is arranged for driving the output signal. The pull up circuit is arranged for selectively controlling the second driving circuit to pull up the output signal according to the first input signal and a second input signal. The pull down circuit is arranged for selectively controlling the second driving circuit to pull down the output signal according to the first input signal and the second input signal.

Abstract: A buffer system is provided that reduces threshold current using a current source to provide power to one or more stages of the buffer system. The buffer system may also include delay management techniques that balances all of, or part of, a delay that may be imparted to an input signal by the current source. In addition, hysteresis techniques may be used to provide enhanced noise management of the input signal.

Abstract: An integrated circuit can include at least one slew generator circuit comprising at least one body biasable reference transistor, the slew generator circuit configured to generate at least a first signal having a slew rate that varies according to characteristics of the reference transistor; a pulse generator circuit configured to generate a pulse signal having a first pulse with a duration corresponding to the slew rate of the first signal; and a counter configured to generate a count value corresponding to a duration of the first pulse.

Abstract: A method of controlling signal termination includes providing first logic for selectively terminating signals received at a first device on a bidirectional data bus, providing second logic for selectively terminating signals received at a second device on the bidirectional data bus, sending first signals from the first device to the second device on the bidirectional data bus at a first speed, stopping the sending of the first signals, after stopping the sending of the first signals, enabling the second logic and shifting a reference voltage of the second device from a first level to a second level, after enabling the second logic at the second device, sending second signals from the first device to the second device on the bidirectional data bus at a higher speed, and controlling the first logic based on a speed of signals received at the first device on the bidirectional data bus.

Abstract: Apparatus and methods for driving a signal are disclosed. An example apparatus includes a pre-driver circuit and a driver circuit. The pre-driver circuit includes a step-down transistor and the driver circuit includes a pull-down transistor configured to be coupled to a reference voltage. In a first mode, the step-down transistor is configured to reduce a voltage provided to the pull-down transistor to less than a supply voltage, and in a second mode, the step-down transistor configured to provide the voltage of the supply voltage to the pull-down transistor. The pre-driver circuit of the example signal driver circuit may further include a step-up transistor configured to increase a voltage provided to a pull-up transistor of the driver circuit to greater than the reference voltage, and in the second mode, the step-up transistor configured to provide the voltage of the reference voltage to the pull-up transistor.

Abstract: Inventive aspects include a method, apparatus, and system for reducing power switch cells in MTCMOS circuits. Such may include disposing columns of real and virtual power straps orthogonally over rows of logic cells. A first power switch cell can be disposed over a real and a virtual power strap in a first column, and collinear with a first row of logic cells. A second power switch cell can be disposed over a real a virtual power strap in a second column, and collinear with a fifth row of logic cells. A third power switch cell can be disposed over a real a virtual power strap in a third column, and collinear with a third row of logic cells. A fourth power switch cell can be disposed over a real a virtual power strap in a fourth column, and collinear with a seventh row of logic cells.

Abstract: A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to generate an indication of whether the first signal exceeds a threshold level. A first threshold control circuit is coupled to receive the indication from the receive circuit and configured to adjust the threshold level according to whether the first signal exceeds the threshold level. A drive strength control circuit is coupled to receive the indication from the receive circuit and configured to adjust a drive strength of at least one output driver of the plurality of output drivers according to whether the first signal exceeds the threshold level.

Abstract: An integrated circuit may include memory interface circuitry that is used to communicate with off-chip memory. The memory interface circuitry may include data strobe (DQS) enable circuitry that receives DQS signals from the off-chip memory and that outputs a gated version of the DQS signals. The DQS enable circuitry may include an input buffer, a comparator, a latch, a flip-flop, a counter, and a gating circuit. The input buffer may receive an incoming DQS signal. The comparator may be used to determine when the incoming DQS signal starts to toggle. The latch may be used to control when a gating signal is asserted. The flip-flop controls the counter, which limits the duration that the gating signal is asserted. The gating circuit receives the DQS signal from the buffer and the gating signal and passes the DQS signal through to its output only when the gating signal is asserted.

Abstract: Various implementations include circuits, devices and/or methods that provide closed-loop feedback crowbar current limiting for logic level-shifting between circuits with different voltage supplies. Some implementations include a level-shift circuit assembly including an input buffer and a current limiter. The input buffer is configured to receive an incoming logic signal that is set relative to a first electrical level, and in response, provide a level-shifted logic signal that is set relative to a second electrical level and is logically consistent with the incoming logic signal. The current limiter is configured to suppress the generation of current associated with the input buffer by providing a bias modification condition to the input buffer, in order to adjust the operation of the input buffer, in response to sensing a voltage difference between the first electrical level and the second electrical level.

Abstract: A transmission line driver including an output configured to have a load impedance is provided. The transmission line driver includes a pull-up circuit coupled in series with the output. The transmission line driver also includes a pull-down circuit coupled in series with the output. The transmission line driver includes a shunt circuit having an adjustable impedance. The shunt circuit is coupled in parallel to the output. The shunt circuit is coupled to the pull-up circuit and the pull-down circuit. The shunt circuit is configured to receive a shunt control signal to adjust the adjustable impedance to provide linear control of an output swing at the output.

Abstract: Methods relating to distribution of a clock signal to logic devices of an integrated circuit. The method includes controlling, by a logic element, the distribution of a clock signal by a clock gater and distributing the clock signal by the clock gater to at least one first logic device, wherein the logic element allows the first clock gater to distribute the clock signal only when at least one first logic device requires the clock signal. An integrated circuit configured to perform such a method. Fabrication of such an integrated circuit.

Abstract: Hardware interrupt functionality associated with a disable pin may be used to place a near-field communication (NFC) device into various operational modes. For example, various intermediate voltage windows may be defined within an I/O voltage domain and a resistive divider running off an I/O rail may generate multiple reference voltages within the I/O voltage domain. In one embodiment, different comparators may compare voltage on the disable pin to the reference voltages generated with the resistive divider to determine whether the voltage on the disable pin falls within one of the intermediate voltage windows. As such, if a particular comparator determines that the voltage on the disable pin falls within one of the intermediate voltage windows, a control signal may be generated to transition the NFC device into a corresponding operational mode.

Abstract: An isolation receiver includes at least one isolation capacitor to provide a first logic signal in response to a second logic signal that is provided by a transmitter. The receiver includes a signal processing circuit to amplify the first logic signal to generate an amplified signal, and the signal processing circuit includes a an amplifier to apply a nonlinear function. A comparator of the receiver provides a third logic signal in response to the amplified signal.

Abstract: A termination network for a receiver device is provided to support both D-PHY signaling and N-factorial signaling. The first end of each of a plurality dynamically configurable switches is coupled to a common node. A first end of each of a plurality of resistances is coupled to a second end of a corresponding switch. A plurality of terminals receive differential signals and each terminal is coupled to a corresponding second end of a resistance. Each of a plurality differential receivers is coupled between two terminals of the termination network, wherein a first differential receiver and a second differential receiver are coupled to the same two terminals, the first differential receiver is used when the differential signals use a first type of differential signal encoding, the second differential receiver is used when the differential signals use a second type of differential signal encoding.

Abstract: A termination circuit for a plurality of memories controlled by a controller is provided. The termination circuit includes a plurality of drivers, a plurality of resistors and a plurality of capacitors. Each of the drivers is coupled to the memories via a transmission line. Each of the resistors is coupled to the corresponding driver via the corresponding transmission line. Each of the capacitors is coupled between the corresponding resistor and a reference voltage. The controller is coupled to the memories via the drivers, and the controller provides a specific code to one of the drivers when a quantity of logic “0” and a quantity of logic “1” transmitted to the memories via the transmission line corresponding to the one of the drivers are unbalanced, so as to adjust a termination voltage of the capacitor corresponding to the one of the drivers.

Abstract: There is provided a signal processing device which is capable of suppressing the influence of a digital data process on an analog signal process without completely stopping a digital data processing circuit. A signal, processing device includes an analog signal processing circuit, a digital data processing circuit, a determination section configured to determine an influence of the digital data processing circuit on the analog signal processing circuit, and a control section configured to stop a partial circuit of the digital data processing circuit or lower processing capability thereof in response to a determination result of the determination section.

Abstract: Provided is a method for reducing output data noise of a semiconductor apparatus which includes a plurality of output buffers to output data. The method includes the steps of: driving low data to a specific output buffer among the plurality of output buffers, and driving data transiting from a high level to a low level to the other output buffers; and measuring the magnitude of data noise occurring in output data of the specific output buffer, and deciding slew rates of the plurality of output buffers based on the measurement result.

Abstract: A signal transmission circ it includes a main driving unit configured to drive a first signal transmission One in response to an input signal and output a first driven signal, an emphasis driving unit configured to perform an emphasis operation on the first driven signal and output an emphasized signal, and a crosstalk control unit configured to perform an equalizing operation on the emphasized signal.

Abstract: A semiconductor device has a first controlled chip, including a first replica output circuit having the same configuration as a first output circuit, a first ZQ terminal connected to the first replica output circuit, a first through electrode connected to the first ZQ terminal, and a first control circuit which sets the impedance of the first replica output circuit. A control chip includes a second ZQ terminal connected to the first through electrode, a comparator circuit which compares a voltage of the second ZQ terminal with a reference voltage, and a second control circuit 123 which performs a process based on a comparison by the comparator circuit. The first control circuit and the second control circuit receive a common input signal to operate and sequentially change and set the impedance until the comparison result changes when an external resistance element is connected to the second ZQ terminal.

Abstract: In an asymmetrically terminated communication system, the power consumed to transmit a particular bit value is adjusted based on whether the bit being output is the second, third, fourth, etc. consecutive bit with the same value after a transition to output the particular bit value. The adjustment of the power consumed to transmit the two or more consecutive bits with the same value may be made by adjusting the driver strength during the second, or subsequent, consecutive bits with the same value. The adjustment of the power consumed is performed on the bit value that consumes the most DC power and the other value is typically not adjusted.

Abstract: An electronic device which includes a first stage having an input capacitance, a switch, a buffer and a second stage having an input sensitive to charge injection and/or voltage glitches. An input of the buffer and the input of the second stage are coupled together at a first node which is configured to be coupled to a voltage source for supplying a reference voltage to the input of the first stage having the input capacitance. In a first configuration of the switch, the switch is arranged to either connect the input of the first stage to the first node and to disconnect the input of the first stage from an output of the buffer. In a second configuration of the switch, to connect the input of the first stage to the output of the buffer and to disconnect the input of the first stage from the first node.

Abstract: Introduced is an active shield method providing security to a security critical integrated circuit against some physical attacks like probing, manipulation and modification, while providing the ability to detect any physical modification made on the active shield itself. Electrically controllable switching circuits are used to construct the upper layer conductive bit lines with electrically selectable different interconnection configurations. These bit lines arranged in a shielding pattern are used to carry a test data between a transmitter circuitry and a number of receiver circuitries which verify the integrity of the shielding lines to provide the security for the integrated circuit. By changing the selected interconnection configuration of the bit lines with a select signal produced by the transmitter, the self detection ability of the proposed active shield is provided as a countermeasure against the vulnerability to physical modification made on the active shield itself.

Abstract: A low-leakage IO circuit is provided. The IO circuit includes an impedance path between a pad and a power supply. The impedance path bypasses a signal path of the pad and includes a switch circuit. According to a relationship between voltages of the power supply and the pad of the IO circuit, the switch circuit selectively conducts the impedance path. When the power supply provides power normally, the switch circuit conducts the impedance path to provide a pull-up resistor between the pad and the power supply. When the power supply provides no power and its voltage is lower than a voltage of the pad, the switch circuit disconnects the conducting path to effectively reduce power leakage.

Abstract: A method of designing an integrated circuit, integrated circuits using different drive strengths and a signal integrity monitor are provide herein. In one embodiment, the signal integrity monitor includes: (1) a signal interface configured to receive a signal from a parallel data bus for transmission over a plurality of signal paths and (2) a victim signal identifier configured to dynamically determine a potential victim signal path of the plurality of signal paths.

Abstract: A detector circuit is disclosed that detects bus signal conditions. To detect a START condition, asynchronous sequential logic detects a first bus signal transition (e.g., from high to low) and a second bus signal (e.g., a high signal). The outputs of the asynchronous sequential logic are combined to produce a START signal that can be latched, so that the START signal can be used to wake up a system or for other purposes. To detect a STOP condition, asynchronous sequential logic is set by a transition (e.g., low to high) of the first bus signal and a second bus signal (e.g., a high signal), producing a STOP signal that can be used to reset the asynchronous sequential logic and the latch.

Abstract: A method for adaptively driving data transmission and a communication device using the same are provided. The proposed method includes following procedures. Detection result is generated after detecting a receiving signal on a receiving path of the communication device. Driving parameter is generated according to the detection result. Finally, a transmitting signal on a transmitting path is adjusted according to the driving parameter.

Abstract: A circuit includes first and second bidirectional clock networks and first and second clock signal generation circuits. A first multiplexer circuit is configurable to provide a first clock signal from a first pin to the first bidirectional clock network. A second multiplexer circuit is configurable to provide the first clock signal from the first bidirectional clock network to the second bidirectional clock network. Third multiplexer circuits are configurable to provide the first clock signal from the second bidirectional clock network to the first and the second clock signal generation circuits.

Abstract: A current-limiting device may be configured to be placed along a power-supply bus to limit current through a first complimentary-metal-oxide semiconductor (CMOS) circuit coupled to the power-supply bus so that current does not exceed a trigger current level of a pnpn diode in a second CMOS circuit coupled to the power bus.

Abstract: Devices and circuits for wiring configurations of a bus system and power supply wires in a memory chip with improved power efficiencies. The effective resistance on the power supply wires may be reduced by utilizing non-active bus wires as additional power wires connected in parallel with the other supply wires. The non-active bus wires may reduce or prevent parasitic couplings and cross-talk effects between neighboring sensitive wires, thereby improving performance of the chip.

Abstract: A device for sensing a binary signal includes a device configured to measure a signal level of the signal, a device configured to determine whether the measured signal level is “low” or “high”, a device configured to provide a variable input impedance, and a device configured to control the input impedance in response to the measured signal level. The variable input impedance may be provided by way of a transistor and a resistor, and by controlling the duty ratio of the transistor using pulse width modulation. Preferably, the input impedance is controlled to be low for low signal levels and to be high for high signal levels, which results in a more reliable sensing of binary signals. The device may be used for detecting the state of contact transducers suffering from parasitic resistances caused by moist and/or polluted environments. Further, a method of sensing a binary signal is provided.

Abstract: A method and circuit for implementing calibration of a linearly weighted, thermal coded I/O driver output stage, and a design structure on which the subject circuit resides are provided. The circuit includes a PFET calibration impedance matching function determining calibration PVTP bits for calibrating output stage PFETs of the linearly weighted, thermal coded I/O driver output stage, an NFET calibration impedance matching function determining calibration bits PVTN for calibrating output stage NFETs of the linearly weighted, thermal coded I/O driver output stage once the PFET calibration is complete and an output latch function providing the calibration PVTP and PVTN outputs for the I/O driver output stage to match an impedance of an external calibration resistor. A clock logic function generates an output latch clock and an internal reset signal completing calibration.

Abstract: Disclosed is a system and method for providing Process-Voltage-Temperature (PVT) compensation for an Input/Output interface. An embodiment may connect an analog section and a digital section together to generate and measure an oscillation frequency (FOSC) used to look up a corresponding PVT control bit value in a look-up table. The analog section may be comprised of a voltage reduction system that reduces a bandgap reference voltage (VBGR) to half the supplied VBGR to a current mirror that supplies a PVT current (IPVT) to driver bit cells and a proportional mirrored control current (ICNTL) to a current controlled oscillator (CCO), which generates FOSC. The digital section may be used in combination with a frequency variable resistor and beta multiplier connected to the CCO to calibrate the capacitance of the CCO to tune out the process variation of the CCO capacitance and render FOSC to be linearly dependent on ICNTL.

Abstract: A semiconductor device has a first controlled chip, including a first replica output circuit having the same configuration as a first output circuit, a first ZQ terminal connected to the first replica output circuit, a first through electrode connected to the first ZQ terminal, and a first control circuit which sets the impedance of the first replica output circuit. A control chip includes a second ZQ terminal connected to the first through electrode, a comparator circuit which compares a voltage of the second ZQ terminal with a reference voltage, and a second control circuit 123 which performs a process based on a comparison by the comparator circuit. The first control circuit and the second control circuit receive a common input signal to operate and sequentially change and set the impedance until the comparison result changes when an external resistance element is connected to the second ZQ terminal.

Abstract: A common mode control circuit (400) for generating a control signal indicative of a common mode signal in first and second signals of a differential signal pair comprises a first charge control means (300) for varying, dependent on polarity of the first and second signals with respect to a threshold, charge on a capacitive element (250, 260, 270). The first charge control means (300) is operable to, in response to the first and second signals both switching polarity simultaneously from opposite polarities, maintain a direction of flow of the charge. The first charge control means (300) can be operable to, in response to the first and second signals both switching polarity simultaneously from opposite polarities and the flow of charge being zero, maintain the flow at zero.

Abstract: A logic signal isolator comprising a transformer having a primary winding and a secondary winding; a transmitter circuit which drives said primary winding in response to a received logic signal, such that in response to a first type of edge in the logic signal, a signal of a first predetermined type is supplied to the primary winding and in response to a second type of edge in the logic signal, a signal of a second predetermined type is supplied to said primary winding, the primary winding and the transmitter being referenced to a first ground; and the secondary winding being referenced to a second ground which is galvanically isolated from the first ground and said secondary winding supplying to a receiver circuit signals received in correspondence to the signals provided to the primary winding, the receiver reconstructing the received logic signal from the received signals.

Abstract: An electronic apparatus is provided with an arrangement of discrete circuit elements designed to reduce power consumption. Such an arrangement comprises a memory; a memory controller to generate a control signal which controls the memory according to a predetermined operating clock; and a transmission line disposed between the memory controller and the memory to allow the control signal to be transmitted to the memory, wherein the timing of the control signal is controlled by a change of the operating clock.