Abstract: With conventional redrivers used for external Serial Advanced Technology Attachment (eSATA), there is no ability to indicated to a host that an external device (like a hard disk drive) is not present. As a result, power is consumed by a host because of nearly continual transmission of communication reset signals. Here, a redriver has been provided that includes a cable disconnect terminal and circuitry within a controller that is able to detect whether an external device is present. This redriver enables a host to be powered down or placed in a low power mode while also enabling the use an eSATA compliant connector.

Abstract: An apparatus having a plurality of power supply domains and a plurality of logic components. Each of the plurality of logic components residing within a different one of the plurality of power supply domains. Each of the plurality of logic components is configured to operate with a corresponding clock signal within a respective one of the plurality of power supply domains.

Abstract: A logic signal isolator comprising a transformer having a primary winding and a secondary winding; a transmitter circuit which drives said primary winding in response to a received logic signal, such that in response to a first type of edge in the logic signal, a signal of a first predetermined type is supplied to the primary winding and in response to a second type of edge in the logic signal, a signal of a second predetermined type is supplied to said primary winding, the primary winding and the transmitter being referenced to a first ground; and the secondary winding being referenced to a second ground which is galvanically isolated from the first ground and said secondary winding supplying to a receiver circuit signals received in correspondence to the signals provided to the primary winding, the receiver reconstructing the received logic signal from the received signals.

Abstract: A system comprises a first signal processing logic module and at least one further signal processing logic module. The system further comprises mismatch handler logic module arranged to detect a mismatch between outputs of the first and at least one further signal processing logic module, the mismatch between outputs indicating a failed operation. The mismatch handler logic module further arranged, upon detection of a mismatch between outputs of the first and at least one further signal processing logic module, to analyse internal states of the first and at least one further signal processing logic module, determine whether the cause of the output mismatch is due to a transient fault, and upon determination that the cause of the output mismatch is due to a transient fault, to re-synchronise the first and at least one further signal processing logic module.

Abstract: In one embodiment, a power domain isolation interface is disclosed. The interface has a level shifter having a signal input coupled to a first power domain and a memory element. The memory element has a signal input coupled to an output of the level shifter, an output coupled to a second power domain, and a hold enable input, wherein the memory element is configured to hold an input state when the hold enable input becomes asserted.

Abstract: A Multi-Threshold CMOS NULL Convention Logic asynchronous circuit (MTNCL). The MTNCL circuit provides delay-insensitive logic operation with significant leakage power and active energy reduction. The MTNCL circuit is also capable of functioning properly under extreme supply voltage scaling down to the sub-threshold region for further power reduction. Four MTNCL architectures and four MTNCL threshold gate designs offer an asynchronous logic design methodology for glitch-free, ultra-low power, and faster circuits without area overhead.

Abstract: A circuit arrangement (10) comprises a circuit terminal (11) for supplying a data signal (DATA) having digital information, a logic circuit (12) that is coupled at an input (22) to the circuit terminal (11) for supplying the digital information, an activation circuit (13), and a voltage regulator (14) that is coupled for activation to an output (18) of the activation circuit (13). The activation circuit (13) comprises an input (16) that is coupled to the circuit terminal (11), a delay element (17) that is coupled to the input (16) of the activation circuit (13), and the output (18), connected to the delay element (17), for emitting an activation signal (SON).

Abstract: A system comprises signal paths. There are first through n signal paths, n being a positive integer. A critical one of the first through n signal paths is based on being a respective one of the first through n signal paths having a slowest signal propagation and/or a path in which a signal propagates slower than a clock cycle. The critical one of the first through n signal paths comprises a first size of a standard cell including corresponding logic devices. The non-critical ones of the first through n signal paths comprise a second size of a standard cell including corresponding logic devices, the second size being smaller than the first size.

Abstract: A drive circuit for a power switch component.

Abstract: The invention relates to an interfacing device for pseudo-differential transmission through interconnections used for sending a plurality of electrical signals. The interfacing device of the invention includes signal terminals and a common terminal. A transmitting circuit receives the input signals of the transmitting circuit coming from a source. The output of the transmitting circuit delivers, when the transmitting circuit is in the activated state, voltages between one of said signal terminals and said common terminal. A receiving circuit delivers, when the receiving circuit is in the activated state, output signals of the receiving circuit determined each by the voltage between one of the signal terminals and the common terminal, to the destination. The balancing circuit is such that, when the transmitting circuit is in the activated state, the current flowing out of the common terminal approximates the opposite of the sum of the currents flowing out of the signal terminals.

Abstract: It is presented a gate driver circuit for driving an electric switch, the switch being arranged to control a main current using a gate signal. The gate driver circuit comprises: a non-linear capacitor means having a lower capacitance when an applied voltage is under a threshold voltage and a higher capacitance when an applied voltage is over the threshold voltage, wherein the non-linear capacitor is arranged to be connected between a high voltage connection point of the switch and a connection point for the gate signal; a current change rate sensor, the current change rate sensor being configured to detect changes in a main current of the electric switch and to control a gate signal of the electric switch depending on the current change; a gate buffer; and at least one current source, arranged to drive the gate buffer. The current change rate sensor is connected to control the current source to thereby control the gate signal of the electric switch.

Abstract: An output circuit having a variable swing level of a terminated output data signal is disclosed. The output circuit includes a control circuit configured to generate a first control signal and a second control signal in response to a voltage swing level selection signal and an output enable signal. The output circuit further includes an output driving circuit configured to, in response to the first and second control signals, perform on-die termination in an input mode and configured to control swing level of a signal output from the output circuit in an output mode.

Abstract: An electronic device designed to transport digital information (“0”, “1”) over long distances, including a transmitter generating current pulses and at least one assembly of receivers converting the received current pulses into logic pulses which are compatible with the operation of standard electronic logic circuits. Each receiver includes a pair of magnetoresistive stacks containing at least one hard ferromagnetic layer and one soft ferromagnetic layer separated by a non-ferromagnetic interlayer, the hard layer of each of the magnetoresistive stacks being pinned in a magnetic orientation perpendicular to an easy-magnetization axis which is used as a reference for the soft layer of the same stack. The soft layer of each magnetoresistive stack has a magnetic orientation which can be modulated by the magnetic field generated by current pulses delivered by the transmitter so as to cause modification of the transverse resistance of the stack sufficient to trigger an electrical signal.

Abstract: A data transmission circuit includes a data transmission unit and a data receiving unit. The data transmission unit generates transmission data based on first chip data and transmit the transmission data via a Through Silicon Via (TSV). The data receiving unit differentially amplifies the transmission data with respect to a reference voltage to generate second chip data.

Abstract: An integrated circuit capable of dual configuration of data flow and operable in a plurality of operational modes is provided. The circuit includes eight corner pins, wherein the eight corner pins comprise a first corner pin and a second corner pin on each side of the circuit in each of four side sets, wherein a first corner pin of one side of the circuit is proximate and adjacent to a second corner pin of an adjacent side counterclockwise from the first corner pin and together constitute a paired corner set, each paired corner set comprising a differential input and a differential output.

Abstract: A logic signal isolator comprising a transformer having a primary winding and a secondary winding; a transmitter circuit which drives said primary winding in response to a received logic signal, such that in response to a first type of edge in the logic signal, a signal of a first predetermined type is supplied to the primary winding and in response to a second type of edge in the logic signal, a signal of a second predetermined type is supplied to said primary winding, the primary winding and the transmitter being referenced to a first ground; and the secondary winding being referenced to a second ground which is galvanically isolated from the first ground and said secondary winding supplying to a receiver circuit signals received in correspondence to the signals provided to the primary winding, the receiver reconstructing the received logic signal from the received signals.

Abstract: In an output circuit having a de-emphasis for use in high-speed serial transmission, a circuit for suppressing a fluctuation of a common mode potential which occurs in output amplitude is provided. A positive pole and a negative pole of an output circuit in a serial transmission device for differential transmission having de-emphasis are connected to the respective outputs of a differential circuit that differentially receives outputs of a detector device for a pattern of data to be transmitted, and a detector device for an inverted pattern of the data to be transmitted. When a specific pattern of data to be transmitted and its reverted pattern appear, a current of the output circuit is compensated by the connected differential circuit, thereby enabling a common mode noise to be prevented.

Abstract: A data transmission circuit includes a data transmission unit and a data receiving unit. The data transmission unit generates transmission data based on first chip data and transmit the transmission data via a Through Silicon Via (TSV). The data receiving unit differentially amplifies the transmission data with respect to a reference voltage to generate second chip data.

Abstract: A system and method to operate an electronic device, such as a memory chip, with an output driver circuit that is configured to include an ODT (On-Die Termination) mode detector detects whether there is sufficient internal clocking available to operate the ODT portion in the output driver in the synchronous mode of operation or to switch the operation to the asynchronous mode. The clock-sufficiency based determination of internal ODT mode of operation (synchronous vs. asynchronous) avoids utilization of complex and inflexible clock processing logic in an ODT control unit in the output driver. This enables the actual clocking to the ODT circuitry to be changed during various device operational modes (e.g., active, power down, etc.) without re-designing the ODT control logic for each of those modes. The simplicity and flexibility of the ODT mode detector design allows for efficient use of chip real estate without affecting the signal transfer speed of the output driver in the electronic device.

Abstract: A method for a mix mode driver to accommodate traces of different lengths includes storing in the mix mode driver a set of one or more control signals and coefficient signals for a trace length. The one or more control signals select a number of the stages to generate a variable amplitude data output signal. Each stage is operable to increase or decrease a data signal, and each of the coefficient signals determines the magnitude of increase or decrease of the data input signal by a stage. A method for operating the mix mode driver includes generating the variable amplitude data output signal with one or more of the stages, and providing the variable amplitude data output signal to a trace.

Abstract: A chip is provided with a specific signal wire and two adjacent signal wires. Output signals based on a specific signal and two adjacent signals are transmitted to the specific signal wire and the two adjacent signal wires respectively. An adjustment coefficient is stored in a memory. The adjustment coefficient is used for reducing an occurrence amount of crosstalk arising between the specific signal wire and the two adjacent signal wires. An adjustment quantity calculation portion calculates an adjustment quantity representing a degree of decrease of a slew rate of the specific signal, based on the adjustment coefficient, the specific signal and the two adjacent signals. A driver adjusts the slew rate of the specific signal based on the adjustment quantity and to transmit one of the output signals corresponding to the specific signal.

Abstract: A multi-interface integrated circuit (IC) comprises a plurality of transistors, and a level detection block. At least one transistor of the plurality of transistors is in communication with a first terminal and either a first or a second lead of the multi-interface IC, and at least one of the plurality of transistors is in communication with the first terminal, a second terminal and either the first or a second lead of the multi-interface IC. The level detection block is in communication with at least one of the plurality of transistors and the first and second leads.

Abstract: A system for reducing electromagnetic interference and ground bounce in an information communication system includes a plurality of information communication devices. Each of the plurality of information communication devices is responsive to a respective information communication clock signal. Each information communication clock signal of each of the plurality of information communication devices is associated with a common reference clock signal. The system includes a phase controller. The phase controller is responsive to the common reference clock signal. The phase controller alters a phase of each information communication clock signal of each of the plurality of information communication devices by a predetermined amount.

Abstract: In order to prevent malfunction due to fluctuations in signal level, a terminating resistor circuit includes terminating resistors the connections whereof to an input/output terminal are capable of being turned on and off, whereby a Thevenin termination is formed. A control circuit exercises control so as to temporally stagger on/off timings of respective ones of the terminating resistors.

Abstract: According to one general aspect, an apparatus may include a clock channel, a shielding tunnel, and clock repeaters. In various embodiments, the clock channel may be configured to carry the clock signal, and may include a portion of a metal layer of an integrated circuit. In some embodiments, the shielding tunnel may be configured to shield, in at least four directions, the clock channel from other signals, and may include portions of a at least three metal layers of the integrated circuit. The shielding tunnel may be connected to the positive and negative supplies in order to provide the required power for the clock repeaters.

Abstract: A method for single event transient filtering in an integrated circuit device is described. The device comprises three sequential elements, each having a data input and a data output with each of the three data outputs coupled to one of three inputs of a voting gate. The method comprises generating first and second nominally equivalent logic signals in first and second SET domains, converting the first and second nominally equivalent logic signals into first, second and third nominally equivalent data channels, and transmitting the first, second and third nominally equivalent data channels to the data inputs of the first, second and third sequential elements.

Abstract: A noise filter circuit includes a first inverter circuit that receives a signal based on an input signal, a second inverter circuit that receives a signal based on the input signal, and a latch circuit that receives signals based on a signal output from the first inverter circuit and a signal based on a signal output from the second inverter circuit as a set signal and a reset signal. Each of the first inverter circuit and the second inverter circuit includes a first-conductivity-type transistor and a second-conductivity-type transistor, the capability of one of the first-conductivity-type transistor and the second-conductivity-type transistor being lower than the capability of the other of the first-conductivity-type transistor and the second-conductivity-type transistor.

Abstract: In a calibration control circuit, a first clock gate circuit restricts passage of reference update clocks during a calibration period so as to stop a first one of the reference update clocks and supplies the restricted reference update clocks as first update clocks CLK1 to both a hit determination circuit and a second clock gate circuit. The second clock gate circuit 110 passes through the first update clocks CLK1 until reception of a hit signal from the hit determination circuit and delivers second update clocks CLK2 to an up/down counter 106. The up/down counter 106 is operated by the second update clocks CLK2. With this structure, the second update clocks used for adjustment steps can be increased in number during the calibration period.

Abstract: Off-die termination module for terminating memory module signal lines in a computer memory subsystem, the computer memory subsystem including a memory controller and a DIMM socket, the memory controller coupled to the DIMM socket via a memory module signal line, the off-die termination module including: an off-die termination component configured to terminate the memory module signal line upon activation; and a spring loaded notch pin implemented as part of the DIMM socket, the spring loaded notch pin configured to toggle activation of the off-die termination component in dependence upon presence of a DIMM in the DIMM socket including activating the off-die termination component upon removal of a DIMM from the DIMM socket and deactivating the off-die termination component upon installation of a DIMM in the DIMM socket.

Abstract: Off-die termination of memory module signal lines in a computer memory subsystem. The computer memory subsystem includes a memory controller and a DIMM socket installed on a PCB. The memory controller is electrically coupled to the DIMM socket via a memory module signal line. Off-die termination includes detecting, by a termination controller installed on the PCB, no presence of a DIMM in the DIMM socket and, responsive to the detection, activating, by the termination controller, an off-die termination component on the PCB to terminate the memory module signal line.

Abstract: An arrangement and method of reducing power in bidirectional I/O ports includes driving an input signal from an I/O port by asserting a high impedance (Hi-Z) signal to an output drive, driving an output signal from the I/O port by refraining from asserting a Hi-Z signal to an output driver, and feeding back the output signal to an input driver when driving the output signal. The method can float the I/O port when the Hi-Z signal is asserted on the output driver or drive the I/O port as an input when the Hi-Z signal is asserted on the output driver. The method can refrain from floating a signal back into the I/O port when driving a signal out by driving a constant logical zero back into the I/O port or driving a constant logical one back or by maintaining a last value driven.

Abstract: The present invention provides a precisely controlled terminator circuit of a differential amplifier, in particular, for a differential amplifier of an optical receiver. The differential circuit, which receives a differential signal by a first input for the normal phase signal and a second input for an anti-phase signal, provides a terminator circuit comprises two resistors connected in serial between two inputs and two resistive connections each including a transistor and a resistor serially connected to the transistor and connected between respective inputs and the power supply line Vcc. The control unit, by receiving a medium potential of two resistors, provides a bias to two transistors so as to equalize the medium potential with the reference potential.

Abstract: According to one general aspect, an apparatus may include a clock channel, a shielding tunnel, and clock repeaters. In various embodiments, the clock channel may be configured to carry the clock signal, and may include a portion of a metal layer of an integrated circuit. In some embodiments, the shielding tunnel may be configured to shield, in at least four directions, the clock channel from other signals, and may include portions of a at least three metal layers of the integrated circuit. The shielding tunnel may be connected to the positive and negative supplies in order to provide the required power for the clock repeaters.

Abstract: A method and apparatus is described herein for pulse shift modulation of output waveforms for reducing crosstalk on interconnects. Based on input pulses/bits, an output waveform is selectively delayed by a shift value to ensure transitions in a first direction occur in a first half of a period and transitions in a second direction occur in a second half of the period. When the same pulse shift modulation is implemented on surrounding traces, certain worst-case crosstalk scenarios are reduced; thus reducing crosstalk and increasing performance in power consumption and speed of data transfer.

Abstract: On die termination (ODT) device that can reduce the number of lines for transferring calibration codes to reduce the size of a chip including the ODT device. The ODT device includes a calibration circuit configured to generate calibration codes for determining a termination resistance, a counting circuit configured to generate counting codes increasing with time. A transferring circuit of the device is configured sequentially to transfer the calibration codes in response to the counting codes. A receiving circuit is configured sequentially to receive the calibration codes from the transferring circuit in response to the counting codes. A termination resistance circuit of the device is configured to perform impedance matching using a resistance determined according to the calibration codes.

Abstract: In some embodiments, an array of sleep transistors is provided, wherein a combination of said transistors may be enabled during an active mode to reduce leakage depending on the leakage characteristics of a chip or associated chip.

Abstract: A circuit topology for multiple loads includes a driving terminal for transmitting a driving signal, a number of transmitting lines, and a number of loads operable to receive the driving signal from the driving terminal. The number of loads are connected to the driving terminal one by one via the number of transmitting lines. Two transmitting lines of the number of transmitting lines, which are nearest and farthest respectively from the driving terminal, are both greater than widths of the other transmitting lines.

Abstract: Apparatus controlling the driver output slew rate that includes a driver circuit having an input signal and an output signal, where the driver circuit is structured and arranged to facilitate control of the slew rate of the output signal. A delay circuit having a time delay proportional to a desired transition time of the driver output signal is coupled to the output of the driver circuit. A first comparator detects when the driver output signal rises through a specified level, and a second comparator detects when the driver output falls through a second specified level. A phase detector is coupled to outputs of the first and second comparators and an output of the delay circuit for aligning the phases of the comparator outputs and the delayed comparator outputs by adjusting the driver output slew rate.

Abstract: This invention is a method of operating a system having multiple finite state machines where each finite state machine generating a ready signal when its operation is complete. This invention senses the multiple ready signals and waits until all the finite state machines generate the ready signal. This waiting can be accomplished with a precharge-conditional discharge circuit used for voting.

Abstract: The present invention provides a differential signaling system comprising: a driver circuit that transmits a differential signal; a receiver circuit that receives the differential signal; and two or more signal lines used for the differential signal to be transmitted by the driver circuit and received by the receiver circuit, wherein the driver circuit gives an arbitrary time lag between the two signals that form the differential signal before transmitting them.

Abstract: A method for single event transient filtering in an integrated circuit device is described. The device comprises three sequential elements, each having a data input and a data output with each of the three data outputs coupled to one of three inputs of a voting gate. The method comprises generating first and second nominally equivalent logic signals in first and second SET domains, converting the first and second nominally equivalent logic signals into first, second and third nominally equivalent data channels, and transmitting the first, second and third nominally equivalent data channels to the data inputs of the first, second and third sequential elements.

Abstract: A complementary field-effect (CMOS) circuit is provided which includes a current-limiting device arranged along a power-supply bus or a ground bus of the circuit. The current-limiting device is configured to prevent latch up of the CMOS circuit. More specifically, the current-limiting device is configured to maintain a junction of the parasitic pnpn diode structure as reverse-biased. A method is also provided which includes creating a current-voltage plot of a pnpn diode arranged within a first CMOS circuit which is absent of a current-limiting device arranged along a power bus of the circuit. In addition, the method includes determining a holding current level from the current-voltage plot and sizing a current-limiting device to place along a power bus of a second CMOS circuit comprising similar design specifications as the first CMOS circuit such that the current through the second CMOS circuit does not exceed the holding current level.

Abstract: A method and apparatus for setting a sampling point of a low voltage differential signal transmitted between Field Programmable Gate Arrays (FPGAs) are provided. The method includes determining in which one a maintenance section or a transition section of a received signal of an initial sampling point is located in, determining a first boundary by shifting the received signal in a first direction if the initial sampling point is located in the maintenance section, determining a second boundary by shifting the first shifted signal in a second direction, and determining a sampling point for determining a sampling reference signal by shifting the second shifted signal in the first direction so that the sampling point may be located at a central position between the first and second boundaries. The method can guarantee the reliability of a data reception by preventing a signal distortion when determining a sampling point in case where the FPGA receives data at a high rate through existing input/output devices.

Abstract: Disclosed are a method, system and apparatus for an improved fail safe I/O driver with pad feedback slew rate control are disclosed. In one embodiment, a pad driver circuit includes a pad node, an NMOS component, a feedback capacitor between the pad node and a gate of the NMOS component to control slew rate across a range of capacitor loads, a switch circuit between the pad node and the feedback capacitor, and a signal generator to generate a signal to control the switch circuit. The switch circuit to maintain a main driver circuit and a pre-driver circuit of the pad driver circuit in a fail safe state when an integrated circuit that includes the pad driver circuit is in the fail safe state. The pad driver circuit may include a PMOS component.

Abstract: An IC uses a tunable interconnect driver between a data source and a data destination to selectively slow down (“de-tune”) data signals. Data sent along relatively short paths are de-tuned to reduce power supply noise during synchronous switching events. In some embodiments, the tunable interconnect driver delays data transmission relative to an un-delayed signal path, in other embodiments, the slew rate of the tunable interconnect driver is selectively reduced.

Abstract: A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends to either another transmission line or one of the memory devices. The branches are arranged in several layers of hierarchy, with the transmission lines in branches having the same hierarchy having the same length. Each transmission line preferably has a characteristic impedance that is half the characteristic impedance of any pair of downstream transmission lines to which it is coupled to provide impedance matching. A dedicated transmission line is used to couple an additional memory device, which may or may not be an error checking memory device, to the register.

Abstract: A logic signal isolator comprising a transformer having a primary winding and a secondary winding; a transmitter circuit which drives said primary winding in response to a received logic signal, such that in response to a first type of edge in the logic signal, a signal of a first predetermined type is supplied to the primary winding and in response to a second type of edge in the logic signal, a signal of a second predetermined type is supplied to said primary winding, the primary winding and the transmitter being referenced to a first ground; and the secondary winding being referenced to a second ground which is galvanically isolated from the first ground and said secondary winding supplying to a receiver circuit signals received in correspondence to the signals provided to the primary winding, the receiver reconstructing the received logic signal from the received signals.

Abstract: A system including a preemphasis driver circuit and a method. One embodiment includes an output terminal, a main driver coupled between the input terminal and the output terminal and an auxiliary driver coupled to the output terminal, wherein at least one unclocked delay element is coupled between the input terminal and the auxiliary driver.

Abstract: A logic signal isolator including a micro-transformer with a primary winding and a secondary winding. A transmitter circuit drives the primary winding in response to a received input logic signal such that, in response to a first type of edge in the logic signal, at least a first amplitude signal is supplied to the primary winding and, in response to a second type of edge in the logic signal, a second different amplitude signal is supplied to the primary winding. A receiver circuit receives corresponding first amplitude and second amplitude signals from the secondary winding and reconstructs the received logic input signal from the received signals.

Abstract: A circuit for attaining reduction in AC noise on power supply line caused by IR drop upon use of a decoupling capacitor represented by a cross-coupled decoupling capacitor with enhanced resistance to electrostatic breakdown, required in the case of a process of a high technology. There is also provided a circuit for suppressing the AC noise on power supply line due to resonance. MOS transistors composing the cross-coupled decoupling capacitor with enhanced resistance to electrostatic breakdown are caused to have lower threshold voltages Vth, thereby reducing a resistance between a source and a drain of each of the MOS transistors, resulting in reduction in IR drop. Further, a damping resistance is effective for suppressing the AC noise on power supply line, and the source-to-drain resistance of each of the MOS transistors is utilized as the damping resistance.