Abstract: A television broadcast receiving apparatus has a demodulating unit including a PLL part synchronizing a phase of an IF signal with a phase of an internally generated carrier signal and outputting an out-of-synchronization flag signal when the IF signal and the carrier signal are in an unsynchronized state, and a muting part muting a sound intermediate frequency signal and outputting a noise signal of a predetermined level when the out-of-synchronization flag signal is outputted from the PLL part. Therefore, even when an IF amplifier of a tuning unit amplifies a noise at the maximum gain when there is no signal, an abnormal sound can be prevented from being outputted from a speaker of a decode and output unit.

Abstract: An integrated video clock signal generator in which a master phase-locked loop (PLL) control circuit uses an off-chip voltage-controlled oscillator (VCO) to produce an on-chip oscillator signal in synchronization with a horizontal reference signal related to a horizontal video synchronization signal. This on-chip oscillator signal drives one or more slave PLL circuits which provide respective one or more on-chip PLL signals synchronized with the on-chip oscillator signal. In accordance with a preferred embodiment, each on-chip PLL signal is a pixel clock signal with a plurality of clock signal pulses which is synchronized with a vertical reference signal related to a vertical video synchronization signal.

Abstract: An apparatus having a complex sine wave generating circuit (3) that generates a complex sine wave, a multiplying circuit (4) that multiplies an input signal by the complex sine wave, a first integrating circuit (5) that integrates the product obtained by the multiplying circuit (4) in the time direction, a first squaring circuit (6) that takes the square of the absolute value of a complex signal output by the first integrating circuit (5), a second squaring circuit (7) that takes the square of the absolute value of the instantaneous amplitude of the input signal, a second integrating circuit (8) that integrates the results obtained by the second squaring circuit (7) in the time direction, and a frequency difference calculating circuit (9) that finds the difference between the frequency of the input signal and the oscillation frequency of the complex sine wave on the basis of the ratio between the output signal level of the first squaring circuit (6) and the output signal level of the second integrating circui

Abstract: In the course of the channel presetting process, the central frequency is set by a step of 1 MHz within the range from the minimum frequency in the VHF band channel plan to the maximum frequency of the VHF band adopted in the place of destination for the scheduled shipment of the TV broadcast receivers, attempts are made to detect broadcast signals by changing frequency within a range of 1.5 MHz to the high frequency side and 0.5 MHz to the low frequency side from the central frequency, and the frequencies of the detected broadcast signals are stored in the semiconductor memory.

Abstract: A PLL control circuit of an optical disc apparatus comprising: a voltage frequency conversion circuit that adjusts an oscillating frequency based on a control voltage to generate a first frequency signal; a phase comparison circuit that compares the phase of the first frequency signal with the phase of a second frequency signal generated based on an RF (Radio Frequency) signal at the time of photoelectric conversion of reflected light of the laser beam applied to an optical disc, to generate a phase difference signal indicating a phase difference between the first frequency signal and the second frequency signal; a charge pump circuit that generates the control voltage for synchronizing the phases of the first frequency signal and the second frequency signal according to the phase difference signal; a first detection circuit that detects whether the RF signal exceeds a predetermined level; a second detection circuit that detects whether the phases of the first frequency signal and the second frequency signal

Abstract: System and method for synchronizing the low speed mirror movement of a mirror display system with incoming frame or video signals, and synchronizing buffered lines of video data to the independently oscillating scanning mirror. According to one embodiment of the invention, the peak portions of the low speed cyclic drive signal are synchronized with the incoming frames of video by compressing or expanding the peak portion or turn around portion so that each video frame begins at the same location on the display screen. The actual position of the high frequency mirror is determined by sensors and a “trigger” signal is generated to distribute the signals for each scan line such that the scan lines are properly positioned on the display.

Abstract: In various implementations, a re-configurable phase lock loop may have multiple signal paths, including a feedforward path to operate in a carrier frequency acquisition mode to obtain a carrier frequency estimate and a feedback loop path to operate in a carrier frequency tracking mode to translate an incoming signal to a baseband signal. The multiple signal paths may share most of the hardware to reduce implementation cost.

Abstract: A display drive integrated circuit is for driving a display panel. The display drive integrated circuit includes a division rate output unit which outputs as a division rate corresponding to a quotient obtained by dividing by M a total number of clock cycles of a dot clock signal corresponding to a clock cycle of a horizontal synchronization signal, where M is a natural number, and a system clock generating unit which generates a system clock signal by dividing the dot clock signal using the division rate.

Abstract: A method for generating a video clock and an associated target image frame is disclosed. The method generates an output clock signal for outputting a target image frame to a panel according to a frame pixel number and a vertical synchronization signal (Vsync). The target image frame corresponds to a source image frame. The frame pixel number is the number of total pixels included in a predetermined frame format, and the Vsync signal is an input Vsync signal or an output Vsync signal. The period of the output clock signal is the result of the period of the Vsync divided by the frame pixel number. In this manner, the format of the target image frame can remain substantially fixed, and is substantially equal to the predetermined frame format.

Abstract: In order to further develop a circuit arrangement (100; 102; 104; 106) and a method of locking onto and/or processing data, in particular audio, television and/or video data, by means of at least one phase locked loop (40), wherein phase information is detected by means of at least one phase detector (44), in particular following the arrival of at least one rising edge and/or falling edge of at least one analog input signal (50; 50), at least one increment (24) is determined by means of at least one loop filter (30), to which the output signal (56) which is output by the phase detector (44) is fed, and at least one ramp oscillator (46) is fed the increment (24) which is output by the loop filter (30), such that inter alia the circuit arrangement (100; 102; 104; 106).

Abstract: A source image with an input vertical resolution and an input horizontal resolution is received using an input clock signal. An intermediate image with an output vertical resolution and the input horizontal resolution is generated using an intermediate clock signal by scaling the source image. An output image with the output vertical resolution and an output horizontal resolution is generated using an output clock signal by scaling the intermediate image. The frequency of the intermediate clock signal is equal to the frequency of the output clock signal multiplied by the ratio of the input horizontal resolution to the output horizontal resolution.

Abstract: A video signal processor for processing input video data in accordance with an input clock signal includes: an input section for changing the format of the video data and outputting resultant data; a logic section for decoding the data output from the input section and outputting decoded data; and a frequency detector for detecting that the clock signal has a frequency higher than a given frequency and outputting a result of the detection as a detection signal. When the frequency of the clock signal is higher than the given frequency, operation of at least part of circuits constituting the video signal processor is stopped in accordance with the detection signal.

Abstract: A method and apparatus for an analog-to-digital video signal converter. The converter is controlled by a clock with controllable frequency and phase for sampling an analog signal. A circuit corrects the clock frequency using a period of a columnar frame differences as a function of columnar location. The sampling clock frequency is changed by an amount dependent on the period of the columnar differences. A second measure of the difference between successive frames is computed for a sequence of clock phases. The frequency of the clock is verified using a characteristic of the second measure. The characteristic can be the ratio of the maximum to the minimum of the second measure over selected clock phases. Other characteristics can be used such as a difference of a maximum and a minimum measure.

Abstract: The present invention relates to the domain of video equipment. It relates to a phase-locked loop able to recover the timing of a synchronization signal comprising a temporal discontinuity of a maximum amplitude equal to PCR_Modulus, the loop comprising: a sample comparator comparing the samples and the local samples of a synthesised signal, means for producing the synthesised signal from a corrected signal, a corrector receiving a comparison result delivered by the comparison means and delivering the corrected signal, According to the invention, the comparison means comprises the means to determine a difference in value between the local samples and the samples of the synchronisation signal and in that the comparison result has a value that depends on the value ? and on the difference between the value ? and the value PCR_Modulus/2.

Abstract: A frame-based phase-locked display controller used in a display system and method thereof are described. The frame-based phase-locked display controller for displaying a plurality of image frames in a video signal comprises a frame-based phase-locked loop and a synchronization signal generator. The frame-based phase-locked loop receives an oscillating signal and an input vertical synchronous signal to generate an output clock signal by phase-lock loop based on the frames. The synchronization signal generator, coupled to the frame-based phase-locked loop, receives the output clock signal to generate an output horizontal synchronous signal, an output vertical synchronous signal and an output display enable (DE) signal. The frame-based phase-locked loop comprises a first PLL, a frequency synthesizer, a second PLL, a fast phase detector, a phase frequency detector and an active pixel region generator.

Abstract: Phase trackers (7) for tracking phases of received data are provided with interpolators (20), error detectors (21,22), combiners (25) and indicator generators (26) for generating at least two streams of interpolated samples, for generating error signals per stream, and for generating an indicator signal for adjusting the interpolation, to avoid the use of sync words for phase tracking. The indicator generator (26) converts combined error signals into indicator signals for adjusting the interpolation through shifting sampling phases of interpolated samples.

Abstract: A circuit for generating a timing signal, the circuit having a memory and a pulse generator, the timing signal consisting of a number of pulses. The memory stores pulse count data, including an indication of the number of pulses in the timing signal, and rising edge and falling edge position data of the timing signal. The pulse generator produces the timing signal in accordance with the pulse count data and has a first circuit for generating rising edge signals, a second circuit for generating falling edge signals, an active control circuit for setting, in correspondence only with the pulse count data, corresponding rising edge signals as active state rising edge signals, and corresponding falling edge signals as active state falling edge signals, and a third circuit for generating said timing signal corresponding to the active state rising edge signals and the active state falling edge signals.

Abstract: The present invention concerns a method and apparatus for setting a frequency reference in an integrated receiver decoder (IRD). More specifically, the present invention discloses an electrical circuit arrangement in which the voltage controlled crystal oscillator (VCXO) is set to oscillate at the desired frequency prior to the initial use thereof and that frequency is stored in a non-volatile memory unit. Upon initial use, the IRD receives a data signal corresponding to a frequency reference. The IRD uses a threshold value to compare the frequency reference of the incoming data signal with the frequency stored in the non-volatile memory. If the frequencies differ by a predetermined value, the frequency from the incoming data signal is stored in the non-volatile memory and is used to set the VCXO.

Abstract: A method and apparatus for an analog-to-digital video signal converter. The converter is controlled by a clock with controllable frequency and phase for sampling an analog signal. A measure of the difference between successive frames of the image is computed for a sequence of clock phases. The measure can be a count taken over pixels of the magnitude of the difference between a pixel in one frame and the corresponding pixel in a following frame exceeding a threshold value. The frequency of the clock is verified using a characteristic of the frame difference. The characteristic can be the ratio of the maximum measure to the minimum measure over the selected clock phases. Other characteristics can be used such as a difference of a maximum and a minimum measure.

Abstract: A synchronization pulse representing a symbol boundary in a signal such as an OFDM signal is obtained by deriving a first signal representing the difference between the amplitudes of samples separated by the useful part of an OFDM symbol, a second signal representing the phase difference between the samples, and combining the first and second signals to derive a resultant signal. The resultant signal is examined and the synchronization pulse generated in response to the signal changing in a predetermined manner.

Abstract: A video signal processing apparatus is provided with a first clock generation circuit for generating a first clock synchronized with an input signal; a second clock generation circuit for receiving a set value to be a reference of an output frequency, adding the set value for every reference clock, extracting data according to the cumulative value, converting the data into an analog signal, reducing quantization noise, and multiplying the analog signal, thereby to obtain a second clock; and a clock switch circuit for generating a sync signal that is switched to the second clock, by using a sync signal generated with the first clock; and video signal processing is carried out using the second clock that is generated according to the resolution of a pixel display.

Abstract: The invention relates to a method for combating the copying of source pictures by means of a camera while they are being displayed, for example using a camcorder in a movie theatre. To this end, it is known, in classical projection systems, to modulate by a carrier wave the brightness of some pixels of the pictures. The frequency of the carrier wave is usually constant and generally half the refresh frequency. The main problem with such systems is that once a pirate has figured out what the modulation frequency is, he can configure his camcorder shutter to filter out this frequency and bypass the anti-camcorder method. According to the invention, the frequency of the carrier is changed at least once throughout the displaying of the sequence pictures or the movie, to defeat all camcorders standards (PAL/NTSC) and shutter configurations.

Abstract: In the known color stripe process for preventing recording of video signals, the color burst present on each line of active video is modified so that any subsequent video tape recording of the video signal shows variations in the color fidelity that appear as undesirable bands or stripes of color error. This color stripe process is improved by a combination of modifying the phase of the color burst on only part of the color burst. Additional improvements were obtained by incorporating techniques of widening the normal color burst envelope towards the trailing edge of horizontal sync and towards the beginning of active video. These techniques are useful in improving the performance of the color stripe process in both the NTSC and PAL color systems. However, additional improvements are described in the PAL system whereby the phase modifications are controlled so as to avoid disturbing the so-called PAL ID pulse.

Abstract: An image data decoding method of an image vertical blanking interval (VBI) and device thereof can adjust a run-in clock signal of data lines of teletext to a data phase of teletext data lines. The method can accurately decode data of the teletext data lines to avoid a phase bias and an erroneous decoding result. A main technical method to decode the data of the VBI is to extract the data of the teletext data lines to determine corresponding bit logical values of the image data and then to output a decode result and also output a phase adjustment value. The phase adjustment value is used to adjust a read phase value of the extracted image so as to synchronize a data phase in VBI.

Abstract: In a display state control apparatus for automatically changing the frequency and the phase of a sampling clock signal according to changes in the phase and frequency of an input signal, and in a display state control method therefor, an optimal display state is maintained by automatically changing the frequency and phase of a sampling clock signal used to sample an input signal according to changes in the input signal. In this manner, user interaction is not required for generating the optimal display control signal.

Abstract: A synchronizing signal control circuit includes: a phase detecting section configured to detect a phase difference between a display synchronizing signal and an input synchronizing signal; an adding section configured to add a set value for setting a synchronization compensation period and the detected phase difference; a synchronization phase correcting section configured to correct the phase of the input synchronizing signal on the basis of the output signal of the adding section; a gate signal generating section configured to generate a gate signal representing the synchronization compensation period based on the display synchronizing signal; a synchronization determining section configured to determine whether the synchronization can be effected, by detecting whether the input synchronizing signal exists within the synchronization compensation period; and a selecting section configured to perform switching to the corrected input synchronizing signal on the basis of the determination result of the synchron

Abstract: A method for synchronizing video signals is provided wherein a synchronization state signal is generated which is descriptive for the synchronization of an output of fields/frames with the respective input of respective fields/frames of an underlying video data screen in particular on the basis of a time difference which is given by respective counted times and/or temporal changes and/or variations thereof.

Abstract: An input video signal is inputted into a first clamp circuit, and then inputted into a second clamp circuit as a clamped video signal so as to be inputted into a switch circuit. The second clamp circuit uses a clamp pulse for clamping a video signal within the period of the sync signal that has been created by a clamp timing generator in the rear stage, and outputs a clamped video signal. The video signal has been clamped so as to be pulled into a constant DC voltage, and absorbs the waviness of a sag that superimposes the video signal. This video signal makes it possible to gain a sync output signal which has been sync separated from a sync separator circuit and has no jitter in the output.

Abstract: A video-signal receiving method is provided. First, receive an analog video signal, wherein the analog video signal comprises a specific video signal and a synchronization signal. Next, at least perform an analog-to-digital conversion on the synchronization signal of the analog video signal according to a sampling signal to generate a digital signal. Then, receive the digital signal and decoding the digital signal to obtain a digital synchronization signal corresponding to the synchronization signal. Afterward, adjust a phase of the sampling signal according to the digital synchronization signal.

Abstract: [Problems] To realize a reliable and stable transfer of digital data that does not require a reference clock and a handshake operation. [Means for Solving the Problem] The present invention provides a digital data transfer method for alternately and periodically transferring first information and second information respectively in a first period and in a second period, wherein: an amount of information of the first information per unit time in the first period is greater than an amount of information of the second information per unit time in the second period; and the second information in the first period is transferred as pulse-width-modulated serial data.

Abstract: A method, apparatus, and system for determining a horizontal resolution and a phase of an analog video signal arranged to display a number of scan lines each formed of a number of pixels is described. A number of initialization values are set where at least one of the initialization values is a current horizontal resolution and then a difference value for each immediately adjacent ones of the pixels is determined. Next, an edge flag value based upon the difference value is stored in at least one of a number of accumulators such that when at least one of the accumulators has a stored edge flag value that is substantially greater than those stored edge flag values in the other accumulators, then the horizontal resolution is set to the current resolution.

Abstract: A method and apparatus for a digital video display. A digital display device receives an analog signal representing an image formed of pixels in video lines and a signal containing a synchronization waveform for the image. An analog-to-digital converter (ADC) receives the analog signal and converts it to a sampled digital waveform. A phase-locked loop including a programmable frequency divider controls the sampling time for the ADC. The programmable frequency divider is controlled by a dividing-ratio algorithm that selects a dividing ratio, measures the number of pixels in a video line using the dividing ratio, and recomputes the dividing ratio by multiplying the selected dividing ratio by the expected number of pixels in a video line and dividing by the measured number of pixels. The sampling phase for the ADC is selected by a sampling-phase control algorithm that minimizes a function representative of the flatness of the sampled digital waveform.

Abstract: A method and system for synchronizing video information derived from an asynchronously sampled video signals provide a mechanism for using asynchronous sampling in the front-end of digital video capture systems. A ratio between the sampling clock frequency and the source video clock frequency is computed via an all digital phase-lock loop (ADPLL) and either a video clock is generated from the ratio by another PLL, a number to clock converter or the ratio is used directly to provide digital synchronization information to downstream processing blocks. A sample rate converter (SRC) is provided in an interpolator that either acts as a sample position corrector at the same line rate as the received video, or by introducing an offset in the ADPLL, the video data can be converted to another line rate via the SRC.

Abstract: A video quality adaptive variable-rate buffering method and system for stabilizing a sampled video signal reduces the buffer size required to compensate for line-to-line variations in an unstable video source. A video signal is sampled at a predetermined rate and decimated by a selectable decimation factor prior to buffering. By selecting different decimation factors, the effective length of the buffer is changed from short duration for stable input signals and to longer duration for unstable input signals. A video signal quality detector is employed to provide a selection input that adjusts the decimation factor and also the loop bandwidth of a clock generator that provides the output clock for the buffer, which is generated from the input signal via a phase-lock loop (PLL). The operation of the system automatically varies from highly responsive for stable video input signals to less responsive for unstable video input signals, providing improved stability in the video output.

Abstract: An intended-usage judger judges an intended usage of an inputted digital imaging signal. A selector selects one or a plurality of signals to be inspected from a group of signals constituting the digital imaging signal based on a result of the judgment by the intended-usage judger. A phase adjuster adjusts a phase of a pulse used when the digital imaging signal is picked up based on an output state of the signal to be inspected.

Abstract: Autophase adjustment is initiated in a display device that digitally displays analog video signals. The autophase adjustment is initiated based on monitoring of at least one of the horizontal and vertical synchronization signal pulse rates and polarity. When a change is detected in either of the horizontal and vertical synchronization pulses, an autophase adjustment is automatically initiated. Correct phase settings are obtained from a table of settings cross referenced by the horizontal and vertical synchronization pulse rates and polarity.

Abstract: A multiplexer of a transmission section generates a clock signal by multiplying a reference clock signal of a digital image signal by a predetermined number ‘K’. A parallel digital image signal is converted into a serial digital signal on the basis of the clock signal, and the serial digital signal is converted into an optical signal in an optical transmission section for transmitting. A demultiplexer extracts a reception clock signal from a serial digital reception signal which is converted into an electric signal in an optical reception section of a reception section, the serial digital reception signal is converted into a parallel signal and a signal corresponding to the parallel digital image signal on the basis of the reception clock signal, and a clock signal corresponding to the reference clock signal is recovered by multiplying the reception clock signal by ‘1/K’.

Abstract: A video system comprises a first video device which transmits a video signal comprising image information and synchronisation information and a second video device which receives the composite video signal. The second device has a time base. For synchronising the two devices synchronisation information is extracted from the video signal received by the second Video device and from the time base of the second video device; a phase difference between the video signal received by the second video device and the time base of the second video device is determined based on the extracted synchronisation information; control information of a first type representative of the amount of the phase difference is transmitted to the first device; and in the first device the phase of the video signal is switched by a phase angle represented by the first type control information.

Abstract: The present invention provides a method for reducing analog PLL (Phase-lock loop) jitter in video ADC application. The HSync/CSync is replaced with a faked HSync signal to be inputted to PLL during vertical blank period. Therefore the analog PLL will only see the faked HSync signal of fixed period as a line-lock trigger signal, while no COAST signal is required. Also, the faked HSync is fine-tuned to match with the external HSync/CSync leading edge to minimize PLL jitter.

Abstract: The timing adjustment unit gives a phase adjustment instruction of the pulse to the imaging device so as to converge to an optimum phase of the pulse set based on the calculation results of the luminance level detecting unit and the variance calculating unit. Furthermore, the timing adjustment unit controls the imaging device so that an exposure state of the analog imaged signal is suited for a luminance level detection process by the luminance level detecting unit and the variance calculation process by the variance calculating unit.

Abstract: Method and system for fine tuning frequency and phase of a sampling clock of analog signals (R, G, B) having digital information, for sampling the analog signals within an optimal sampling period, enabling optimal display by a digital display device (92). Small amount of information from input signals is required for rapidly and accurately determining values of frequency and phase of the sampling clock. After measuring using a measurement system (96) and obtaining pixel values while sweeping phase values of signals using a phase locked loop (PLL) mechanism (48), there is determining values of two parameters, (i) error of an initial frequency value of the sampling clock (Rx clock), proportional to error of an initial phase locked loop (PLL) division factor value, and (ii) phase of the sampling clock, without need for making additional measurements based on these values, using a control unit (94).

Abstract: A video decoder in which the video source clock is generated entirely in the digital domain is disclosed herein. By creating a virtual version of the source clock in a numeric oscillator, the amount of noise in the system is substantially reduced. Furthermore, by transferring the digitized video signal, sampled with an asynchronous crystal clock, into the source clock domain, the accuracy of the brightness (amplitude) and color (phase) information can be greatly enhanced.

Abstract: A display synchronization signal generation apparatus and method, which make it possible to display a stable image irrespective of changes of horizontal and vertical frequencies of a received analog video signal in an analog video signal receiver. The display synchronization signal generation apparatus includes a detection unit, a change amount conversion unit, and a vertical synchronization signal generation unit. The detection unit detects an amount of change in a vertical period of an input video signal by comparing current and previous vertical periods of the input video signal. The change amount conversion unit converts the detected amount of change into the amount of change in a vertical period of a video signal to be displayed, using the current vertical period and the total number of pixels per frame. The vertical synchronization signal generation unit generates a vertical synchronization signal of the video signal to be displayed.

Abstract: The invention is a circuit and method for automatically adjusting the phase and frequency of a pixel clock derived from analog image data. The circuit includes a phase locked loop circuit adapted to generate a phase locked loop clock responsive to a reference signal and an edge detector circuit adapted to generate an edge pulse signal corresponding to a transition of an analog data signal. A phase detector circuit is adapted to identify a phase of the phase locked loop clock associated to the transition of the analog data and thereby generate a phase adjust signal. A phase adjust circuit is adapted to generate a pixel clock by adjusting the phase of the phase locked loop clock responsive to the phase adjust signal.

Abstract: A processing circuit for a sync signal includes a trial circuit and a windowing circuit. The trial circuit includes a counter that generates a count value proportional to the duration between successive sync pulses. When the count value reaches a trial sync spacing count value, a trial window signal is created and the counter is reset. If a predetermined number of subsequent sync pulses occur within the trial window signal, the sync spacing count value is confirmed and stored in a sync spacing register. The windowing circuit includes a counter that generates a count value proportional to the duration between successive window signals, and compares the count value to the value stored in the sync spacing register to generate a window signal. The window signal is compared with the sync signal pass valid sync signals.

Abstract: Disclosed is a channel equalizing apparatus and method for a digital television receiver that performs channel equalization using equalizing algorithms. The channel equalizing apparatus includes a channel equalizing section for compensating for channel distortion using a blind algorithm and a decision directed algorithm among equalizing algorithms, and a equalizing control section for calculating error values for compensating for the channel distortion from the blind algorithm and the decision directed algorithm and controlling the channel equalizing section to compensate for the channel distortion according to the calculated error values.

Abstract: When performing A/D conversion on image signals, when reducing noise that is caused by jitter by adjusting the phase of the sampling clocks, even if the input waveform has considerable waveform distortion such as a triangular wave, it is possible to reliably reduce this noise. Input analog image signals are converted into digital image data using sampling clocks from a PLL circuit by A/D conversion means. Next, image data that has delayed by a 1 clock delay circuit is subtracted from the digital data by a subtracter. The maximum value of one screen of the subtracted output is then determined, and 5 is subtracted therefrom to provide a threshold value. A comparator compares the subtracted output and the threshold value, and outputs a signal when the subtracted output is greater than the threshold value. A counter then supplies the count value of these signals to a CPU, and the CPU controls the phases of the sampling clocks using a switch.

Abstract: An external synchronous signal circuit comprises: means for measuring a phase difference between the external frame synchronous signal (FRM_SYNC) and the frame synchronous signal (FRM) of the digital video signal; means for generating a signal (EXT_H) having the same period as that of the horizontal synchronous signal (HBK) of the digital video signal, the signal (EXT_H) having the measured phase difference with reference to the frame synchronous signal (FRM) of the digital video; and means for generating a signal (EXT_F) having the same period as that of the frame synchronous signal (FRM) of the digital video signal, the signal (EXT_F) having the measured phase difference with reference to the frame synchronous signal (FRM) of the digital video. The generated signals (EXT_F) and (EXT_H) are outputted as an external frame timing signal and an external horizontal timing signal of an external synchronous signal.

Abstract: A pixel clock frequency is adjusted in response to periodically monitoring the relative positions between a video signal to be displayed and a video signal captured. Image shear of the display signal may be avoided quickly. Adjustments are made to the color burst signal where dramatic changes in the pixel clock frequency result.

Abstract: A method An apparatus and system for producing a digital video signal from an analog video signal, the analog video signal including an analog video data signal that is raster scanned in lines across a CRT screen to form consecutive frames of video information, the raster scanning controlled by use of a horizontal synchronizing signal (Hsnyc) (Hsync) that controls a line scan rate, and a vertical synchronizing signal (Vsnyc) (Vsync) that controls a frame refresh rate, to produce consecutive frames of video information, wherein the digital signal is produced by generating a pixel clock signal with pixel clocks for repetitively sampling instantaneous values of the analog video data signal, and digitizing the analog video data signal based on the pixel clock sampling.