Abstract: A video signal converter converts a first video signal into a second video signal by changing the number of scanning lines. A horizontal pulse synchronized with the first video signal is fed into a PLL circuit, which generates a first clock signal synchronized with the horizontal pulse. The first video signal undergoes A/D conversion by sampling with the first clock signal. The converter receives a first digital video signal which has undergone the A/D conversion, the first clock signal, the horizontal pulse, and a vertical pulse synchronized with the first video signal, and thus changes a number of scanning lines of the first video signal. The converter, next, writes a second digital video signal into a memory by synchronizing the first clock signal.

Abstract: A video display apparatus comprises a phase-locked loop receiving a horizontal synchronous signal for generating an oscillation signal following the frequency of the horizontal synchronous signal, a tracking circuit for generating a tracking control signal for moving the frequency of the oscillation signal into a predetermined capture range of the phase-locked loop when the frequency of the horizontal synchronous signal changes, so that the frequency of the oscillation signal follows the frequency of the horizontal synchronous signal, and an output circuit receiving and amplifying the oscillation signal to output a horizontal output signal.

Abstract: An image data processing apparatus is described that prevents the period of a horizontal timing signal from being shifted. The apparatus includes a separator, a phase-locked loop, a detector, a compensator and a timing signal generator. The detector delays a reference clock signal in a shorter period than the period of the reference clock signal, in a step-like manner, to produce a plurality of delayed timing signals having step-like phase differences. The detector further contrasts the plurality of delayed timing signals with a horizontal sync signal and the reference clock signal to measure the phase difference and the period of the horizontal sync signal. The compensator sets a ratio for combining consecutive luminance data in accordance with the phase difference and the period of the reference clock signal and combines consecutive luminance data in accordance with the ratio to generate compensated luminance data.

Abstract: A phase locked loop for synchronizing decoding clocks with encoding clocks in a Moving Picture Experts Group (MPEG) system. The phase-locked loop circuit includes a voltage controlled oscillator for converting a decoding clock into an encoding clock, a register unit for storing multiplexing program clock reference signals, each input with a desired number of bits, a counter being initialized by a first program clock reference signal output from the register unit, thereby generating a local program clock reference signal, and a phase error control unit for combinationally operating the program clock reference signal stored in the register unit and the local program clock reference signal, thereby generating a phase error signal for controlling the voltage controlled oscillator.

Abstract: The invention presents a dot clock reproducing apparatus for automatically reproducing the dot clock easily, by setting the dot clock frequency of a video signal source, and correcting the phase difference of the dot clock occurring in the transmission route or the like, and also presents a dot clock reproducing method comprising, in dot clock reproduction, a step of sampling at a frequency different from the dot clock of video signal, a step of detecting the aliasing frequency component occurring at this time, and a step of reproducing the dot clock so as not to cause this aliasing frequency component, and as an apparatus employing such method, the invention further provides a dot clock reproducing apparatus comprising A/D converting means for receiving an adjusting signal delivered from a video signal source, and sampling this adjusting signal to convert into a digital signal, PLL means for dividing a specified synchronizing signal and generating a sampling clock for the A/D converting means, frequency anal

Abstract: A PLL circuit includes a phase comparator that compares an external synchronizing signal and an internal synchronizing signal to detect a phase difference therebetween, and a voltage-controlled oscillator that generates the internal synchronizing signal by oscillation thereof. The frequency of the voltage-controlled oscillator is controlled depending upon the phase difference, so that the internal synchronizing signal becomes in phase with the external synchronizing signal. A limiting device is provided, which limits the phase of the external synchronizing signal supplied to the phase comparator to be within a predetermined window period that includes the timing of generation of the internal synchronizing signal.

Abstract: A VCD up-grading circuit board for a CD player or CD-ROM includes an MPEG decoder, a microprocessor, a DRAM, an audio digital/analog converter, a TV encoder and a synchronous clock generator. The VCD up-grading circuit board for a CD player or CD-ROM is attached to the CD player or CD-ROM to allow the CD player or CD-ROM to play a VCD without additional connection between the VCD up-grading circuit board and the CD player (CD-ROM).

Abstract: In a synchronization stabilizing circuit and a television signal receiver, the follow-up range (TX) of the synchronizing signal (SH) is changed based on the judged result (J1) that it is judged whether or not the synchronizing signal (SH) itself exists and the judged result (J2) that it is judged whether or not the input signal exists in a follow-up range (TX), so that the signal can be synchronized easily in a short period even if the frequency of the synchronizing signal (SH) is deviated.

Abstract: A clock signal generator and method for generating a clock signal which is synchronized with an input composite video signal. The generator comprises a synchronizing separator for separating a horizontal synchronizing signal from an input composite video signal; a burst separator for separating a color burst signal from the input composite video signal; a phase error detector for receiving the horizontal synchronizing signal, detecting a phase error and outputting a phase error signal for a previous horizontal period; a phase change detector for receiving the color burst signal, detecting a phase change of the color burst signal, and outputting a phase change signal for a present horizontal period; an adder for adding the phase error signal and the phase change signal; and a clock signal generator for receiving an output of the adding means and generating a clock signal which is synchronized with the input composite video signal.

Abstract: Vertical and horizontal sync signals are separated from an NTSC signal inputted from an outside by an external input circuit and a luminance signal (Y) and chrominance signals (B-Y, R-Y) are extracted and converted into RGB data. External RGB data and RGB data formed by a software are processed and the resultant data is supplied to an output converting circuit. The RGB data is converted into analog signals of the luminance signal and chrominance signals of a television signal by using individual system clock signals and outputted. A clock generating circuit generates two kinds of dot clocks which are used for the output converting circuit. The dot clock which is generated from the clock generating circuit and is used for conversion of the luminance signal is phase matched so as to follow a jitter of a horizontal sync signal (H) separated by an external video input circuit.

Abstract: A video/graphics overlay circuit receives an analog input composite video signal and a digital input composite video signal and combines them into a linear combination output composite video signal depending on the state of one or more mixer control signals. The two composite video input signals are each capacitively coupled to buffer and clamp circuits through which the blank or DC level of each signal is clamped to two volts. The outputs of the buffer and clamp circuits are then fed to a mixer circuit and burst separator circuits. The mixer circuit generates the output composite video signal which is a linear combination of the input composite video signals as controlled by the one or more mixer control signals. The burst separator circuits separate the burst signal from the input composite video signals. The extracted burst signals are then provided to a burst signal phase-locked loop for locking the burst signals of the input composite video signals in phase.

Abstract: When the margin between a write frequency-divided clock signal and a read frequency-divided clock signal becomes remarkably decreased, a clock phase difference detecting circuit outputs a reset execution command. While a reset execution command is being output in a blanking interval, a reset signal generating circuit supplies a reset signal to an input side counter corresponding to a reset execution command so as to reset the phase of the write frequency-divided clock signal to an initial state.

Abstract: In a video frame grabber for digitizing analog video signals which have a pure analog video signal component and a synchronization signal component, the synchronization signals are digitized along with the pure analog video signals. Video gain and offset, sync gain, and sync threshold can be adjusted electronically. A variable time delay can be imposed on the sampling clock signals and on horizontal reference signals. Optimal values can be determined for the various parameters.

Abstract: An H-sync to pixel clock phase detection circuit comprising: a programmable delay line for delaying an H-sync signal; a differential clock driver circuit for producing a pixel clock signal and a pixel clock/signal from a pixel clock signal input; a first D flip-flop having D and CLK inputs and a Q output; a second D flip-flop having D and CLK inputs and a Q output; wherein the delayed H-sync signal from the programmable delay line is applied to the respective D inputs of the first and second D flip-flops, wherein the pixel clock signal from the differential clock driver circuit is applied to the CLK input of the first D flip-flop, and wherein the pixel clock/signal from the differential clock driver is applied to the CLK input of the second D flip-flop; and a third D flip-flop having D and CLK inputs and a Q output; wherein the Q output of the first D flip-flop is applied to the D input of the third D flip-flop, wherein the Q output of the second flip-flop is applied to the CLK input of the third D flip-flop;

Abstract: A video/graphics overlay circuit receives an analog input composite video signal and a digital input composite video signal and combines them into a linear combination output composite video signal depending on the state of one or more mixer control signals. The two composite video input signals are each capacitively coupled to buffer and clamp circuits through which the blank or DC level of each signal is clamped to two volts. The outputs of the buffer and clamp circuits are then fed to a mixer circuit and burst separator circuits. The mixer circuit generates the output composite video signal which is a linear combination of the input composite video signals as controlled by the one or more mixer control signals. The burst separator circuits separate the burst signal from the input composite video signals. The extracted burst signals are then provided to a burst signal phase-locked loop for locking the burst signals of the input composite video signals in phase.

Abstract: An arrangement for synchronizing a digitally generated color subcarrier signal to the color burst signal from another video signal, such as that from a video casette recorder or from a cable television signal, in a manner that allows a line locked clock to be used without causing unacceptable disturbance to the generated subcarrier signal.

Abstract: A digital sine wave signal is read form a memory storage of a phase synchronizing apparatus and is converted into an analog signal through a digital to analog converter. This converted analog sine wave is phase compared to an input analog sine wave supplied to an input terminal of the synchronization apparatus. The phase of the digital sine wave is synchronized with that of the input analog sine wave by controlling a read address signal of the memory storage based upon a detected phase error signal between the input analog sine wave and the converted analog sine wave. Thus, a desired digital signal synchronized with the phase of an input signal can be generated by a simple arrangement by digital processing.

Abstract: A method for producing a digital video signal from an analog video signal, the analog video signal including an analog video data signal that is raster scanned in lines across a CRT screen to form consecutive frames of video information, the raster scanning controlled by use of a horizontal synchronizing signal (H.sub.snyc) that controls a line scan rate, and a vertical synchronizing signal (V.sub.snyc) that controls a frame refresh rate, to produce consecutive frames of video information, wherein the digital video signal is produced by generating a pixel clock signal with pixel clocks for repetitively sampling instantaneous values of the analog video data signal, and digitizing the analog video data signal based on the pixel clock sampling. An expected width E, measured in number of pixel clocks, of a video image producible by the analog video signal is estimated, and an actual width W, measured in number of pixel clocks, of the video image producible by the analog video signal is calculated.

Abstract: An arrangement for stabilizing a horizontal synchronization signal, serving as an input signal for a phase-locked loop (PLL) for generating a clock signal, by separating the horizontal synchronization signal from a composite synchronization signal including both horizontal and vertical synchronization signals. A horizontal synchronization gate signal is generated for outputting a pulse signal approximately in phase with the horizontal synchronization signal and having at least the pulse width of the horizontal synchronization signal in accordance with the composite synchronization signal and a clock pulse signal having a predetermined frequency. The horizontal synchronization signal is retrieved from the composite synchronization signal in accordance with a logical product when matching the polarity of the horizontal synchronization gate signal with the polarity of the composite synchronization signal.

Abstract: An automatic step generator that monitors and corrects the sampling rate in a video signal. The invention isolates a sampling window in the prevailing sampling rate, the window advantageously being 144 lines for NTSC, or 231 lines for PAL, or some other preselected window wherein the sample count therein at an ideal sampling rate approximates an integer power of 2. The invention then calculates the numeric difference between that ideal sample count in the window and the preselected integer power of 2. The actual sample count in the window is then determined, and is adjusted by the numeric difference between the ideal count and the integer power of 2. Variations in this adjusted actual sample count and the integer power of 2 will thus represent variations between the actual sampling rate and the ideal sampling rate. A step value to correct the actual sampling rate to achieve the ideal rate may then be derived by dividing the adjusted actual sample count by the integer power of 2.

Abstract: In a video frame grabber for digitizing analog video signals which have a pure analog video signal component and a synchronization signal component, the synchronization signals are digitized along with the pure analog video signals. Video gain and offset, sync gain, and sync threshold can be adjusted electronically. A variable time delay can be imposed on the sampling clock signals and on horizontal reference signals. Optimal values can be determined for the various parameters.

Abstract: A method for producing a digital video signal from an analog video signal, the analog video signal including an analog video data signal that is raster scanned in lines across a CRT screen to form consecutive frames of video information, the raster scanning controlled by use of a horizontal synchronizing signal (H.sub.sync) that controls a line scan rate, and a vertical synchronizing signal (V.sub.sync) that controls a frame refresh rate, to produce consecutive frames of video information, wherein the digital video signal is produced by generating a pixel clock signal with pixel clocks for repetitively sampling instantaneous values of the analog video data signal, and digitizing the analog video data signal based on the pixel clock sampling. An expected width E, measured in number of pixel clocks, of a video image producible by the analog video signal is estimated, and an actual width W, measured in number of pixel clocks, of the video image producible by the analog video signal is calculated.

Abstract: A television receiver providing a stable image whether or not a composite color signal is present, in which a transmitter-recognition processes the television synchronization signals of the composite color signal. A character generator displays alphanumeric as well as graphic characters. The deflection generators and the character generator are operative with TV signals as well as characters that are alphanumeric as well as graphic. The deflection generators and the character generator are driven by control signals. An oscillator controls the deflection generators, and a phase comparator operates in the presence of synchronization signals to synchronize the oscillator. The phase comparator receives no signals from the input terminal when no synchronization signals are present, so that the oscillator oscillates at a fixed preadjustable frequency to provide a stable image.

Abstract: A more rapid charging of an integrating capacitor of a PLL is provided when large frequency changes are desired. In one embodiment, the phase locked loop (PLL) circuit sinks or sources current to charge or discharge the integrating capacitor. A threshold voltage proportional to a current through the capacitor turns on a circuit which sinks or sources more current of the proper polarity to the integrating capacitor from an external source until a PLL lock is achieved. Once the lock is achieved, if a small correction current is required by the PLL, the small correction current is below a threshold required to actuate the augmenting circuit, and the PLL loop behaves in the usual manner as if the augmenting circuit were not present. In another embodiment, the integrating capacitor is reduced in value by switchably connecting a second capacitor in series with the integrating capacitor so that the total reduced capacitance of reduced value can be charged more quickly.

Abstract: A horizontal synchronizing signal Hs and a vertical synchronizing signal Vs are converted to digital data, respectively, by corresponding frequency-to-voltage conversion circuits 10 and 20 and AD conversion circuits 30 and 40. These digital data are compared with regulation values corresponding to the operation frequencies of a CRT display 2000 stored in the regulation value memory 90 by a frequency decision circuit 50 so that abnormality of frequency of the horizontal synchronizing signal and vertical synchronizing signal is decided. At an abnormal time, the state indication data corresponding to the abnormal state are read out from the state indication data memory 70. The display control circuit 60 constitutes a new video signal based on the state indication data and supplies the new signal to the CRT display in place of the video signal from the computer 1000 through the switch 80.

Abstract: An automotive video display of a scene from a camera has a graphics window to display vehicle information. A video graphics controller has a programmable synchronous generator for the graphics window which is synchronized or gen-locked with the camera or external video signal. A digital sync separator provides digital external sync signals. A start circuit monitors the external sync signals to detect the start of a video frame and starts the sync generator which is initially in synchronism with the external signal. A phase locked loop maintains the synchronism. A crystal oscillator circuit includes an inductor and a varactor which is tuned to vary the oscillator frequency enough to track the external video signal.

Abstract: An apparatus and method are provided for automatically adjusting a pixel sampling clock frequency and phase of a video display to match the frequency and phase of a pixel clock used to generate an incoming video signal being received by the video display. Voltage transitions are detected between pixel intensities in a video signal. The voltage transitions are compared with pixel sampling clock pulse signals of the video display in order to correctly match the frequency and phase of the video signal, and thus produce a more stable and noise-free image on the video display.

Abstract: A horizontal synchronizing signal is applied as a reference signal and a voltage-controlled oscillator outputs a frequency signal on the basis of the frequency of the horizontal synchronizing signal. The period of the frequency signal is divided in accordance with a frequency-dividing value set in advance, the difference in frequency between the frequency-divided frequency signal and the horizontal synchronizing signal and the phase difference between them are obtained, and control is performed in such a manner that the frequency of the signal outputted by the voltage-controlled oscillator is decided in dependence upon the frequency difference. In an interval in which a vertical synchronizing signal turns off and the frequency of the horizontal synchronizing signal fluctuates, the input to the voltage-controlled oscillator is held fixed to prevent a fluctuation in the outputted display clock.

Abstract: A monitor-mode control circuit and method thereof determines a video mode by detecting horizontal and vertical sync frequencies and the polarities of the sync frequencies received from a video card, varies an external resistance value connected to a predetermined port of a microprocessor in accordance with the determined video mode to output a voltage for controlling the picture status of the monitor, in which a program of the microprocessor is changed by a demand of a buyer without changing the hardware to easily correspond to any specification required by the buyer unrestricted by the specification, an external resistance value connected to the predetermined port of the microprocessor at a high or low state is varied to adjust and output voltages of a horizontal size, a vertical size, a horizontal position, a vertical position and a side pin/barrel corresponding to the determined video mode, and a voltage of an oscillating frequency for correcting the synchronization of a picture is output by a pulse width

Abstract: A digital phase error detector for locking to a color subcarrier signal in an analog video signal. The digital phase error detector includes a digitizer responsive to a sample clock which generates a first digital data stream from the analog video signal. Filtering circuitry filters the first digital data stream to generate a second data stream by substantially eliminating DC offset of the color subcarrier signal digitized by the digitizer. A mixer mixes the second digital data stream to generate a third digital data stream representing sum and difference frequencies of a product of the color subcarrier signal and a reference clock. An accumulator accumulates this product which represents a phase error between the color subcarrier signal and the reference clock. A voltage controlled oscillator is responsive to this phase error for generating the sample clock.

Abstract: In an automatic frequency control circuit for synchronizing a horizontal deflection current of a television receiver with a horizontal sync signal, a bi-level signal which assumes either of two levels when the flyback pulse is or below a threshold value is produced, and a wider sync signal in synchronism with the horizontal sync signal and having a pulse width wider than the horizontal sync signal and equal to an odd multiple of the operating clock period is also produced. A phase comparator detects the difference in the number clock periods between a period period from a leading edge of the wider sync signal to an edge of the bi-level signal, and a period from the edge of the bi-level signal to a trailing edge of the wider sync signal. The detected difference is used to control a VCO. In an alternative configuration, a digital signal indicative of a magnitude of the flyback pulse during its rising or falling slope at an edge of the horizontal sync signal is produced and used for control of the VCO.

Abstract: The present invention relates to a method of enhancing the noise Immunity of a phase-locked loop. The phase-locked loop includes a comparator and apparatus for inhibiting the action of the comparator on the phase-locked loop. According to the method, the inhibition is lifted during a main time window resulting from the intersection of a first time window derived from the input signal of the phase-locked loop, and of a second time window derived from the loop-return signal.

Abstract: A system and method for determining a timing error of an incoming signal, in one embodiment, receives the incoming signal into a receiver, and locates a known portion within a time frame of the incoming signal. The known portion is compared with a stored representation of the known portion, and with a stored representation of a derivative of the known portion. The timing error of the incoming signal is determined with respect to the clock signal based on the comparing of the known portion with the stored representations, and a subsequent known portion is located within a subsequent time frame of the incoming signal based on the timing error.

Abstract: A video system pulse generating circuit has the frequency of the video system pulse being an integral multiple of a video synchronizing signal, and being synchronized with video synchronizing signal. The video system pulse generating circuit includes a phase locked loop circuit, a dividing circuit, and a synchronizing range determining circuit, wherein an asynchronous oscillator such as a quartz oscillator is not required.

Abstract: A bi-phase stable FPLL is locked by a DC pilot component in a recovered data signal. The signal is formatted in repetitive data segments including sync characters and a DC pilot. A sign bit, indicative of the polarity of the recovered data, is developed from the sync characters and is used to augment the DC pilot to stabilize the lock up of the FPLL to produce the desired polarity of recovered data.

Abstract: In an automatic frequency control circuit for synchronizing a horizontal deflection current of a television receiver with a horizontal sync signal, a bi-level signal which assumes either of two levels when the flyback pulse is or below a threshold value is produced, and a wider sync signal in synchronism with the horizontal sync signal and having a pulse width wider than the horizontal sync signal and equal to an odd multiple of the operating clock period is also produced. A phase comparator detects the difference in the number clock periods between a period period from a leading edge of the wider sync signal to an edge of the bi-level signal, and a period from the edge of the bi-level signal to a trailing edge of the wider sync signal. The detected difference is used to control a VCO. In an alternative configuration, a digital signal indicative of a magnitude of the flyback pulse during its rising or falling slope at an edge of the horizontal sync signal is produced and used for control of the VCO.

Abstract: Disclosed herein is an oscillator circuit used for a PIP system which displays a child picture image without distortion even when the image method of the child picture image is different from that of a parent picture image. The oscillator circuit employed in such a system includes a programmable frequency divider for frequency dividing an output of a voltage-controlled oscillator with a frequency dividing ratio to produce a frequency-divided signal and a control circuit for controlling the oscillation frequency of the oscillator 201 according to a phase difference between the frequency-divided signal and a horizontal synchronizing signal. The frequency dividing ratio for the frequency divider is changed according to the image method of the child picture image.

Abstract: A high frequency television signal receiving apparatus providing excellent linear detection of output characteristics by improving the phase characteristic of the picture synchronous detector. A variable capacitive element is equivalently connected in parallel to a reference solid-state oscillation element. The reference solid-state oscillation element controls the frequency of a local oscillation device including a PLL circuit for feeding a local oscillation signal to a mixer for converting a high frequency signal into an intermediate frequency signal. A first low pass filter is connected between a phase comparator for detecting a phase difference of the intermediate frequency signal and the output of a detection oscillator for generating a detection oscillation signal with a specific phase difference. A second low pass filter having a larger time constant than the first low pass filter is connected to the variable capacitive element.

Abstract: A composite synchronization extraction circuit is particularly suited for receiving composite video signals containing closed captioning data in raster scan line 21 by means of a signal CMOS integrated circuit device. A dual mode voltage clamp is realized in CMOS technology. The clamp includes temperature compensated current sources in the form of complementary current mirrors through which a clamped composite synchronization node of is charged and discharged, the output of which controls a transistor for charging the composite synchronization node. Detected pulse amplitude is set by slicing the incoming pulse at the back porch level and then doubling the amplitude with an amplifier and comparing that level with the back porch level as derived from a sample-and-hold device. The slice voltage level is maintained without an off-chip capacitor by an analog-digital-analog conversion process.

Abstract: An AFC system and method of detecting and compensating frequency drift in the carrier frequency of a Gaussian filtered Minimum Shift Keying (GMSK) signal by demodulated frequency compensated samples of the received signal and calculating a frequency compensation angle based upon the demodulated frequency compensation samples. The compensation angle is fed back to the frequency compensator and error detector and used to calculate the error signal.

Abstract: A demodulating system for a high definition television (HDTV) that includes a tuning circuit for selecting one out of a plurality of received radio frequency (RF) signals and for converting the selected signal into an intermediate frequency (IF) signal according to an input loop-controlling signal. An oscillating circuit generates a sine wave signal. A filtering circuit passes only a pilot signal containing HDTV carrier information from the IF signal and cancels the remainder. A FPLL circuit for using a predetermined algorithm to form a loop-controlling signal for synchronizing the frequency and phase of the pilot signal and the frequency and phase of the sine wave and providing the loop-controlling signal to the tuning circuit.

Abstract: A dual mode AGC system for a television receiver in which data is in the form of symbols occurring at a fixed symbol rate. The symbols are sent in successive data segments, each having a sync character. Enablement of an AFC Defeat signal defines an initial interval during which the IF gain is maximum. When the AFC Defeat signal becomes inactive, the receiver is operated in a non-coherent mode in which the gain of the IF amplifier is reduced incrementally whenever the IF signal exceeds a clipping level for a period of eight successive symbol clocks. Upon a segment sync lock condition occurring, a normal coherent mode is entered in which the AGC responds to a signal characteristic, i.e. data segment sync. The rate of gain change available in the non-coherent mode-is much greater than that in the normal coherent mode.

Abstract: A dot clock generation system has a voltage-controlled oscillator (VCO) for generating a dot clock signal for an analog-to-digital convertor (ADC). A dot clock synchronization (sync) generator counts cycles of the dot clock signal and generates a dot clock sync signal. An analog video signal is passed through a first differential buffer to create an analog video sync signal. The analog video sync signal is passed through a first flip-flop storage element to a phase detector. The dot clock sync signal is passed through a second storage element and then through a second differential buffer to the phase detector. The second storage buffer insures that the edge of the dot clock sync signal which is used by the phase detector is tightly tied with the sampling edge of the dot clock signal which is used by the ADC to sample the analog data within the analog video signal.

Abstract: PLL apparatus for generating an oscillatory signal phase locked to a component of a further signal comprises a variable oscillator for generating the oscillatory signal and a source of the further signal. A phase detector responsive to the oscillatory signal and to the component of the further signal, provides a phase error signal which is coupled to the variable oscillator via a limiter. Circuit means are provided for controlling the limiting level of the limiter. The dual limiting substantially improves the loop noise tolerance and reduces the loop sensitivity to occasional phase reversals of the component of the further signal. Additional enhancements to loop stability and noise immunity are provided by an unlock detector which detects and totalizes phase rotations in a selected area of a phase plane and by a phase wrap detector which maintains a lock indication during phase angle wrapping.

Abstract: A pilot signal detection circuit receives a supply of a pilot signal produced by frequency-modulation of a predetermined third frequency carrier signal by a first discrimination signal of a first frequency and a second discrimination signal of a second frequency, and makes a discrimination between the first discrimination signal and the second discrimination signal by whether a signal detected is of the first frequency or of the second frequency. The pilot signal detection circuit is constituted by first and second multiplying and filtering stages. The first multiplying and filtering stage includes first and second multipliers and first and second low-pass filters. The first and second multipliers multiply the pilot signal respectively with the first reference signal and the second reference signal, and produce respectively first and second multiplied signals.

Abstract: A frequency modulating system for frequency-modulating an input signal with a predetermined carrier frequency comprising a controller circuit and a frequency modulator. The controller circuit includes an automatic frequency detecting circuit, a voltage controlled oscillator, an error current generator, a feedback clamping circuit, a deviation current generator, and an adder circuit generating a frequency deviation/carrier frequency correction signal provided to the frequency modulator. The frequency modulator modulates the frequency in response to an output of the controller circuit and includes an oscillator having the same structure as that of the voltage control oscillator.

Abstract: A method and apparatus for synchronizing display timing in a digital television system with a pixel addressable display having a color wheel is disclosed. The display timing circuit 22 includes phase comparator 40, for comparing the phase of a wheel index signal generated by a color wheel 20 with the phase of a frame synchronization signal indicating that a complete frame is ready to be displayed. Display timing circuit 22 further comprises a color wheel synchronization generator 42 which generates a color wheel synchronization signal in response to a phase difference value produced by phase comparator 40. The color wheel synchronization signal is used to increase, decrease, or maintain the speed of color wheel 20 to achieve a known phase relationship between the frame synchronization signal and the wheel index signal. Display timing circuit 22 further comprises a clock generator applicable to generate a display master clock signal having a known frequency relation to the wheel index signal.

Abstract: A digital automatic frequency controlling method and circuit therefor in which a digital horizontal sync signal is separated from an input horizontal sync signal in response to a system clock, a horizontal sync separation point value is extracted, an actual horizontal sync period is calculated by using the digital horizontal sync signal and the clock pulse number within one horizontal sync period, a line jitter amount is calculated by subtracting a standard horizontal sync period from the actual horizontal sync period, a correction coefficient in response to the line jitter amount is generated to modulo-operate a standard frequency down-converting carrier color signal and to thereby generate a new frequency down-converting carrier color signal having compensated line jitter.

Abstract: A phase locked loop (PLL) chain for locking audio sampling to serial digital component video timing has a deserializer that recovers a video sample clock signal from a serial digital video signal, the deserializer including a wide bandwidth PLL. A tracking filter in the form of a narrow bandwidth PLL having a low pass filter function reduces the jitter in the video sample clock signal to produce a stable reference clock signal. The stable reference clock signal is input to an audio sample clock generator to produce a stable audio sample clock signal for extracting audio data from the serial digital video signal.

Abstract: Various video signals provide horizontal sync pulses for generating a horizontal drive signal only during a horizontal sync portion and part of the vertical sync portion of a video signal. The invention generates a horizontal drive signal in the absence of horizontal sync pulses through the use of a phase locked loop (PLL) connected in feedback to horizontal counter logic. The counter logic receives pulses from the phase locked loop and at a predetermined count generates a horizontal drive signal. During the horizontal sync portion of the video drive signal, the frequency of the phase locked loop is determined by a time difference between a second signal derived directly from a horizontal sync pulse and a first signal generated by a predetermined count. The horizontal drive signal is thus synchronized to the horizontal sync pulses.