Abstract: In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.

Abstract: In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.

Abstract: To provide a data transmission system capable of reducing skews between a reference signal and a phase modulation signal and accelerating data transmission. In a data transmission system having a transmitter for transmitting a reference signal and a phase modulation signal having a phase difference related to the value of input data from the reference signal and a receiver for obtaining data in accordance with the phase difference between the received reference signal and phase modulation signal, the transmitter transmits the reference signal and an adjustment signal having no phase difference before transmitting data and a control circuit variably controls delay values of variable delay devices so that the phase difference between the reference signal and adjustment signal received by the receiver decreases.

Abstract: Methods and systems of generating a frequency switching local oscillator signal are disclosed. One method includes generating a reference clock signal, and clocking a counter with the reference clock signal. The counter controls selection of a one of a plurality of analog values stored in at least one of a plurality of periodic signal generators. The frequency switching local oscillator signal is generated by selecting an output of a one of the plurality of periodic signal generators.

Abstract: A received signal having pilots is converted to a first signal in the frequency domain having the pilots. The pilots are extracted from the first signal to obtain extracted pilots to form a second signal. The second signal is used to provide a first estimate of a channel. The first estimate is converted to the time domain. Noise is removed from the first estimate in the time domain to provide a second estimate of the channel in the time domain. An autocorrelation of the channel in the frequency domain is determined using the second estimate of the channel. Extension signals are determined using the autocorrelation. The extension signals are appended to the first estimate of the channel to obtain a third estimate of the channel. The third estimate is used to provide a data signal in the frequency domain.

Abstract: A system for implementing an orthogonal frequency division multiplexing scheme and providing an improved range extension. The system includes a transmitter for transmitting data to a receiver. The transmitter includes a symbol mapper for generating a symbol for each of a plurality of subcarriers and a spreading module for spreading out the symbol on each of the plurality of subcarriers by using a direct sequence spread spectrum. The symbol on each of the plurality of subcarriers is spread by multiplying the symbol by predefined length sequences. The receiver includes a de-spreader module for de-spreading the symbols on each of the plurality of subcarriers. The de-spreader module includes a simply correlator receiver for obtaining maximum detection. The correlator produces an output sequence of a same length as an input sequence and the de-spreader module uses a point of maximum correlation on the output sequence to obtain a recovered symbol.

Abstract: A system and method of communicating sub-synchronization information into a transmitted digital audio stream and extracting sub-synchronization information from a received digital audio stream is provided. The method includes the steps of having a transmitter introduce sub-synchronization information into a data stream at a period less than that of existing transmitter pre-amble signals, and transmitting that data to a receiver. The method further includes the steps of receiving the transmitted data stream in the receiver circuitry, extracting the synchronization information, and using the synchronization information to accurately decode the received audio data.

Abstract: The field of the invention is that of transmission interfaces for synchronous digital input signals composed of bits transmitted in series at a frequency of transmission equal to a first integer multiple M of a first clock frequency. The interface according to the invention comprises at least one deserializer operating in over-sampling mode and supplying digital output samples of each bit in parallel. The output samples are transmitted at a second clock frequency, integer multiple N of a third frequency. The third frequency is substantially equal to the first frequency. Each sampled bit is substantially composed of N samples. The interface has an electronic device for frequency-locking the third frequency onto the first clock frequency. The device has means for counting the number of samples composing each sampled bit.

Abstract: An all-digital frequency synthesizer architecture is built around a digitally controlled oscillator (DCO) that is tuned in response to a digital tuning word (OTW). In exemplary embodiments: (1) a gain characteristic (KDCO) of the digitally controlled oscillator can be determined by observing a digital control word before and after a known change (?fmax) in the oscillating frequency; and (2) a portion (TUNE_TF) of the tuning word can be dithered (1202), and the resultant dithered portion (dkTF) can then be applied to a control input of switchable devices within the digitally controlled oscillator.

Abstract: A wireless communication system includes: a frequency down-converting circuit for receiving a wireless signal and for performing frequency down-conversion on the wireless signal to output a frequency down-converted signal; a first training circuit for performing frequency comparison between the frequency down-converted signal and a plurality of candidate carrier signals having different frequencies so as to determine a plurality of selected carrier signals from the candidate carrier signals; a second training circuit for performing phase comparison between the frequency down-converted signal and phases of a pseudo-noise sequence at each of the selected carrier signals so as to determine a matching phase and a matching carrier; and a demodulator for demodulating the frequency down-converted signal according to the matching carrier and the matching phase so as to generate a demodulated signal.

Abstract: A method for detecting a specific timing from a synchronization channel is described. A signal with a known sequence is received. Two or more correlation values between the received signal and the known sequence are calculated at two or more positions. The two or more correlation values are compared. A determination is made whether the position of the known sequence has been shifted based on the comparison. A specific timing of a synchronization channel is detected based on the determination.

Abstract: Computer-readable media, apparatus and other embodiments associated with performing comma alignment with scrambled data are described. One example method includes controlling an apparatus to generate a data stream that facilitates achieving and determining alignment in a device. The data stream includes sequences of N random portions of Y-bit characters followed by a Z-bit alignment character, N, Y and Z being integers. Another example method includes controlling an apparatus to receive and examine the data stream. The method also includes generating an alignment signal upon determining an alignment for recovered data in the device.

Abstract: An OFDM reception device detects a time at which impulse noise occurs in a received OFDM signal, and specifies a start position candidate period that does not have intersymbol interference and is estimated to have a guard interval signal in a symbol. When setting a FFT window of an effective symbol length in a symbol duration of each symbol, if the impulse noise occurrence time is included in the symbol, the OFDM reception device determines a start position of the FFT window within a range of the start position candidate period so as to exclude the impulse noise occurrence time as much as possible.

Abstract: An apparatus including a first circuit, a second circuit, a third circuit, and a fourth circuit. The first circuit may be configured to generate a demodulated signal in response to a modulated signal and a seed value selected in response to a first control signal. The second circuit may be configured to generate a second control signal in response to the demodulated signal. The third circuit may be configured to generate the first control signal in response to the second control signal, a compensation signal, and the first control signal, where generation of the first control signal includes adding the second control signal, the compensation signal, and a latched version of the first control signal. Generation of the latched version of the first control signal may include sampling the first control signal in response to a clock signal. The compensation signal may compensate for variation in the clock signal.

Abstract: Systems and methods are provided for aligning a video clock with the raster output scanner start-of-scan signal in printing systems. A system and method is proposed to align the pixel clock to an asynchronous reference signal generated in the raster output scanner. The proposed system and method adjusts a phase for a static phase value while performing a dynamic phase shifting for the start-of-scan signal alignment.

Abstract: Disclosed are a method and system for generating switching a timing signal for separating a transmitting and receiving signal in a RF repeater of a mobile telecommunication network by using a TDD scheme and an OFDM modulation scheme, which transmits a part of a RF signal extracted from a coupler of a RF repeater to a switching timing signal generating circuit when a RF signal transmitted from an Access Point (hereinafter, referred to as “AP”) is transmitted to a RF repeater, locates a frame start position of a RF signal by correlating a reference signal generated in a switching timing signal generating circuit and a RF signal extracted from a coupler, and is capable of transmitting a RF signal by distinguishing between a downlink signal and a uplink signal by using a switching timing signal in a switch when calculating a starting point of a downlink signal and a uplink signal which is included in an RF signal by using an AP's frame standard on the basis of a frame starting location, and transmitting to a RF r

Abstract: Clock synchronization for a wireless communication system is described. The communication system utilizes a server with a radio coupled to receive a radio frequency (RF) signal and a clock interface to receive a reference clock signal. The server includes a network interface configured to receive, from a base station, a time that the RF signal was received at the base station. The server further includes a processing device configured to determine when the RF signal was transmitted and a location of the base station, and configured to calculate clock offset value representative of a time to delay a local clock signal at the base station to synchronize the local clock signal at the base station with the reference clock signal.

Abstract: A method of operating a phase locked loop (FIG. 5) for a wireless receiver is disclosed. The method includes receiving a reference signal (503) having a first and a second plurality of cycles and receiving a feedback signal (512) having the first and the second plurality of cycles. The feedback signal is compared (504) to the reference signal. A plurality of phase errors is produced for each cycle of (UP, FIG. 10A) the first plurality of cycles in response to the step of comparing.

Abstract: An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing reference signal. The data-sampling signal may be provided by adjustably delaying a clock signal according to the phase information acquired from the strobe signal. The data-sampling signal may also have an improved waveform compared to the timing reference signal, including a fifty percent duty cycle and sharp transitions. The phase information acquired from the timing reference signal may also be used for other purposes, such as aligning received data with a local clock domain, or transmitting data so that it arrives at a remote device in synchronism with a reference clock signal at the remote device.

Abstract: Methods and systems to synchronize to a remote node counting rate, symbol rate, and carrier frequency as functions of an estimated frequency offset and relationships between the remote node carrier frequency and counting rate, and between the remote node carrier frequency and symbol rate. The carrier frequency offset may be scaled in accordance with a ratio between the carrier frequency and the remote counting rate to synchronize the local counting rate with the remote counting rate, and/or scaled in accordance with a relationship between the carrier frequency and the remote symbol rate to synchronize the a local receive path and/or transmit path sample rate with the remote symbol rate. The carrier frequency offset may applied as compensation in the receive path and/or the transmit path. The remote and local nodes may correspond to a network coordinator and an existing node, respectively, in a Multimedia Over Coax (MoCA) environment.

Abstract: A channel estimation method suitable for use in a CDMA communications system employs a high order interpolation using four interpolation points per slot. Four FIR interpolation filters (18-21) produce a channel estimate for each quarter of a slot by weighting the summed pilots of four slots by amounts related to pre-computed polynomial co-efficients. The invention has been shown wot mobiles and has the advantage of low computional complexity.

Abstract: A device for signal synchronization in a communication system is configured to perform a first sliding correlation for a received signal and a pseudo-random noise (PN) sequence to obtain information on symbol timing, identify a fractional carrier frequency offset (FCFO) using the information on symbol timing and the cyclic extension property of the PN guard interval (GI), and provide a first product by multiplying the received signal with the FCFO. The device is also configured to provide a set of second products by multiplying the first product with each of a set of phases related to integral carrier frequency offsets (ICFOs), perform a second sliding correlation for the PN sequence and each one of the set of the second products to thereby provide a set of peak values, and identify an ICFO by detecting an index number of a maximal value among the set of peak values.

Abstract: The present invention provides architectures and methods which enables faster and more power efficient detection of channel parameters used by a communication system. Various parallel preamble correlator structures are able to perform searches for multiple preambles in parallel. The received samples are correlated with different delays between the samples corresponding to the different possible channel parameters that may be used by the communication system. Processing elements used in the preamble search may be shared among the parallel preamble search sections of a given architecture to reduce costs and power consumption. Decimation and filtering may also be used to reduce the interference from adjacent channels.

Abstract: A variable code-tracking loop filter in a receiver having the ability to change its parameters multiple times in response to received signals. Parameters for the code-tracking loop filter may be varied based on phase and frequency errors from an error detector. In one implementation, the code-tracking loop filter is able to repeatedly vary a single parameter, such as its received bandwidth, based on the phase and frequency errors, while in another, the code-tracking loop filter may vary two or more parameters, such as the loop bandwidth and the natural frequency.

Abstract: Example embodiments are directed to a bandwidth synchronization circuit and a bandwidth synchronization method. The bandwidth synchronization circuit includes an upsizer and a syncdown unit. The upsizer includes a sync packer and a sync unpacker operating according to a first clock. The syncdown unit is connected to the upsizer and performs a syncdown operation on data of the upsizer in response to a second clock of a frequency lower than a frequency of the first clock.

Abstract: A universal series bus (USB) frequency synchronous apparatus using a start of frame (SOF) signal generated by a master device to mark a reference interval is disclosed. The frequency synchronizing apparatus includes a frequency divider, a counter unit with a default pulse number, an arithmetic unit, and an adjusting unit. The frequency divider divides a high frequency signal by a variable frequency factor to generate a lock frequency signal. The counter is used to detect a pulse number of the lock frequency signal at a reference interval and obtain a pulse difference between the default pulse number and the detected pulse number of the lock frequency signal.

Abstract: Double data rate (“DDR”) circuitry or the like is modified or enhanced to include edge detection capability. During edge detection mode the circuitry is supplied with serial training data that includes successive pairs of equal-valued bits. Several, differently-phased, candidate clock signals are used one after another in order of increasing phase to clock the DDR circuitry. Adjacent bits in the training data that should be equal-valued are captured by the DDR circuitry and compared. Any candidate clock signal that causes the bits thus compared to be unequal is flagged as having phase close to edges in the data. The approximate phase of data edges is thereby indicated by the phase (or phases) of the candidate clock signal (or signals) causing the bits compared as described above to be unequal.

Abstract: A method and device for signal detection is disclosed. At least one detection period is predefined for detecting a signal of a signal source, a differential signal of a pair of signal sources, or a dual-differential signal of three signal sources during at least one clock cycle.

Abstract: A communication apparatus using a synchronized clock signal includes: a communication signal generation unit generating one of a baseband signal and a signal obtained by applying digital modulation to the baseband signal, as a communication signal; an interface unit transmitting the generated communication signal and receiving a communication signal from an external source; a communication signal analyzing unit analyzing the received communication signal; a clock signal providing unit providing a clock signal to the communication signal generation unit, the interface unit, and the communication signal analyzing unit; and a controller controlling the communication signal generation unit, the interface unit, the communication signal analyzing unit, and the clock signal providing unit.

Abstract: An apparatus for performing a channel-to-channel delay correction and frame synchronization with low latency includes, on each of a plurality of channels, a clock-and-data recovery circuit, a frequency divider circuit, a circuit for detecting the phase difference between the phase of the frequency-divided clock signal and the phase of a clock signal, a serial-to-parallel converter circuit, a register array for holding the parallel output of the serial-to-parallel converter circuit, and a frame-head detector for detecting a frame head from the output of the register array and outputting a frame detection signal. A last-frame-head detector receives the frame detection signals from each of the channels and detects a channel on which the frame head was detected last. The frame head detected last, the phase of the internal clock signal, and the phase of a frequency-divided clock of a retiming clock of the channel are adjusted to substantially coincide.

Abstract: A method includes: delaying an excursion of at least one signal a first number of clock phases when the excursion departs from a value in a first direction; and delaying the excursion of the at least one signal a second number of the clock phases when the excursion departs toward the value in a second direction. The first number of clock phases is different from the second number of clock phases. The at least one signal effects a plurality of succeeding excursions in substantial synchrony with a clocked signal presenting succeeding clock cycles having a plurality of the clock phases in each respective clock cycle.

Abstract: A receiver for receiving information that contains clock information and data information and a clock-embedded interface method. In the clock-embedded method, a clock signal and data may be reconstructed by receiving a pair of differential signals that contain clock information and data information and by using a change in a common voltage of the pair of differential signals.

Abstract: A system for reducing electromagnetic interference and ground bounce in an information communication system includes a plurality of information communication devices. Each of the plurality of information communication devices is responsive to a respective information communication clock signal. Each information communication clock signal of each of the plurality of information communication devices is associated with a common reference clock signal. The system includes a phase controller. The phase controller is responsive to the common reference clock signal. The phase controller alters a phase of each information communication clock signal of each of the plurality of information communication devices by a predetermined amount.

Abstract: A clock generator circuit for generating synchronization signals for a multiple chip system. The clock generator circuit comprises generation of a synchronization signal from a reference clock and chip global clock with edge detection logic. In high performance server system design with multiple chips, a common practice for server systems is to use feedback clock and delayed reference clock to generate the synchronization signal. The generated synchronization signal is transferred to latches clocked by the global clock to be used for chip synchronization functions. As the system clock frequency is pushed higher, the phase difference between generated synchronization signal clocked by feedback clock and receiving latch clocked by global clock is becoming such a large portion of cycle time that this signal cannot be transferred deterministically.

Abstract: A method and apparatus for synchronizing timing of Access Points (APs) and/or Synchronization Units (SUs) includes (a) arranging a cable having at least four pairs of twisted wires connected between two or more fixed APs and/or SUs in a network; (b) assigning a first pair of the twisted wires to carry a positive D.C. voltage to at least one AP or SU; (C) assigning a second pair of the twisted wires to carry a negative D.C. voltage to at least one AP or SU; (d) providing to the first and second pairs of rails a series of synchronization pulses generated from a synchronization source and capacitively-coupled to the first and second pairs of twisted wires so as to supply a composite signal; and (e) reconstructing the generated synchronization pulses by detecting pulses on the positive and negative D.C. voltages at a receiving end by at least one AP or SU.

Abstract: A base point of a communication frame is detected by only using a reception signal, and an offset amount from the base point and the like are estimated. A device includes: an extraction unit for extracting self correlation processing signals from a digital communication signal having a signal frame for synchronization by using a pair of correlation processing windows of a variable size; a correlation unit for performing self correlation processing to the self correlation processing signals extracted; a matching unit for performing pattern matching processing between the correlation-processed signal, obtained through the self correlation processing, and a reference signal; and a computation unit for estimating the base point of the signal frame and an offset of the digital communication signal with respect to the base point, based on distance information of the pattern matching processing.

Abstract: A method for determining timing positions in a wireless communications system comprises creating a time-domain timing detection window from a preamble of a receiving signal, generating a first vector of correlations between sampling points in the time-domain timing detection window and sampling points of a known preamble, identifying a pivot position from the largest correlation value of the first vector and generating second vectors based on the pivot position, generating a third vector comprising the largest elements of the second vectors; generating a fourth vector comprising sums of elements in the second vectors, generating fifth and sixth vectors comprising a sum of subsets of the third and fourth vectors, respectively, calculating a seventh vector using the fifth and sixth vectors according to a predetermined equation, and selecting an index of one element from the fifth and seventh vectors to be the timing position according to a predetermined rule.

Abstract: To support cell search, multiple (e.g., two) synchronization transmissions are sent in a frame with non-uniform spacing. Information is conveyed via the non-equal distances between consecutive synchronization transmissions. Multiple levels of non-uniform spacing may be used to convey different types of information. In one design, the multiple synchronization transmissions are sent in different subframes of a frame, and each synchronization transmission is sent in one of multiple symbol periods in a respective subframe. The synchronization transmissions may be sent in non-evenly spaced subframes to convey frame boundary. One synchronization transmission may be sent in one of multiple possible symbol periods depending on the information, e.g., a particular group of cell IDs, being conveyed. The distances between synchronization transmissions may also be used to convey cyclic prefix length.

Abstract: A local area wireless transmission system includes: at least one transmitter transmitting a multimedia data signal with a first speed; at least one receiver receiving the multimedia data signal; and at least one master receiver transmitting a synchronization control signal with a second speed lower than the first speed, the at least one master receiver receiving the multimedia data signal from the at least one transmitter wirelessly and from the at least one receiver wiredly.

Abstract: Provided is a method for detecting frame sync and frame structure in a satellite broadcasting system, which acquires an estimated value for detecting frame structure and frame sync and overcomes distortion of correlation analysis values by summing differential correlation values for SOF positions in consideration of the variable frame length, and selecting a maximum value in a channel environment with low signal-to-noise ratio and high frequency error. SOF is a sync word indicating the start point of a frame. The method includes the steps of: acquiring SOF differential correlation value sequences; acquiring sums (di,t) of the correlation values normalized for SOF positions based on the number of symbols per frame by using the above-generated SOF differential correlation value sequences; and selecting a maximum value (dz,x) among the sums of correlation values, detecting z as a frame sync position, and detecting x as a frame structure index.

Abstract: A data processing circuit includes: a first circuit part having a first synchronization signal; a second circuit part having a second synchronization signal, and receiving a data signal and the first synchronization signal from the first circuit part; a phase comparing part carrying out phase comparison between the second synchronization signal and the first synchronization signal in the second circuit part; and a control part controlling a phase of the first synchronization signal based on a comparison result of the phase comparing part.

Abstract: A synchronized control method for actuators driving a moving device includes the sending of a signal repeating a frame including the code of the control to be executed, inserting into the frame sent a time information item representative of the control generation duration, extracting the time information item and computing at least one of the application start and the application end instant of control, and the reception of the signal for application of the control to the actuator as long as the generation of the control signal lasts.

Abstract: A method and apparatus are disclosed for generating phase controlled data, based on a roaming tap interpolator. The present invention recognizes that roaming tap interpolators have inherent nonlinearities and discontinuities at the boundaries of each interpolation region. A roaming tap interpolator is disclosed that shifts the interpolation curve in time in order to avoid the undesired artifacts in the interpolation curve. A roaming tap interpolator generally comprises a plurality of delay elements that delays a first signal to generate a plurality of interpolation regions each having an associated phase; a multiplexer to select one or more of the interpolation regions; and an interpolator to process the selected one or more of the interpolation regions to generate a second signal.

Abstract: A method of operating a wireless communications device may include determining a wake-up time for a receiver using a low frequency clock. Beginning at the wake-up time, the receiver may listen for reception of a packet transmitted from a remote device over a wireless interface. An actual time of reception of the packet transmitted from the remote device may be detected, and a new wake-up time for the receiver may be determined using the low frequency clock and the actual time of reception of the packet.

Abstract: The present invention relates to a method for measuring radio channel quality in a radio communication system. In the method a modulated signal is received over a communication channel. The modulated signal has been modulated by using modulation parameters. A decoder decodes (305) the modulated signal and forms decoded data. The decoder creates (306) a decoder performance indicator (PS) that depends on the decoded data. Then a radio channel quality indicator (RCQI) is created, the radio channel quality indicator being essentially independent of the modulation parameters.

Abstract: A method for motion estimation of sequences of images is proposed, wherein for consecutive frames (f1, f2) respective corresponding consecutive Fourier transformed frames (F1, F2) are determined, and wherein motion parameters for translation, rotation and/or for scaling are derived based on a phase relationship between said respective corresponding consecutive Fourier transformed frames (F1, F2), and in particular based on translational, rotational and/or scaling properties of the Fourier transforming process.

Abstract: Receivers (1) for receiving frequency signals are, to improve their time synchronization accuracy, provided with synchronization stages (20) for performing a coarse time synchronization through autocorrelating samples of a group of preamble symbols (t1,t2,t3) and a fine time synchronization through crosscorrelating samples of a further group of preamble symbols (t10,G1) with predefined samples. The synchronization stages (20) also perform a coarse and a fine frequency synchronization through detecting and accumulating phases of samples of a yet further group of preamble symbols (t8,t9) and of another group of preamble symbols (T1,T2). The synchronization stages (20) have buffering units (21) and controlling units (22) for controlling mixing units (11) and transformating units (12) in processing stages (10). The preamble symbols have ten short preamble symbols (t1-t10), a guard interval preamble symbol (G 1) and two training symbols (T 1,T2).

Abstract: A clock generator circuit for generating synchronization signals for a multiple chip system. The clock generator circuit comprises generation of a synchronization signal from a reference clock and chip global clock with edge detection logic. In high performance server system design with multiple chips, a common practice for server systems is to use feedback clock and delayed reference clock to generate the synchronization signal. The generated synchronization signal is transferred to latches clocked by the global clock to be used for chip synchronization functions. As the system clock frequency is pushed higher, the phase difference between generated synchronization signal clocked by feedback clock and receiving latch clocked by global clock is becoming such a large portion of cycle time that this signal cannot be transferred deterministically.

Abstract: Provided are a transmission device, a receiving device, and a communication system having a simple configuration and capable of reliably executing the confirmation of a changed bit rate. The communication system 1 sends, to the receiving device 3, a serial data signal Sdata that is set as a constant value across a period of a constant multiple of a cycle of the clock when a bit rate of a serial data signal Sdata in the transmission device 2 is changed. The receiving device 3 that received the serial data signal Sdata receives training data Tdata from the transmission device 2 when it is determined that the serial data signal Sdata is a constant value across a period of a constant multiple of a cycle of the clock, and proceeds to the processing of confirming the changed bit rate.

Abstract: A modulator, and demodulator, apparatus and method for use in a multiple sub-channel communication system is taught. A commutator is employed for fractionally sampling, or distributing, signals from, or to, a multiple channel polyphase filter. The filter is coupled with a discrete Fourier transform, or its inverse, such that the relationship between the base-band sampling rate of a plurality of sub-channel signals, the frequency spacing of the sub-channel signals, and the sampling rate of a composite signal can be related by any rational number, thereby freeing designers to optimize system design respecting channel spacing, bandwidth, and signaling rates. The advantages of the present invention are realized by adjusting the interpolation and decimation rates of the filter, and by adjusting the resolution and decimation rates of the transform.