Abstract: The present invention relates to an enhancement normally off nitride semiconductor device and a method of manufacturing the same. The method includes the steps of: forming a buffer layer on a substrate; forming a first nitride semiconductor layer on the buffer layer; forming a second nitride semiconductor layer on the first nitride semiconductor layer; etching a gate region above the second nitride semiconductor layer up to a predetermined depth of the first nitride semiconductor layer; forming an insulating film on the etched region and the second nitride semiconductor layer; patterning a source/drain region, etching the insulating film in the source/drain region, and forming electrodes in the source/drain region; and forming a gate electrode on the insulating film in the gate region. In this manner, the present invention provides a method of easily implementing a normally off enhancement semiconductor device by originally blocking 2DEG which is generated under a gate region.

Abstract: A semiconductor device includes: substrate region; a gate electrode, a source electrode, and a drain electrode which are placed on a first surface of the substrate regions; an active area between gate and source placed between the gate electrode and the source electrode; an active area between gate and drain placed between the gate electrode and the drain electrode; an active area placed on the substrate region of the underneath part of the gate electrode, the source electrode, and the drain electrode; and a non-active area placed adjoining the active area, the active area between gate and source, and the active area between gate and drain. Furthermore, width WA1 of the active area between gate and source is wider than width WA2 of the active area between gate and drain. Channel resistance of an active area between source and gate placed between a gate electrode and a source electrode is reduced, and high-frequency performance is provided.

Abstract: A nitride semiconductor device includes: a main semiconductor region comprising a first nitride semiconductor layer having a first band gap, and a second nitride semiconductor layer having a second band gap larger than the first band gap, a heterojunction being formed between the first nitride semiconductor layer and a the second nitride semiconductor layer such that two-dimensional electron gas layer can be caused inside the first nitride semiconductor layer based on the heterojunction; a source electrode formed on the main semiconductor region; a drain electrode formed on the main semiconductor region and separated from the source electrode; a third nitride semiconductor layer formed on the first nitride semiconductor layer and between the source electrode and the drain electrode; and a gate electrode formed on the third nitride semiconductor layer. The third nitride semiconductor layer has a third band gap smaller than the first band gap.

Abstract: There is provided a semiconductor device and a method of manufacturing the same.

Abstract: A method for manufacturing a III-V CMOS device is disclosed. The device includes a first and second main contact and a control contact. In one aspect, the method includes providing the control contact by using damascene processing. The method thus allows obtaining a control contact with a length of between about 20 nm and 5 ?m and with good Schottky behavior. Using low-resistive materials such as Cu allows reducing the gate resistance thus improving the high-frequency performance of the III-V CMOS device.

Abstract: An integrated optical waveguide has a first optical waveguide, a second optical waveguide, and a groove. The second optical waveguide is coupled to the first optical waveguide and has a refractive index that is different from the first optical waveguide. The groove is disposed so as to traverse an optical path of the first optical waveguide and is separated from an interface between the first optical waveguide and the second optical waveguide by a predetermined spacing. The spacing from the interface and the width of the groove are determined such that reflection at a boundary between the first optical waveguide and the second optical waveguide is weakened. A semiconductor board may be disposed at a boundary between the first optical waveguide and the second optical waveguide.

Abstract: A new devices structure of nano tunneling field effect transistor based on nano metal particles is introduced. The nano semiconductor device, comprising a source and a drain, wherein each of the source and drain comprise an implanted nano cluster of metal atoms, wherein the implanted nano cluster of metal atoms forming the source has an average radius in the range from about 1 to about 2 nanometers, and the implanted nano cluster of metal atoms forming the drain has an average radius in the range from about 2 to about 4 nanometers. Processes for producing the nano semiconductor device are detailed.

Abstract: Fabrication methods of a high frequency (sub-micron gate length) operation of AlInGaN/InGaN/GaN MOS-DHFET, and the HFET device resulting from the fabrication methods, are generally disclosed. The method of forming the HFET device generally includes a novel double-recess etching and a pulsed deposition of an ultra-thin, high-quality silicon dioxide layer as the active gate-insulator. The methods of the present invention can be utilized to form any suitable field effect transistor (FET), and are particular suited for forming high electron mobility transistors (HEMT).

Abstract: An aspect of the present invention inheres in a semiconductor device includes a semiconductor region, a source electrode and a drain electrode, which are provided on a main surface of the semiconductor region, a gate electrode exhibiting normally-off characteristics, the gate electrode being provided above the main surface of the semiconductor region while interposing a p-type material film therebetween, and being arranged between the source electrode and the drain electrode, and a fourth electrode that is provided on the main surface of the semiconductor region, and is arranged between the gate electrode and the drain electrode.

Abstract: A semiconductor device includes a carrier transit layer above a substrate, a carrier supply layer above the carrier transit layer, an etching stopper layer above the carrier supply layer, the etching stopper layer being coupled to a gate electrode, and a cap layer above the etching stopper layer, the cap layer being coupled to each of a source electrode and a drain electrode and having a conduction band energy lower than that of the etching stopper layer, wherein a portion of the etching stopper layer on the cap layer includes Silicon.

Abstract: A method for fabricating a Schottky device includes the following sequences. First, a substrate with a first conductivity type is provided and an epitaxial layer with the first conductivity type is grown on the substrate. Then, a patterned dielectric layer is formed on the epitaxial layer, and a metal silicide layer is formed on a surface of the epitaxial layer. A dopant source layer with a second conductivity type is formed on the metal silicide layer, followed by applying a thermal drive-in process to diffuse the dopants inside the dopant source layer into the epitaxial layer. Finally, a conductive layer is formed on the metal silicide layer.

Abstract: A display apparatus includes a thin film transistor provided on a substrate and a pixel electrically coupled to the thin film transistor. The thin film transistor includes a semiconductor layer on the substrate, a first insulating layer on the semiconductor layer and having a first contact hole and a second contact hole, a source electrode on the first insulating layer and making contact with the semiconductor layer through the first contact hole, a drain electrode on the first insulating layer and making contact with the semiconductor layer through the second contact hole, a gate electrode between the source electrode and the drain electrode and having a stacked structure including a first conductive layer and a second conductive layer, and a second insulating layer between the source electrode and the drain electrode and covering the gate electrode.

Abstract: A semiconductor device includes a substrate; a nitride based compound semiconductor layer placed on the substrate; an active area which is placed on the nitride based compound semiconductor layer, and is composed of an aluminum gallium nitride layer (AlxGa1-xN) (where 0.1<=x<=1); an isolation region which performs isolation of the active area mutually; a gate electrode, a source electrode, and a drain electrode which have been placed on the active area surrounded by the isolation region; and a trench region formed by etching for a part of the active area under the gate electrode. The semiconductor device is highly reliable, high performance and high power and a fabrication method for the same is also provided.

Abstract: A method for manufacturing a semiconductor device includes: forming a first active region, a second active region, an inactive region located between the first active region and the second active region, and a third active region, which crosses the inactive region to electrically connect the first active region to the second active region, in a semiconductor layer; forming an insulating layer on the semiconductor layer; and forming an opening selectively in the insulating layer by dry etching.

Abstract: Embodiments of the present disclosure describe structural configurations of an integrated circuit (IC) device such as a high electron mobility transistor (HEMT) switch device and method of fabrication. The IC device includes a buffer layer formed on a substrate, a channel layer formed on the buffer layer to provide a pathway for current flow in a transistor device, a spacer layer formed on the channel layer, a barrier layer formed on the spacer layer, the barrier layer including aluminum (Al), nitrogen (N), and at least one of indium (In) or gallium (Ga), a gate dielectric directly coupled with the spacer layer or the channel layer, and a gate formed on the gate dielectric, the gate being directly coupled with the gate dielectric. Other embodiments may also be described and/or claimed.

Abstract: Disclosed are embodiments of a field effect transistor (FET) having decreased drive current temperature sensitivity. Specifically, any temperature-dependent carrier mobility change in the FET channel region is simultaneously counteracted by an opposite strain-dependent carrier mobility change to ensure that drive current remains approximately constant or at least within a predetermined range in response to temperature variations. This opposite strain-dependent carrier mobility change is provided by a straining structure that is configured to impart a temperature-dependent amount of a pre-selected strain type on the channel region. Also disclosed are embodiments of an associated method of forming the field effect transistor.

Abstract: Provided is an epitaxial substrate capable of achieving a semiconductor device that has excellent schottky contact characteristics as well as satisfactory device characteristics. On a base substrate, a channel layer formed of a first group III nitride that contains at least Al and Ga and has a composition of Inx1Aly1Gaz1N (x1+y1+z1=1) is formed. On the channel layer, a barrier layer formed of a second group III nitride that contains at least In and Al and has a composition of Inx2Aly2Gaz2N (x2+y2+z2=1) is formed such that an In composition ratio of a near-surface portion is smaller than an In composition ratio of a portion other than the near-surface portion.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a first layer. A second layer is disposed on the first layer and different from the first layer in composition. An interface is between the first layer and the second layer. A third layer is disposed on the second layer. A gate is disposed on the third layer. A source feature and a drain feature are disposed on opposite sides of the gate. Each of the source feature and the drain feature includes a corresponding metal feature at least partially embedded in the second and the third layer. A corresponding intermetallic compound underlies each metal feature. Each intermetallic compound contacts a carrier channel located at the interface.

Abstract: A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.

Abstract: The mechanisms of forming SiC crystalline regions on Si substrate described above enable formation and integration of GaN-based devices and Si-based devices on a same substrate. The SiC crystalline regions are formed by implanting carbon into regions of Si substrate and then annealing the substrate. An implant-stop layer is used to cover the Si device regions during formation of the SiC crystalline regions.

Abstract: A method of fabricating a GaN HEMT includes growing a first epitaxial layer on a substrate, growing a second epitaxial layer on the first epitaxial layer, growing a third epitaxial layer on the second epitaxial layer, depositing a first dielectric film on the third epitaxial layer, using dielectric films to form a first sidewall dielectric spacer, forming a sidewall gate adjacent the first sidewall dielectric spacer. The sidewall gate may be made to be less than 50 nm in length.

Abstract: A transistor includes a semiconductor channel disposed nearby a gate and in an electrical path between a source and a drain, wherein the channel and at least one of the source or the drain are separated by an interface layer so as to form a channel-interface layer-source/drain junction in which a Fermi level of the semiconductor channel is depinned in a region near the junction and the junction has a specific contact resistance of less than approximately 1000 ?-?m2. The interface layer may include a passivating material such as a nitride, a fluoride, an oxide, an oxynitride, a hydride and/or an arsenide of the semiconductor of the channel. In some cases, the interface layer consists essentially of a monolayer configured to depin the Fermi level of the semiconductor of the channel, or an amount of passivation material sufficient to terminate all or a sufficient number of dangling bonds of the semiconductor channel to achieve chemical stability of the surface.

Abstract: A III-V-group compound semiconductor device includes a substrate, a channel layer provided over the substrate, a barrier layer provided on the channel layer so as to form a hetero-interface, a plurality of electrodes provided on the barrier layer, an insulator layer provided to cover an entire upper surface of the barrier layer except for at least partial regions of the electrodes, and a hydrogen-absorbing layer stacked on the insulator layer or an integrated layer in which an hydrogen-absorbing layer is integrated with the insulator layer.

Abstract: Electronic field effect devices, and methods of manufacture of these electronic field effect devices are disclosed. In particular, there is disclosed an electronic field effect device which has improved electrical properties due to the formation of a highly mobile two-dimensional charge-carrier gas in a simple structure formed from diamond in combination with polar materials.

Abstract: Methods and apparatuses for forming a device structure including a high-thermal-conductivity substrate are disclosed herein. A method forming such a device structure may comprise forming an active layer over a first substrate in a manner such that a frontside of the active layer faces the first substrate and a backside of the active layer faces away from the first substrate, forming a second substrate over the backside of the active layer, and removing the first substrate to expose the frontside of the active layer. Other embodiments are described and claimed.

Abstract: A bulk GaN layer is on a first surface of a substrate, wherein the bulk GaN layer has a GaN transistor region and a bulk acoustic wave (BAW) device region. A source/drain layer is over a first surface of the bulk GaN layer in the GaN transistor region. A gate electrode is formed over the source/drain layer. A first BAW electrode is formed over the first surface of the bulk GaN layer in the BAW device region. An opening is formed in a second surface of the substrate, opposite the first surface of the substrate, which extends through the substrate and exposes a second surface of the bulk GaN layer, opposite the first surface of the bulk GaN layer. A second BAW electrode is formed within the opening over the second surface of the bulk GaN layer.

Abstract: A process for fabricating a semiconductor device. The process including (a) growing a channel layer on a buffer layer, (b) growing a barrier layer on the channel layer, (c) epitaxially growing a quaternary etch-stop layer on the barrier layer, (d) growing a first contact layer on the quaternary etch-stop layer, (e) growing a second contact layer on the first contact layer, (f) etching portions of the second contact layer to reveal a first recess surface, and (g) etching portions of the first contact layer to reveal a second recess surface. The second contact layer may be a highly doped contact layer. The second recess surface generally forms a gate region. The first and the second contact layers have a first etch rate and the quaternary etch-stop layer has a second etch rate in a chosen first etch chemistry.

Abstract: This invention discloses a bottom-anode Schottky (BAS) diode that includes an anode electrode disposed on a bottom surface of a semiconductor substrate. The bottom-anode Schottky diode further includes a sinker dopant region disposed at a depth in the semiconductor substrate extending substantially to the anode electrode disposed on the bottom surface of the semiconductor and the sinker dopant region covered by a buried Schottky barrier metal functioning as a Schottky anode.

Abstract: There is provided a semiconductor device including: a SiC substrate; an AlGaN layer formed on the SiC substrate; a source electrode and a drain electrode formed on the AlGaN layer so as to be spaced from each other; a first insulation film formed between the source electrode and the drain electrode and having a band-like opening parallel to the drain electrode and the source electrode; a gate electrode formed at the opening in the first insulation film; a second insulation film formed on the first insulation film in such a manner as to cover a surface of the gate electrode; and a source field plate electrode which is formed on the second insulation film and the source electrode and an end portion of which on the drain electrode side is spaced from the second insulation film, thereby suppressing degradation in device performance.

Abstract: A semiconductor device includes a nitride semiconductor stacked structure including a carrier transit layer and a carrier supply layer; a p-type nitride semiconductor layer provided over the nitride semiconductor stacked structure and including an active region and an inactive region; an n-type nitride semiconductor layer provided on the inactive region in the p-type nitride semiconductor layer; and a gate electrode provided over the active region in the p-type nitride semiconductor layer.

Abstract: A shallow p-n junction diffusion layer having a high activation rate of implanted ions, low resistivity, and a controlled leakage current is formed through annealing. Annealing after impurities have been doped is carried out through light irradiation. Those impurities are activated by annealing at least twice through light irradiation after doping impurities to a semiconductor substrate 11. The light radiations are characterized by usage of a W halogen lamp RTA or a flash lamp FLA except for the final light irradiation using a flash lamp FLA. Impurity diffusion may be controlled to a minimum, and crystal defects, which have developed in an impurity doping process, may be sufficiently reduced when forming ion implanted layers in a source and a drain extension region of the MOSFET or ion implanted layers in a source and a drain region.

Abstract: Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a doped silicon-carbide gate, while other embodiments include a JFET with a metal gate. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.

Abstract: An aspect of the present invention inheres in a semiconductor device includes a semiconductor region, a source electrode and a drain electrode, which are provided on a main surface of the semiconductor region, a gate electrode exhibiting normally-off characteristics, the gate electrode being provided above the main surface of the semiconductor region while interposing a p-type material film therebetween, and being arranged between the source electrode and the drain electrode, and a fourth electrode that is provided on the main surface of the semiconductor region, and is arranged between the gate electrode and the drain electrode.

Abstract: A method for manufacturing an integrated circuit structure is disclosed. First, a dielectric layer is formed on a substrate, the substrate has a transistor region and a diode region. Next, a contact hole and an opening are formed in the dielectric layer, a size of the opening being larger than that of the contact hole. Next, a first metal layer is formed on the dielectric layer and filled into the contact hole and the opening. Next, a portion of the first metal layer is removed to form a contact plug above the transistor region and form a metal spacer on a sidewall of the opening. Next, an ion implantation process is performed to form a lightly doped region in the substrate at a bottom of the opening. Finally, a contact metal layer is formed on the lightly doped region.

Abstract: An Enhancement-mode (E-mode) high electron mobility transistor (HEMT) includes a channel layer with a 2-Dimensional Electron Gas (2DEG), a barrier layer inducing the 2DEG in the channel layer, source and drain electrodes on the barrier layer, a depletion layer on the barrier layer between the source and drain electrodes, and a gate electrode on the depletion layer. The barrier layer is recessed below the gate electrode and the depletion layer covers a surface of the recess and extends onto the barrier layer around the recess.

Abstract: Various embodiments of the disclosure include the formation of enhancement-mode (e-mode) gate injection high electron mobility transistors (HEMT). Embodiments can include GaN, AlGaN, and InAlN based HEMTs. Embodiments also can include self-aligned P-type gate and field plate structures. The gates can be self-aligned to the source and drain, which can allow for precise control over the gate-source and gate-drain spacing. Additional embodiments include the addition of a GaN cap structure, an AlGaN buffer layer, AlN, recess etching, and/or using a thin oxidized AlN layer. In manufacturing the HEMTs according to present teachings, selective epitaxial growth (SEG) and epitaxial lateral overgrowth (ELO) can both be utilized to form gates.

Abstract: A method of making a semiconductor device includes forming a p-type semiconductor region to an n-type semiconductor substrate in such a manner that the p-type semiconductor region is partially exposed to a top surface of the semiconductor substrate, forming a Schottky electrode of a first material in such a manner that the Schottky electrode is in Schottky contact with an n-type semiconductor region exposed to the top surface of the semiconductor substrate, and forming an ohmic electrode of a second material different from the first material in such a manner that the ohmic electrode is in ohmic contact with the exposed p-type semiconductor region. The Schottky electrode is formed earlier than the ohmic electrode.

Abstract: An optical device includes a first electrode of a first conductivity type, and a second electrode of a second conductivity type. A nanowire is positioned between the first and second electrodes. The nanowire has at least two segments and a junction region formed between the at least two segments. One of the segments is the first conductivity type and the other of the segments is the second conductivity type. At least one of the at least two segments has a predetermined characteristic that affects optical behavior of the junction region.

Abstract: A semiconductor device 1 includes a substrate 2 having on a main surface thereof a central area and a peripheral area which surrounds the central area and is exposed, a semiconductor layer 4 which is formed on the main surface of the substrate 2, is made of a material harder than the substrate 2, is in the shape of a mesa, and has a steep side over the exposed peripheral area, and an insulating film 12S provided on a side surface of the semiconductor layer 4.

Abstract: A semiconductor component that includes a Schottky device, an edge termination structure, a non-Schottky semiconductor device, combinations thereof and a method of manufacturing the semiconductor component. A semiconductor material includes a first epitaxial layer disposed on a semiconductor substrate and a second epitaxial layer disposed on the first epitaxial layer. The second epitaxial layer has a higher resistivity than the semiconductor substrate. A Schottky device and a non-Schottky semiconductor device are manufactured from the second epitaxial layer. In accordance with another embodiment, a semiconductor material includes an epitaxial layer disposed over a semiconductor substrate. The epitaxial layer has a higher resistivity than the semiconductor substrate. A doped region is formed in the epitaxial layer. A Schottky device and a non-Schottky semiconductor device are manufactured from the epitaxial layer.

Abstract: A semiconductor device includes a substrate; a nitride based compound semiconductor layer placed on the substrate; an active area which is placed on the nitride based compound semiconductor layer, and is composed of an aluminum gallium nitride layer (AlxGa1-xN) (where 0.1<=x<=1); an isolation region which performs isolation of the active area mutually; a gate electrode, a source electrode, and a drain electrode which have been placed on the active area surrounded by the isolation region; and a trench region formed by etching for a part of the active area under the gate electrode. The semiconductor device is highly reliable, high performance and high power and a fabrication method for the same is also provided.

Abstract: A semiconductor device has: a semiconductor substrate having a pair of current input/output regions via which current flows; an insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed on the semiconductor substrate via the gate electrode opening, the mushroom gate electrode structure having a stem and a head formed on the stem, the stem having a limited size on the semiconductor substrate along a current direction and having a forward taper shape upwardly and monotonically increasing the size along the current direction, the head having a size expanded stepwise along the current direction, and the stem contacting the semiconductor substrate in the gate electrode opening and riding the insulating film near at a position of at least one of opposite ends of the stem along the current direction.

Abstract: A nitride semiconductor device includes: a semiconductor base layer made of a conductive group III nitride semiconductor having a principal plane defined by a nonpolar plane or a semipolar plane; an insulating layer formed on the principal plane of the semiconductor base layer with an aperture partially exposing the principal plane; a nitride semiconductor multilayer structure portion, formed on a region extending onto the insulating layer from the aperture, having a parallel surface parallel to the principal plane of the semiconductor base layer as well as a +c-axis side first inclined surface and a ?c-axis side second inclined surface inclined with respect to the principal plane of the semiconductor base layer and including two types of group III nitride semiconductor layers at least having different lattice constants; a gate electrode formed to be opposed to the second inclined surface; a source electrode arranged to be electrically connected with the group III nitride semiconductor layers; and a drain ele

Abstract: A compound semiconductor device includes a substrate having an opening formed from the rear side thereof; a compound semiconductor layer disposed over the surface of the substrate; a local p-type region in the compound semiconductor layer, partially exposed at the end of the substrate opening; and a rear electrode made of a conductive material, disposed in the substrate opening so as to be connected to the local p-type region.

Abstract: Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a doped silicon-carbide gate, while other embodiments include a JFET with a metal gate. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.

Abstract: A fluorine treatment that can shape the electric field profile in electronic devices in 1, 2, or 3 dimensions is disclosed. A method to increase the breakdown voltage of AlGaN/GaN high electron mobility transistors, by the introduction of a controlled amount of dispersion into the device, is also disclosed. This dispersion is large enough to reduce the peak electric field in the channel, but low enough in order not to cause a significant decrease in the output power of the device. In this design, the whole transistor is passivated against dispersion with the exception of a small region 50 to 100 nm wide right next to the drain side of the gate. In that region, surface traps cause limited amounts of dispersion, that will spread the high electric field under the gate edge, therefore increasing the breakdown voltage.

Abstract: In a method of forming a gate recess, on a surface of an epitaxial wafer including an epitaxial substrate, having a semiconductor layer having the band gap energy varying therein in the depth-wise direction, and a SiN surface protective layer, having a sidewall forming a gate opening and coating the surface of the epitaxial substrate, ultraviolet light having its energy equivalent to the band gap energy of the specific semiconductor layer is irradiated, while the specific semiconductor layer is photoelectrochemically etched from the gate opening with the SiN surface protective layer used as a mask. The gate recess free from plasma ion-induced damage is thus obtained.

Abstract: A low Schottky barrier semiconductor structure is provided, comprising: a substrate; a SiGe layer with low Ge content formed on the substrate; a channel layer with high Ge content formed on the SiGe layer; a gate stack formed on the substrate and a side wall of one or more layers formed on both sides of the gate stack; a metal source and a metal drain formed in the channel layer and on the both sides of the gate stack respectively; and an insulation layer formed between the substrate and the metal source and between the substrate and the metal drain respectively.

Abstract: A transistor device sequentially comprises a semiconductor substrate, a drain, a source, a gate metal seed layer and a gate Schottky contact. The gate metal seed layer comprises a gelatinous substance layer and multiple metal seed crystals. A manufacture method comprises steps of providing a semiconductor substrate; forming a drain and a source; forming a patterned photoresist layer with a photolithography to define a gate area on the semiconductor substrate; forming a gate metal seed layer on the semiconductor substrate with a sensitization process and an activation process; and forming a gate Schottky contact on the gate metal seed layer with an electroless plating approach.

Abstract: Schottky barrier semiconductor devices are provided including a wide bandgap semiconductor layer and a gate on the wide bandgap semiconductor layer. The gate includes a metal layer on the wide bandgap semiconductor layer including a nickel oxide (NiO) layer. Related methods of fabricating devices are also provided herein.